CN102208451B - Metal insulated gate field effect transistor structure for high-voltage integrated circuit and preparation method thereof - Google Patents
Metal insulated gate field effect transistor structure for high-voltage integrated circuit and preparation method thereof Download PDFInfo
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- CN102208451B CN102208451B CN 201110139814 CN201110139814A CN102208451B CN 102208451 B CN102208451 B CN 102208451B CN 201110139814 CN201110139814 CN 201110139814 CN 201110139814 A CN201110139814 A CN 201110139814A CN 102208451 B CN102208451 B CN 102208451B
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Abstract
The invention discloses a metal insulated gate field effect transistor structure for a high-voltage integrated circuit. The structure comprises a P-type substrate and a P-type epitaxial layer, wherein a P-type isolated well region, an N-type isolated well region, a P-type back gate region and a high-voltage N-type well region are formed on the P-type epitaxial layer; and an N-type source region is formed in the P-type back gate region. The structure is characterized in that: an N-type buried layer is arranged below the P-type back gate region; two ends of the N-type buried layer are connected with the N-type isolated well region and the high-voltage N-type well region respectively; a first source end N-type buffer layer and a second source end N-type buffer layer are arranged on two sides of the N-type source region; and a P-type back gate metal connecting line and a source metal connecting line are connected to the P-type back gate contact region and the N-type source region respectively. According to the structure, the problem of substrate current which is ubiquitous in the traditional bootstrap diode is solved, the charging speed of a bootstrap capacitor is improved, and the dynamic property of a driving circuit is improved.
Description
Technical field
The present invention relates to the high voltage half-bridge drive circuit in the field of high voltage power semiconductor devices, is metal-insulator gate field-effect tubular construction and the preparation method who can be used for high voltage integrated circuit about a kind of.
Background technology
The high voltage half-bridge drive circuit can be used for various application, such as the electric ballast in motor-driven, the fluorescent lamp and power supply etc.The high side direct voltage source of half-bridge circuit is unsteady with respect to the downside direct voltage source, therefore need to derive high side direct voltage source with boostrap circuit.Boostrap circuit comprises a bootstrap capacitor and a bootstrap diode, to such an extent as to but since the required electric capacity of boostrap circuit and puncture voltage and the peak current capacity of bootstrap diode be difficult to be integrated on the half-bridge driven chip too greatly, in at present many half-bridge drive circuits, bootstrap capacitor and bootstrap diode are made of discrete component.
US Patent No. 6507085 and US7518209 are integrated in bootstrap diode and drive on the chip, it is integrated in bootstrap diode on the outer or shading ring of the shading ring of drive circuit, compared with in the past discrete bootstrap diode, integrated diode has reduced production cost.Yet, exist parasitic triode to open problem during this integrated diode conducting, produce very large substrate leakage current, thereby affect the stability of whole circuit, the simultaneously generation of leakage current also can have influence on the charging rate of bootstrap capacitor, so that the dynamic characteristic variation of drive circuit.
A kind of bootstrap diode emulator of US Patent No. 5502632 usefulness replaces bootstrap diode to be integrated in the driving chip.Bootstrap diode emulator is comprised of a kind of LDMOS (being integrated bootstrapping metal-insulator gate field-effect transistor, hereinafter to be referred as integrated bootstrapping MOSFET) of special construction and the drive circuit of its periphery, and they can substitute bootstrap diode and use.Integrated bootstrapping MOSFET is made on the isolation strip of high/low-basin, and its realization does not need extra area, only needs the drive circuit of the integrated bootstrapping MOSFET of a small size of increase to get final product.Bootstrap diode emulator has suppressed the parasitic triode unlatching, thereby has solved the substrate leakage flow problem.Yet patent US5502632 has just introduced the bootstrap diode emulator circuit, to the structure of integrated bootstrapping MOSFET but without introducing, integrated bootstrapping MOSFET is a kind of LDMOS that specific (special) requirements is arranged, take NLDMOS as example, during forward conduction, source connects high potential, so source need to be high pressure resistant, and back grid needs separately biasing.
Summary of the invention
The invention provides a kind of metal-insulator gate field-effect tubular construction for high voltage integrated circuit and preparation method thereof, this STRUCTURE DEPRESSION the parasitic triode unlatching, greatly reduced substrate leakage current, thereby improved the charging rate of bootstrap capacitor, improve the dynamic characteristic of drive circuit, reduced integrated area.
The present invention adopts following technical scheme:
A kind of metal-insulator gate field-effect tubular construction for high voltage integrated circuit, comprise: P type substrate, be provided with p type buried layer and dark N-type well region on the upper left surface of P type substrate, at P type substrate, the upper surface of dark N-type well region and p type buried layer is provided with P type epitaxial loayer, be provided with P type isolation well region at p type buried layer, be provided with the upper area that high-pressure N-shaped well region and high-pressure N-shaped well region extend and enter P type substrate at dark N-type well region, in high-pressure N-shaped well region, be provided with drain terminal N-type buffering area, between P type isolation well region and high-pressure N-shaped well region, be provided with N-type isolation well region and P type back gate region, and, a border of N-type isolation well region contacts with P type isolation well region, a border of P type back gate region contacts with high-pressure N-shaped well region, another border of N-type isolation well region contacts with another borderline phase of P type back gate region, in P type isolation well region, be provided with P type isolation contact zone, in P type back gate region, be provided with P type back of the body gate contact zone and N-type source region, in drain terminal N-type buffering area, be provided with the N-type drain region, public boundary at P type back gate region and high-pressure N-shaped well region is provided with gate oxide, in P type isolation well region, the N-type isolation well region, the P type isolation contact zone of P type back gate region and high-pressure N-shaped well region top, P type back of the body gate contact zone, the N-type source region, zone beyond gate oxide and the top, N-type drain region is provided with field oxide, being provided with polysilicon gate and polysilicon gate at gate oxide extends to above the field oxide above the high-pressure N-shaped well region, be provided with the medium isolating oxide layer at field oxide and polysilicon gate, on P type isolation contact zone and N-type drain region, be connected with respectively P type isolated area metal connecting line and drain metal line, it is characterized in that, below P type back gate region, be provided with n type buried layer, the two ends of described n type buried layer stretch out respectively and respectively with the N-type isolation well region, high-pressure N-shaped well region connects, between P type back of the body gate contact zone and N-type source region, be provided with the first source N-type resilient coating, above the first source N-type resilient coating, be provided with the first thin field oxide, between N-type source region and gate oxide, be provided with the second source N-type resilient coating, above the second source N-type resilient coating, be provided with the second thin field oxide, be connected with respectively P type back grid metal connecting line and source metal line at P type back of the body gate contact zone and N-type source region.
Described metal-insulator gate field-effect tubular construction preparation method for high voltage integrated circuit is as follows:
The first step: prepare P type silicon substrate,
Second step: growth oxide layer, deposit silicon nitride, photoetching, Implantation antimony generate n type buried layer; Photoetching, Implantation phosphorus generate dark N-type well region, annealing; Remove silicon nitride, photoetching, boron ion implantation generate p-type buried regions, annealing,
The 3rd step: growing P-type epitaxial loayer; Growth oxide layer, deposit silicon nitride, photoetching, Implantation phosphorus generate high-pressure N-shaped well region; Photoetching, Implantation phosphorus generate N-type isolation well region and drain terminal N-type buffering area, oxidation, generate 5000 oxide layer at the upper surface of high pressure N trap and low pressure N trap; Remove silicon nitride,
The 4th step: general notes boron ion generation P type isolation well region and P type back gate region, annealing; Remove above-mentioned 5000 oxide layer,
The 5th step: deposit silicon nitride, Implantation phosphorus generate the first source N-type resilient coating and the second source N-type resilient coating; Oxidation generates the first thin field oxide and the second thin field oxide; Remove silicon nitride,
The 6th step: the growth field oxide,
The 7th step: growth a layer thickness is 1000 gate oxide, and Implantation boron fluoride threshold value is adjusted, and then carries out deposit, the etching of polysilicon gate,
The 8th step: photoetching, Implantation phosphorus and arsenic generate N-type source region and N-type drain region; Photoetching, Implantation boron fluoride generate P type isolation contact zone and P type back of the body gate contact zone; Deposit medium isolating oxide layer, contact hole etching, depositing metal aluminium, etching aluminium carries out the medium Passivation Treatment at last to form P type isolated area metal connecting line, P type back grid metal connecting line, source metal line and drain metal line.
Preparation method and the existing technique compatibility mutually that is used for the metal-insulator gate field-effect tubular construction of high voltage integrated circuit, and compared with prior art, the present invention has following advantage:
(1) in traditional integrated bootstrap diode structure, parasitic triode anode during the diode forward conducting/N-type extension/P type substrate conducting, produce substrate leakage current, substrate leakage current has a strong impact on the stability (with reference to figure 1) of whole drive circuit, and the source electrode of integrated bootstrapping MOSFET separates with back grid among the present invention, back grid is setovered separately, so that back grid/n type buried layer is anti-inclined to one side, thereby suppressed the conducting of parasitic triode back grid/n type buried layer/P type substrate, suppressed the generation of substrate leakage, improve the charging rate of bootstrap capacitor, thereby improved the dynamic characteristic (with reference to figure 4 and Fig. 6) of drive circuit.
(2) traditional integrated bootstrap diode structure, has larger forward voltage drop, conduction loss is large, bootstrap capacitor can not be charged to the downside supply voltage, and the integrated bootstrapping MOSFET among the present invention, forward voltage drop is little during low frequency, and conduction loss is little, and bootstrap capacitor can be charged to approximate downside supply voltage.
(3) with n type buried layer, high-pressure N-shaped well region and three N-type zones of N-type isolation well region P type back gate region and P type substrate are kept apart fully among the present invention, thereby can setover separately to back grid.
(4) during charging process, source electrode connects downside power end (with reference to figure 6), thereby source need to be born necessarily withstand voltage, and the both sides in N-type source region are provided with the first source N-type resilient coating and the second source N-type resilient coating among the present invention, can be so that source is born required withstand voltage.
(5) integrated bootstrap diode is so that drive the area of chip and greatly increase, the present invention can directly be made on the isolation strip of high/low-basin and not increase extra area, the control circuit that only need to increase on the basis of original driving chip by a small size gets final product, and has saved production cost.
Description of drawings
Fig. 1 is the structural representation of traditional integrated bootstrap diode.
Fig. 2 is the traditional connection diagram of integrated bootstrap diode in high-voltage driving circuit.
Fig. 3 is the vertical view of the integrated bootstrapping MOSFET of patent of the present invention in high-voltage driving circuit, high-voltage driving circuit is by the high-low pressure isolation strip (103) in the middle of high lateral circuit district (101), downside circuit region (102) and two districts thereof, integrated bootstrapping MOSFET(200) be positioned on the high-low pressure isolation strip (103).
Fig. 4 is that Fig. 3 is along I-I
,The profile of direction.As seen from the figure, have parasitic triode back grid/n type buried layer/P type substrate among the integrated bootstrapping MOSFET, and back of the body grid-control circuit processed (with reference to figure 6) can suppress the unlatching of this parasitic triode.
Fig. 5 is that Fig. 3 is along II-II
,The profile of direction.P type back gate region (10) needs to isolate fully with n type buried layer (2), high-pressure N-shaped well region (6) and (7) three N-type zones of N-type isolation well region, as shown in Figure 5, and isolation that realization is complete equally in 3 dimension spaces.
Fig. 6 is the connection diagram of integrated bootstrapping MOSFET in high-voltage driving circuit in the patent of the present invention, as seen from the figure, back grid is controlled separately, so that back grid/n type buried layer is anti-inclined to one side, thereby suppress the unlatching of parasitic triode back grid/n type buried layer/P type substrate, solved the substrate leakage problem that has parasitic triode to cause.
Fig. 7 is the preparation method's flow process of the integrated bootstrapping MOSFET in the patent of the present invention.
Embodiment
With reference to Fig. 4, structure of the present invention is elaborated, a kind of integrated bootstrapping MOSFET device for bootstrap diode emulator, comprise: P type substrate 1, be provided with p type buried layer 4 and dark N-type well region 3 on the upper left surface of P type substrate 1, at P type substrate 1, the upper surface of dark N-type well region 3 and p type buried layer 4 is provided with P type epitaxial loayer 5, be provided with P type isolation well region 9 at p type buried layer 4, be provided with the upper area that high-pressure N-shaped well region 6 and high-pressure N-shaped well region 6 extend and enter P type substrate 1 at dark N-type well region 3, in high-pressure N-shaped well region 6, be provided with drain terminal N-type buffering area 8, between P type isolation well region 9 and high-pressure N-shaped well region 6, be provided with N-type isolation well region 7 and P type back gate region 10, and, a border of N-type isolation well region 7 contacts with P type isolation well region 9, a border of P type back gate region 10 contacts with high-pressure N-shaped well region 6, another border of N-type isolation well region 7 contacts with another borderline phase of P type back gate region 10, in P type isolation well region 9, be provided with P type isolation contact zone 17, in P type back gate region 10, be provided with P type back of the body gate contact zone 18 and N-type source region 19, in drain terminal N-type buffering area 8, be provided with N-type drain region 20, public boundary at P type back gate region 10 and high-pressure N-shaped well region 6 is provided with gate oxide 15, in P type isolation well region 9, N-type isolation well region 7, the P type isolation contact zone 17 of P type back gate region 10 and high-pressure N-shaped well region 6 tops, P type back of the body gate contact zone 18, N-type source region 19, zone beyond gate oxide 15 and 20 tops, N-type drain region is provided with field oxide 13, being provided with polysilicon gate 16 and polysilicon gate 16 at gate oxide 15 extends to above the field oxide above the high-pressure N-shaped well region 6, be provided with medium isolating oxide layer 21 at field oxide 13 and polysilicon gate 16, on P type isolation contact zone 17 and N-type drain region 20, be connected with respectively P type isolated area metal connecting line 22 and drain metal line 25, it is characterized in that, below P type back gate region 10, be provided with n type buried layer 2, the two ends of described n type buried layer 2 stretch out respectively and respectively with N-type isolation well region 7, high-pressure N-shaped well region 6 connects, between P type back of the body gate contact zone 18 and N-type source region 19, be provided with the first source N-type resilient coating 11, above the first source N-type resilient coating 11, be provided with the first thin field oxide 11', between N-type source region 19 and gate oxide 15, be provided with the second source N-type resilient coating 12, above the second source N-type resilient coating 12, be provided with the second thin field oxide 12', on P type back of the body gate contact zone 18 and N-type source region 19, be connected with respectively P type back grid metal connecting line 23 and source metal line 24.
Above-mentioned n type buried layer 2 right-hand members extend to the lower-left end 0.5-3 μ m that surpasses high-pressure N-shaped well region 6.
With reference to Fig. 7, the preparation method of the metal-insulator gate field-effect tubular construction of mesohigh integrated circuit of the present invention is described in detail:
The first step: prepare P type silicon substrate 1,
Second step: growth oxide layer, deposit silicon nitride, photoetching, Implantation antimony generate n type buried layer 2; Photoetching, Implantation phosphorus generate dark N-type well region 3, annealing; Remove silicon nitride, photoetching, boron ion implantation generate p-type buried regions 4, annealing,
The 3rd step: growing P-type epitaxial loayer 5; Growth oxide layer, deposit silicon nitride, photoetching, Implantation phosphorus generate high-pressure N-shaped well region 6; Photoetching, Implantation phosphorus generate N-type isolation well region 7 and drain terminal N-type buffering area 8, oxidation, generate 5000 oxide layer at the upper surface of high pressure N trap and low pressure N trap; Remove silicon nitride,
The 4th step: general notes boron ion generates P type isolation well region 9 and P type back gate region 10, anneals; Remove above-mentioned 5000 oxide layer,
The 5th step: deposit silicon nitride, Implantation phosphorus generate the first source N-type resilient coating 11 and the second source N-type resilient coating 12; Oxidation generates the first thin field oxide 11' and the second thin field oxide 12'; Remove silicon nitride,
The 6th step: growth field oxide 13,
The 7th step: growth a layer thickness is 1000 gate oxide 15, and Implantation boron fluoride threshold value is adjusted, and then carries out deposit, the etching of polysilicon gate 16,
The 8th step: photoetching, Implantation phosphorus and arsenic generate N-type source region 19 and N-type drain region 20; Photoetching, Implantation boron fluoride generate P type isolation contact zone 17 and P type back of the body gate contact zone 18; Deposit medium isolating oxide layer 21, contact hole etching, depositing metal aluminium, etching aluminium carries out the medium Passivation Treatment at last to form P type isolated area metal connecting line 22, P type back grid metal connecting line 23, source metal line 24 and drain metal line 25.
Claims (2)
1. metal-insulator gate field-effect tubular construction that is used for high voltage integrated circuit, comprise: P type substrate (1), be provided with p type buried layer (4) on the upper left surface of P type substrate (1), be provided with dark N-type well region (3) on the upper right surface of P type substrate (1), at P type substrate (1), the upper surface of dark N-type well region (3) and p type buried layer (4) is provided with P type epitaxial loayer (5), be provided with P type isolation well region (9) at p type buried layer (4), be provided with the upper area that high-pressure N-shaped well region (6) and high-pressure N-shaped well region (6) extend and enter P type substrate (1) at dark N-type well region (3), in high-pressure N-shaped well region (6), be provided with drain terminal N-type buffering area (8), between P type isolation well region (9) and high-pressure N-shaped well region (6), be provided with N-type isolation well region (7) and P type back gate region (10), and, a border of N-type isolation well region (7) contacts with P type isolation well region (9), a border of P type back gate region (10) contacts with high-pressure N-shaped well region (6), another border of N-type isolation well region (7) contacts with another borderline phase of P type back gate region (10), in P type isolation well region (9), be provided with P type isolation contact zone (17), in P type back gate region (10), be provided with P type back of the body gate contact zone (18) and N-type source region (19), in drain terminal N-type buffering area (8), be provided with N-type drain region (20), public boundary at P type back gate region (10) and high-pressure N-shaped well region (6) is provided with gate oxide (15), in P type isolation well region (9), N-type isolation well region (7), the P type isolation contact zone (17) of P type back gate region (10) and high-pressure N-shaped well region (6) top, P type back of the body gate contact zone (18), N-type source region (19), zone beyond gate oxide (15) and N-type drain region (20) top is provided with field oxide (13), be provided with the field oxide top that polysilicon gate (16) and polysilicon gate (16) extend to high-pressure N-shaped well region (6) top at gate oxide (15), be provided with medium isolating oxide layer (21) at field oxide (13) and polysilicon gate (16), on P type isolation contact zone (17) and N-type drain region (20), be connected with respectively P type isolated area metal connecting line (22) and drain metal line (25), it is characterized in that, be provided with n type buried layer (2) in the below of P type back gate region (10), the two ends of described n type buried layer (2) stretch out respectively and respectively with N-type isolation well region (7), high-pressure N-shaped well region (6) connects, between P type back of the body gate contact zone (18) and N-type source region (19), be provided with the first source N-type resilient coating (11), be provided with the first thin field oxide (11') in the first source N-type resilient coating (11) top, between N-type source region (19) and gate oxide (15), be provided with the second source N-type resilient coating (12), be provided with the second thin field oxide (12') in the second source N-type resilient coating (12) top, on P type back of the body gate contact zone (18) and N-type source region (19), be connected with respectively P type back grid metal connecting line (23) and source metal line (24).
2. the metal-insulator gate field-effect tubular construction for high voltage integrated circuit according to claim 1 is characterized in that, n type buried layer (2) right-hand member extends to the lower-left end 0.5-3 μ m that surpasses high-pressure N-shaped well region (6).
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| CN106298768B (en) * | 2015-06-10 | 2019-03-19 | 联华电子股份有限公司 | The operating method of semiconductor element and semiconductor element |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7518209B2 (en) * | 2005-03-16 | 2009-04-14 | Fairchild Korea Semiconductor, Ltd | Isolation of a high-voltage diode between a high-voltage region and a low-voltage region of an integrated circuit |
| US7655979B2 (en) * | 2004-04-27 | 2010-02-02 | Fairchild Korea Semiconductor, Ltd. | High voltage gate driver integrated circuit including high voltage junction capacitor and high voltage LDMOS transistor |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7655979B2 (en) * | 2004-04-27 | 2010-02-02 | Fairchild Korea Semiconductor, Ltd. | High voltage gate driver integrated circuit including high voltage junction capacitor and high voltage LDMOS transistor |
| US7518209B2 (en) * | 2005-03-16 | 2009-04-14 | Fairchild Korea Semiconductor, Ltd | Isolation of a high-voltage diode between a high-voltage region and a low-voltage region of an integrated circuit |
Non-Patent Citations (1)
| Title |
|---|
| 钱钦松 等.Research into charge pumping method technique for hot-carrier.《Journal of Semiconductors》.2009,第30卷(第10期),全文. * |
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