CN1494136A - 一种带有内置散热片的芯片封装结构 - Google Patents
一种带有内置散热片的芯片封装结构 Download PDFInfo
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- CN1494136A CN1494136A CNA021377715A CN02137771A CN1494136A CN 1494136 A CN1494136 A CN 1494136A CN A021377715 A CNA021377715 A CN A021377715A CN 02137771 A CN02137771 A CN 02137771A CN 1494136 A CN1494136 A CN 1494136A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
本发明涉及一种带有内置式散热片的芯片封装结构。传统的外置式和内置式散热结构存在着体积大或散热效果差的缺点。本发明的内置式散热结构包括:基板、设置于所述基板上的芯片、通过凸起和粘结剂设置于所述基板上的散热片以及塑封体,在所述散热片的顶部开设有多条凹槽。由于本发明的内置式散热片的芯片封装结构在传统的基础上增开了凹槽,有效地增大了散热片与空气的接触面积,因而,相应地提高了其散热性能。
Description
技术领域
本发明涉及内置散热片的新设计,尤其涉及对芯片封装结构中的内置散热片的改进。
背景技术
由于一些集成电路的工作功率较大,因此,在这类集成电路上一般都需要设置散热结构。现有芯片上的散热结构分为外置式和内置式两种。
外置式的结构如图1所示,即在经封装的芯片(集成电路)101上表面,设置金属页片102,该金属页片102即为散热片,起到散热的作用。这种外置式结构虽然散热效果较佳,但一般体积较大,不适应电子行业对封装尺寸轻薄短小的要求。
内置散热片一般埋入到芯片的塑封胶内部,以将芯片产生的热量传导到基板或散发到空气中。内置式的结构如图2和图3所示,其中图2为传统的内置式结构的剖面图,图3是图2的俯视图。如图2所示,在传统球栅阵封装BGA形式基础上,在塑封体21内埋入散热片22,散热片2的底部有若干凸起24,这些凸起24通过粘结剂26粘接到在基板25上。这些凸起24的作用是保证散热片22的下沿27与基板25之间留有一定的间隙28,以便塑封胶在注塑过程中能够顺利地流入并充满散热片22内部的空腔29。塑封后,散热片22的顶部30将暴露于空气中,与塑封体顶端的高度相同。由于散热片22一般由导热性能较好的材料,例如铜、铝等制成,采用了这样的结构,芯片31上产生的热量就可以通过散热片散发到空气中。但是,从图3中可以更清楚地看出,这种内置式结构的缺点在于,其散热片22的散热面为一个平面,与空气的接触面积有限,散热效果不如具有叶片结构的外置式散热结构。
发明内容
本发明的目的在于,结合传统内置式和外置式结构的特点,提供一种散热效果接近外置式的带有内置式散热片的芯片封装结构。
根据本发明的上述目的,本发明的带有内置式散热片的芯片封装结构包括:基板、设置于所述基板上的芯片、通过凸起和粘结剂设置于所述基板上的散热片以及塑封体,其特征在于,在所述散热片的顶部开设有多条凹槽。
如上所述的带内置式散热片的芯片封装结构,所述凹槽可以为直线型、圆环形、中心向外发散形或蛇形。
如上所述的带内置式散热片的芯片封装结构,所述散热片的顶部为圆形或方形。
如上所述,本发明对传统的内置式结构改进之处在于,在散热片的顶部开设了凹槽,其作用是增大散热片与空气的接触面积,从而有效地提高散热效果。
附图说明
下面将结合附图详细描述本发明的具体实施例。附图中:
图1是传统的外置式散热片结构的示意图;
图2和图3是传统的内置式散热片结构的示意图。
图4-8本发明的带有内置散热片的芯片封装结构的多个实施例的结构示意图。
具体实施方式
请参见图4A和图4B。图4A为本发明的带有内置散热片的芯片封装结构的一个实施例的剖视图,图4B为其俯视图。从整体上来说,该结构与传统的内置式结构基本相似。在传统球栅阵封装BGA形式基础上,在塑封体1内埋入散热片2,散热片2的底部有若干凸起4,这些凸起4通过粘结剂6粘接到在基板5上。这些凸起4的作用是保证散热片2的下沿7与基板5之间留有一定的间隙8,以便塑封胶在注塑过程中能够顺利地流入并充满散热片2内部的空腔9。塑封后,散热片2的顶部10将暴露于空气中,与塑封体顶端的高度相同。散热片2一般由导热性能较好的材料,例如铜、铝等制成。本发明对传统的内置式结构的改进之处在于,在散热片2的顶部开设有多条凹槽3,这些凹槽3使得散热片2与空气的接触面积增大,从而有效地提高散热效果。这些凹槽3的形状可以变化,例如在图4的实施例中,凹槽为直线型;在图5的实施例中,凹槽3A呈圆环形;在图6和图7的实施例中,凹槽4A和5A呈中心向外发散形;在图8的实施例中,凹槽6A呈蛇形。对于直流形的凹槽结构,可以在芯片的应用环境中,使空气流动方向顺着该凹槽的走向,这样更能显示其优越的散热性能。
再者,散热片2顶部的形状也是可以变化的,例如,图4、图5和图7的实施例中,散热片2的顶部为圆形,而在图6和图8的实施例中,散热片2的顶部为方形。应当理解,这里所描述的凹槽形状和散热片顶部形状只是作为例子,任何合适的其它形状对于本发明来说,都是可以采用的。
Claims (7)
1、一种带有内置式散热片的芯片封装结构包括:基板、设置于所述基板上的芯片、通过凸起和粘结剂设置于所述基板上的散热片以及塑封体,其特征在于,在所述散热片的顶部开设有多条凹槽。
2.如权利要求1所述的带内置式散热片的芯片封装结构,其特征在于,所述凹槽为直线型。
3.如权利要求1所述的带内置式散热片的芯片封装结构,其特征在于,所述凹槽为圆环形。
4.如权利要求1所述的带内置式散热片的芯片封装结构,其特征在于,所述凹槽为中心向外发散形。
5.如权利要求1所述的带内置式散热片的芯片封装结构,其特征在于,所述凹槽为蛇形。
6.如权利要求1至5之一所述的带内置式散热片的芯片封装结构,其特征在于,所述散热片的顶部为圆形。
7.如权利要求1至5之一所述的带内置式散热片的芯片封装结构,其特征在于,所述散热片的顶部为方形。
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010143080A1 (en) * | 2009-06-10 | 2010-12-16 | Green Arrow Asia Limited | Integrated circuit package having a castellated heatspreader |
CN102842542A (zh) * | 2011-06-21 | 2012-12-26 | 中兴通讯股份有限公司 | 塑封芯片及其制造方法 |
CN106057747A (zh) * | 2015-04-09 | 2016-10-26 | 三星电子株式会社 | 包括散热器的半导体封装件及其制造方法 |
CN109863596A (zh) * | 2019-01-22 | 2019-06-07 | 长江存储科技有限责任公司 | 集成电路封装结构及其制造方法 |
US11862529B2 (en) | 2020-09-30 | 2024-01-02 | Huawei Technologies Co., Ltd. | Chip and manufacturing method thereof, and electronic device |
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2002
- 2002-11-01 CN CNA021377715A patent/CN1494136A/zh active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010143080A1 (en) * | 2009-06-10 | 2010-12-16 | Green Arrow Asia Limited | Integrated circuit package having a castellated heatspreader |
CN102842542A (zh) * | 2011-06-21 | 2012-12-26 | 中兴通讯股份有限公司 | 塑封芯片及其制造方法 |
WO2012174833A1 (zh) * | 2011-06-21 | 2012-12-27 | 中兴通讯股份有限公司 | 塑封芯片及其制造方法 |
CN106057747A (zh) * | 2015-04-09 | 2016-10-26 | 三星电子株式会社 | 包括散热器的半导体封装件及其制造方法 |
CN109863596A (zh) * | 2019-01-22 | 2019-06-07 | 长江存储科技有限责任公司 | 集成电路封装结构及其制造方法 |
CN109863596B (zh) * | 2019-01-22 | 2020-05-26 | 长江存储科技有限责任公司 | 集成电路封装结构及其制造方法 |
US11476173B2 (en) | 2019-01-22 | 2022-10-18 | Yangtze Memory Technologies Co., Ltd. | Manufacturing method of integrated circuit packaging structure |
US11862529B2 (en) | 2020-09-30 | 2024-01-02 | Huawei Technologies Co., Ltd. | Chip and manufacturing method thereof, and electronic device |
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