WO2012174833A1 - 塑封芯片及其制造方法 - Google Patents

塑封芯片及其制造方法 Download PDF

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Publication number
WO2012174833A1
WO2012174833A1 PCT/CN2011/083848 CN2011083848W WO2012174833A1 WO 2012174833 A1 WO2012174833 A1 WO 2012174833A1 CN 2011083848 W CN2011083848 W CN 2011083848W WO 2012174833 A1 WO2012174833 A1 WO 2012174833A1
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WO
WIPO (PCT)
Prior art keywords
chip
heat sink
plastic
molding material
receiving groove
Prior art date
Application number
PCT/CN2011/083848
Other languages
English (en)
French (fr)
Inventor
何钢
王刚
宋滨
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2012174833A1 publication Critical patent/WO2012174833A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Definitions

  • the present invention relates to the field of communications, and in particular to a plastic package chip and a method of fabricating the same.
  • BACKGROUND OF THE INVENTION Currently, integrated circuits are widely used in base stations and computers. However, a large number of plastic encapsulated chips in these integrated circuits generate a large amount of heat, so that how to perform effective heat dissipation becomes a very difficult problem. In the related art, the heat dissipation mode of the plastic package chip is mainly divided into air cooling and water cooling.
  • Air cooling is to attach a heat-conducting heat sink to the plastic chip with a large heat output, and fix a small fan above the heat sink, and water cooling is to distribute the draft tube around the heat sink.
  • the cooling liquid that drives the high specific heat capacity circulates in the draft tube. It can be seen that whether it is air-cooled or water-cooled, it is necessary to assemble a heat sink around the plastic chip.
  • 1 is a schematic cross-sectional view of a plastic package chip according to the related art. As shown in FIG. 1, a molding material 11, a circuit substrate 13, a chip lead 14, a die 15, a die mounting stage 16, and a wire bonding 17 are included. At the same time, fins 12 are integrally wrapped on the top and surrounding outer walls of the molding material 11.
  • the plastic chip is mainly cooled by the chip pin 14 and the heat sink 12 in two ways. However, it has a supporting structure for fixing the heat sink. This technology is complicated to implement, and the chip space in the base station or the computer is extremely limited, and the heat sink 12 wrapped on the top and outer walls of the molding material 11 will undoubtedly Further occupying the already limited chip space, thereby affecting the heat dissipation effect of the plastic package chip.
  • the present invention provides a plastic package chip and a method of fabricating the same to at least solve the problem that the heat sink in the related art occupies a large chip space and thus affects the heat dissipation effect of the plastic package chip.
  • a plastic package chip comprising a molding material and a heat sink, wherein an edge of the molding material is provided with a receiving groove, and the receiving groove is provided to receive the heat sink.
  • the receiving groove is provided at an upper edge of the molding material.
  • the heat sink is located in the receiving groove, and the upper edge of the heat sink is flush with the upper edge of the molding material.
  • the die and wire bonds are also included, and the receiving groove is disposed directly above the die and wire bonds.
  • a method of manufacturing a plastic-sealed chip comprising: providing a receiving groove at an edge of a molding material in a plastic-sealed chip; and embedding a heat sink in the receiving groove.
  • the accommodating groove is provided at the edge of the molding material in the plastic chip, and the accommodating groove is disposed at an upper edge of the molding material in the plastic chip.
  • embedding the heat sink in the receiving groove comprises: adjusting an upper edge of the heat sink to be flat with an upper edge of the molding material.
  • arranging the receiving groove at the edge of the molding material in the plastic chip comprises: arranging the receiving groove directly above the die and the wire bonding in the plastic chip.
  • arranging the receiving groove at the edge of the molding material in the plastic chip comprises: a hot-melt sealing material.
  • the method further comprises: disposing a heat dissipating silica gel around the heat sink in the receiving groove.
  • the invention is provided with a receiving groove for accommodating the heat sink, that is, the heat sink is placed inside the plastic sealing material, the process is simple and reliable, and the chip space can be saved, thereby ensuring the heat dissipation effect of the plastic sealing chip.
  • FIG. 1 is a schematic cross-sectional view of a packaged chip according to the related art
  • FIG. 2 is a schematic cross-sectional view of a chip structure according to an embodiment of the present invention
  • FIG. 3 is a flow chart of a method of manufacturing a plastic packaged chip according to an embodiment of the present invention.
  • FIG. 4 is a flow chart of a method of fabricating a plastic encapsulated chip in accordance with a preferred embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS It should be noted that the embodiments in the present application and the features in the embodiments may be combined with each other without conflict. The invention will be described in detail below with reference to the drawings in conjunction with the embodiments.
  • the invention provides a plastic encapsulated chip.
  • 2 is a schematic cross-sectional view of a chip structure according to an embodiment of the present invention. As shown in FIG. 2, the sealing material 11 and the heat sink 12 are included, wherein the edge of the molding material 11 is provided with a receiving groove 111, and the receiving groove 111 is disposed to receive heat dissipation.
  • the heat sink 12 is wrapped on the top and the outer wall of the molding material 11, which complicates the process and occupies a large chip space.
  • the receiving groove 111 for accommodating the heat sink 12, the heat sink 12 is placed inside the molding material 11, the process is simple and reliable, and the chip space can be saved, thereby ensuring the heat dissipation effect of the plastic chip.
  • the receiving groove 111 is provided at the upper edge of the molding material 11.
  • the preferred embodiment places the accommodating groove 111 at the upper edge of the molding material 11 to set the heat sink 12 In the upper part of the plastic chip, it is compatible with the prior art and improves the heat conduction efficiency of the heat sink 12.
  • the heat sink 12 is located in the receiving groove 111, and the upper edge of the heat sink 12 is flush with the upper edge of the molding material 11.
  • the plastic chip can be made into a regular organic whole, thereby facilitating the layout of the device in the base station or the computer using the plastic chip.
  • the plastic package further includes a die 15 and a wire bond 17, and the receiving groove 111 is disposed directly above the die 15 and the wire bond 17.
  • the distance between the heat sink 12 and the die 15 and the wire bond 17 can be shortened, thereby reducing the thermal resistance and speeding up the heat dissipation efficiency.
  • the plastic chip is made faster, more stable, and more suitable for overclocking.
  • the heat sink 12 does not touch the wire bonding 17 .
  • the molding material 11 may be in the form of a solid or a cavity.
  • the shape of the fins 12 may be arbitrary, such as rectangular or circular.
  • the heat sink 12 may be made of a synthetic material or a metal material having a high thermal conductivity and a low thermal resistance.
  • the invention adds a new combination of heat sinks on the plastic chip, and adopts a new combined structure to accelerate the heat dissipation of the plastic chip, thereby prolonging the service life of the chip. Therefore, the method of the invention not only takes into consideration the cost and performance, but also ensures the convenience and flexibility of the use of the plastic package chip.
  • Embodiments of the present invention also provide a method of manufacturing a plastic package chip.
  • 3 is a flow chart of a method of manufacturing a plastic package chip according to an embodiment of the present invention. As shown in FIG. 3, the following steps S302 to S304 are included. Step S302, a receiving groove 111 is provided at an edge of the molding material 11 in the plastic chip. In step S304, the heat sink 12 is embedded in the accommodating groove 111. Preferably, arranging the receiving groove 111 at the edge of the molding material 11 in the plastic package comprises: accommodating the groove 111 at the upper edge of the molding material 11 in the plastic chip.
  • the preferred embodiment places the accommodating groove 111 at the upper edge of the molding material 11 to set the heat sink 12 In the upper part of the plastic chip, it is compatible with the prior art and improves the heat conduction efficiency of the heat sink 12.
  • embedding the heat sink 12 in the receiving groove 111 comprises: adjusting the upper edge of the heat sink 12 to be flat with the upper edge of the molding material 11.
  • the plastic chip can be made into a regular organic whole, thereby facilitating the layout of the device in the base station or the computer using the plastic chip.
  • arranging the receiving groove 111 at the edge of the molding material 11 in the plastic chip includes: arranging the receiving groove 111 directly above the die 15 and the wire bonding 17 in the plastic chip.
  • the distance between the heat sink 12 and the die 15 and the wire bonding 17 can be shortened, thereby reducing the thermal resistance and speeding up the heat dissipation efficiency.
  • the plastic chip is made faster, more stable, and more suitable for overclocking. It should be noted that the heat sink 12 does not touch the wire bonding 17 .
  • arranging the receiving groove 111 at the edge of the molding material 11 in the plastic chip comprises: a hot-melt sealing material 11.
  • the hot-melt sealing material 11 in the preferred embodiment is simple and reliable in implementation.
  • the method further includes: disposing a heat dissipating silica gel around the heat sink 12 in the receiving groove 111. In the preferred embodiment, by disposing the heat dissipating silica gel, the heat conduction efficiency of the heat sink 12 can be improved, thereby ensuring the heat dissipation effect of the plastic package chip.
  • step S402 the circuit board 13 on which the circuit has been designed is fixed, and then the etched die 15 and the wire bond 17 are fixed on the circuit substrate 13, and all the tests are completed.
  • step S404 a groove is formed at the top of the molding material 11.
  • step S406 the heat sink 12 is embedded in the molding material 11.
  • the embedding method includes the following manner
  • Method 1 The hot melt molding material is embedded after 11 .
  • Method 2 The heat sink 12, which is preferably heat-dissipating and non-conductive, is embedded in the molding material 11, and a heat-dissipating silica gel is applied between the heat sink 12 and the molding material 11.
  • a plastic package chip and a method of fabricating the same are provided.
  • the invention is provided with a receiving groove for accommodating the heat sink, that is, the heat sink is placed inside the plastic sealing material, and the process is simple and reliable, and the chip space can be saved, thereby ensuring the heat dissipation effect of the plastic sealing chip.
  • modules or steps of the present invention can be implemented by a general-purpose computing device, which can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. Alternatively, they may be implemented by program code executable by the computing device, such that they may be stored in the storage device by the computing device, or they may be separately fabricated into individual integrated circuit modules, or they may be Multiple modules or steps are made into a single integrated circuit module.
  • the invention is not limited to any specific combination of hardware and software.
  • the above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes can be made to the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and scope of the present invention are intended to be included within the scope of the present invention.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

提供一种塑封芯片及其制造方法，该塑封芯片包括：塑封材料（11）和散热片（12），其中，塑封材料（11）的边缘设置有容纳槽（111），容纳槽（111）用于容纳散热片（12）。该芯片可以解决散热片占用较大芯片空间从而影响塑封芯片的散热效果的问题，并在保证芯片散热的良好效果下，结构简单可靠、易实现，且可以节约芯片空间。

Description

塑封芯片及其制造方法 技术领域 本发明涉及通信领域， 具体而言， 涉及一种塑封芯片及其制造方法。 背景技术 目前， 集成电路在基站、 电脑中获得了广泛应用， 但是， 这些集成电路中的大量 塑封芯片会产生很大热量， 从而使得如何进行有效散热变成了一个非常棘手的问题。 相关技术中， 塑封芯片的散热方式主要分为风冷和水冷。 风冷就是将一块导热性 较好的散热片紧紧贴住发热量较大的塑封芯片， 并在散热片的上方再固定一个小型的 风扇， 而水冷是在该散热片周围分布导流管， 并驱动高比热容的冷却液体在该导流管 中循环。 由此可见， 无论风冷还是水冷的散热方式， 都需要在塑封芯片周围装配散热 片。 图 1是根据相关技术的塑封芯片的剖面示意图， 如图 1所示， 包括塑封材料 11、 电路基板 13、 芯片引脚 14、 管芯 15、 管芯安装台 16和引线键合 17。 同时， 在塑封材 料 11的顶部与四周外壁上整体包裹有散热片 12。 本塑封芯片主要通过芯片引脚 14和 散热片 12两种方式进行散热。 但是， 其有支撑结构来固定该散热片， 此技术实现复杂， 无论是基站还是电脑中 的芯片空间都是极为有限的， 而包裹在塑封材料 11 的顶部与四周外壁上的散热片 12 无疑会进一步占用本已极为有限的芯片空间， 从而影响塑封芯片的散热效果。 发明内容 本发明提供了一种塑封芯片及其制造方法， 以至少解决相关技术中的散热片占用 较大芯片空间从而影响塑封芯片的散热效果的问题。 根据本发明的一个方面， 提供了一种塑封芯片， 包括塑封材料和散热片， 其中， 塑封材料的边缘设置有容纳槽， 容纳槽设置为容纳散热片。 优选地， 容纳槽设置在塑封材料的上边缘。 优选地， 散热片位于容纳槽内， 并且散热片的上边缘与塑封材料的上边缘持平。 优选地， 还包括管芯和引线键合， 并且容纳槽设置在管芯和引线键合的正上方。 根据本发明的另一个方面， 提供了一种塑封芯片的制造方法， 包括： 在塑封芯片 中的塑封材料的边缘设置容纳槽； 在容纳槽中嵌入散热片。 优选地， 在塑封芯片中的塑封材料的边缘设置容纳槽包括： 在塑封芯片中的塑封 材料的上边缘设置容纳槽。 优选地， 在容纳槽中嵌入散热片包括： 调整散热片的上边缘与塑封材料的上边缘 持平。 优选地， 在塑封芯片中的塑封材料的边缘设置容纳槽包括： 设置容纳槽位于塑封 芯片中的管芯和引线键合的正上方。 优选地， 在塑封芯片中的塑封材料的边缘设置容纳槽包括： 热熔塑封材料。 优选地， 在容纳槽中嵌入散热片之后， 上述方法还包括： 在容纳槽中的散热片周 围设置散热硅胶。 本发明通过设置用于容纳散热片的容纳槽， 即将散热片置于塑封材料的内部， 实 现工艺简单、 可靠， 可以节约芯片空间， 从而保证塑封芯片的散热效果。 附图说明 此处所说明的附图用来提供对本发明的进一步理解， 构成本申请的一部分， 本发 明的示意性实施例及其说明用于解释本发明， 并不构成对本发明的不当限定。 在附图 中： 图 1是根据相关技术的塑封芯片的剖面示意图； 图 2是根据本发明实施例的芯片结构的剖面示意图； 图 3是根据本发明实施例的塑封芯片的制造方法的流程图； 图 4是根据本发明优选实施例的塑封芯片的制造方法的流程图。 具体实施方式 需要说明的是， 在不冲突的情况下， 本申请中的实施例及实施例中的特征可以相 互组合。 下面将参考附图并结合实施例来详细说明本发明。 本发明提供了一种塑封芯片。图 2是根据本发明实施例的芯片结构的剖面示意图， 如图 2所示， 包括塑封材料 11和散热片 12， 其中， 塑封材料 11的边缘设置有容纳槽 111， 容纳槽 111设置为容纳散热片 12。 相关技术中， 散热片 12包裹在塑封材料 11的顶部与四周外壁上， 实现工艺复杂， 且将占用较大芯片空间。本发明实施例中，通过设置用于容纳散热片 12的容纳槽 111， 即将散热片 12置于塑封材料 11的内部， 实现工艺简单、 可靠， 可以节约芯片空间， 从而保证塑封芯片的散热效果。 优选地， 容纳槽 111设置在塑封材料 11的上边缘。考虑到相关技术中塑封芯片的 风冷或水冷， 通常是在其上方配置风扇或者导流管， 因此， 本优选实施例将容纳槽 111 设置在塑封材料 11的上边缘， 以便将散热片 12设置在塑封芯片的上部， 从而可以兼 容现有技术， 并提升散热片 12的导热效率。 优选地， 散热片 12位于容纳槽 111内， 并且散热片 12的上边缘与塑封材料 11的 上边缘持平。 本优选实施例中， 通过调整散热片 12的上边缘与塑封材料 11的上边缘 持平， 可以使得塑封芯片成为一个形状规则的有机整体， 从而有利于使用该塑封芯片 的基站或者电脑中的器件布局。 优选地， 塑封芯片还包括管芯 15和引线键合 17， 并且容纳槽 111设置在管芯 15 和引线键合 17的正上方。 本优选实施例中， 通过设置容纳槽 111在管芯 15和引线键 合 17的正上方，可以缩短散热片 12到管芯 15和引线键合 17的距离， 从而降低热阻， 加快散热效率， 使该塑封芯片速度更快、 更稳定、 更适合超频。 需要说明的是， 散热 片 12不要碰到引线键合 17。 优选地， 塑封材料 11的形式可以是实心的， 也可以是空腔的。 优选地， 散热片 12的形状可以是任意的， 例如矩形、 圆形。 优选地， 散热片 12可以采用导热率高、 低热阻的合成材料或金属材料。 综上， 本发明在塑封芯片上加散热片进行全新组合， 并采用新的组合架构来加快 塑封芯片的散热， 从而延长了芯片的使用寿命。 因此， 本发明方法既兼顾了成本、 性 能， 又保证了塑封芯片使用的便利性、 灵活性。 本发明实施例还提供了一种塑封芯片的制造方法。 图 3是根据本发明实施例的塑 封芯片的制造方法的流程图， 如图 3所示， 包括如下的步骤 S302至步骤 S304。 步骤 S302， 在塑封芯片中的塑封材料 11的边缘设置容纳槽 111。 步骤 S304, 在容纳槽 111中嵌入散热片 12。 优选地， 在塑封芯片中的塑封材料 11的边缘设置容纳槽 111包括： 在塑封芯片中 的塑封材料 11的上边缘设置容纳槽 111。 考虑到相关技术中塑封芯片的风冷或水冷， 通常是在其上方配置风扇或者导流管， 因此， 本优选实施例将容纳槽 111设置在塑封 材料 11的上边缘， 以便将散热片 12设置在塑封芯片的上部， 从而可以兼容现有技术， 并提升散热片 12的导热效率。 优选地， 在容纳槽 111中嵌入散热片 12包括： 调整散热片 12的上边缘与塑封材 料 11的上边缘持平。本优选实施例中， 通过调整散热片 12的上边缘与塑封材料 11的 上边缘持平， 可以使得塑封芯片成为一个形状规则的有机整体， 从而有利于使用该塑 封芯片的基站或者电脑中的器件布局。 优选地，在塑封芯片中的塑封材料 11的边缘设置容纳槽 111包括：设置容纳槽 111 位于塑封芯片中的管芯 15和引线键合 17的正上方。 本优选实施例中， 通过设置容纳 槽 111在管芯 15和引线键合 17的正上方， 可以缩短散热片 12到管芯 15和引线键合 17的距离， 从而降低热阻， 加快散热效率， 使该塑封芯片速度更快、 更稳定、 更适合 超频。 需要说明的是， 散热片 12不要碰到引线键合 17。 优选地， 在塑封芯片中的塑封材料 11的边缘设置容纳槽 111包括： 热熔塑封材料 11。 本优选实施例中的热熔塑封材料 11， 实现方式简单、 可靠。 优选地， 在容纳槽 111中嵌入散热片 12之后， 上述方法还包括： 在容纳槽 111中 的散热片 12周围设置散热硅胶。本优选实施例中， 通过设置散热硅胶， 可以提升散热 片 12的导热效率， 从而保证塑封芯片的散热效果。 下面将结合实例对本发明实施例的实现过程进行详细描述。 图 4是根据本发明优选实施例的塑封芯片的制造方法的流程图， 如图 4所示， 包 括如下的步骤 S402至步骤 S406。 步骤 S402， 将线路已经设计好的电路基板 13固定， 然后将已经蚀刻过的管芯 15 和引线键合 17固定在电路基板 13上， 完成所有的测试。 步骤 S404, 在塑封材料 11的顶部开槽。 步骤 S406， 将散热片 12嵌入塑封材料 11中。 具体地， 嵌入方式包括如下的方式
①和方式②。 方式①： 热熔塑封材料 11后嵌入。 方式②： 将较佳散热性并且不导电的散热片 12嵌入塑封材料 11中， 并在散热片 12与塑封材料 11之间加散热硅胶。 综上所述， 根据本发明的上述实施例， 提供了一种塑封芯片及其制造方法。 本发 明通过设置用于容纳散热片的容纳槽， 即将散热片置于塑封材料的内部， 实现工艺简 单、 可靠， 可以节约芯片空间， 从而保证塑封芯片的散热效果。 显然， 本领域的技术人员应该明白， 上述的本发明的各模块或各步骤可以用通用 的计算装置来实现， 它们可以集中在单个的计算装置上， 或者分布在多个计算装置所 组成的网络上， 可选地， 它们可以用计算装置可执行的程序代码来实现， 从而， 可以 将它们存储在存储装置中由计算装置来执行， 或者将它们分别制作成各个集成电路模 块， 或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。 这样， 本发明 不限制于任何特定的硬件和软件结合。 以上所述仅为本发明的优选实施例而已， 并不用于限制本发明， 对于本领域的技 术人员来说， 本发明可以有各种更改和变化。 凡在本发明的精神和原则之内， 所作的 任何修改、 等同替换、 改进等， 均应包含在本发明的保护范围之内。

Claims

一种塑封芯片， 包括塑封材料（11)和散热片（12)， 其中， 所述塑封材料（11) 的边缘设置有容纳槽（111)， 所述容纳槽（111)设置为容纳所述散热片 （12)。 根据权利要求 1所述的塑封芯片， 其中， 所述容纳槽（111)设置在所述塑封材 料 （11) 的上边缘。 根据权利要求 2所述的塑封芯片，其中，所述散热片（12)位于所述容纳槽（111) 内， 并且所述散热片 （12) 的上边缘与所述塑封材料 （11) 的上边缘持平。 根据权利要求 1所述的塑封芯片， 其中， 还包括管芯 （15) 和引线键合 （17)， 并且所述容纳槽（111)设置在所述管芯（15)和所述引线键合（17)的正上方。 一种塑封芯片的制造方法， 包括：
在塑封芯片中的塑封材料 （11) 的边缘设置容纳槽 （111);
在所述容纳槽 （111) 中嵌入散热片 （12)。 根据权利要求 5所述的方法， 其中， 在塑封芯片中的塑封材料 （11) 的边缘设 置容纳槽（111)包括： 在所述塑封芯片中的塑封材料（11) 的上边缘设置容纳 槽 （111)。 根据权利要求 6所述的方法， 其中， 在所述容纳槽 （111) 中嵌入散热片 （12) 包括： 调整所述散热片 （12) 的上边缘与所述塑封材料 （11) 的上边缘持平。 根据权利要求 5所述的方法， 其中， 在塑封芯片中的塑封材料 （11) 的边缘设 置容纳槽（111)包括： 设置所述容纳槽（111)位于所述塑封芯片中的管芯（15) 和引线键合 （17) 的正上方。 根据权利要求 5至 8中任一项所述的方法，其中，在塑封芯片中的塑封材料（ 11 ) 的边缘设置容纳槽 （111) 包括： 热熔所述塑封材料 （11)。 根据权利要求 5至 8中任一项所述的方法， 其中， 在所述容纳槽（111) 中嵌入 散热片（12)之后，所述方法还包括：在所述容纳槽（111)中的所述散热片（12) 周围设置散热硅胶。
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