CN1479407A - 结合有天线的半导体组件结构 - Google Patents

结合有天线的半导体组件结构 Download PDF

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CN1479407A
CN1479407A CNA03141317XA CN03141317A CN1479407A CN 1479407 A CN1479407 A CN 1479407A CN A03141317X A CNA03141317X A CN A03141317XA CN 03141317 A CN03141317 A CN 03141317A CN 1479407 A CN1479407 A CN 1479407A
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antenna
silicon plate
assembly structure
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真S直宽
真篠直宽
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Shinko Electric Industries Co Ltd
Shinko Electric Co Ltd
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
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    • H01Q23/00—Antennas with active circuits or circuit elements integrated within them or attached to them
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    • H01Q1/00—Details of, or arrangements associated with, antennas
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    • H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
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    • H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04—Resonant antennas
    • H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
    • H01Q9/0421—Substantially flat resonant element parallel to ground plane, e.g. patch antenna with a shorting wall or a shorting pin at one end of the element
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    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor

Abstract

本发明提供一种结合有天线的半导体组件结构，通过改进组成天线3的组件结构的材料减小天线的长度。铁电层(2)形成在硅板(1)上，由导体膜组成的天线(3)形成在铁电层(2)上。通孔(9)形成在硅板(1)上。如电容器、SAW滤波器和电感的电子元件结合到硅板(1)上以组成组件结构。

Description

结合有天线的半导体组件结构
技术领域
本发明涉及结合有天线并且能够起到插入物(interposer)作用的半导体组件的结构。本发明还涉及该结构的制造方法。更具体地，本发明可用于制造其中使用插入物的多芯片组件。
背景技术
通常，用于无线通信的天线由导电材料或陶瓷和导电材料的组合物制成。然而，根据无线通信使用的频率，可以限定天线结构。例如，当使用形成在通常的玻璃环氧树脂制成的印制板(介电常数约4.5)上的天线在2.5GHz的频带中进行无线通信时，需要提供长度为18mm的天线。另一方面，当天线形成在陶瓷制成的板(介电常数为10)上时，需要提供长度约13mm的天线。
对于由陶瓷或印制板制成的平面天线来说，即使需要使用高介电常数的材料，通常，用于平面天线或印制板的材料的介电常数很少超过100。
公开在日本待审专利公开No.8-56113中的现有技术，介绍了检测毫米波使用的检测器。根据该现有技术，地导电膜和介质膜叠置在硅或砷化镓制成的半导体板上，平面天线和用于向该平面天线提供电能的微条路径形成在该介质膜上，借助倒装芯片接合，在其上提供有信号检测电路或信号产生电路的由砷化镓制成的第二半导体板安装在微条路径上。
在该现有技术中，公开了一种结构，代替使用提供在半导体板上介质膜上的平面天线，使用介质板，借助通孔，通过设置在背面上的端子向形成在板上的平面天线提供电能。
如上所述，用于进行无线通信的天线通常形成在印制板上，需要提供长度为预定值的天线。因此，例如，不可能将天线结合到硅芯片内，这是由于在硅芯片内不能确保足够大的天线形成区。
发明概述
因此，本发明的一个目的是提供一种半导体组件结构，通过改进其上形成有天线的组件结构的材料，来减小天线的长度，天线可以形成在硅芯片内。
为了实现以上目的，根据本发明，提供一种半导体组件结构，包括：具有第一和第二表面的硅板，形成在硅板的第一表面或第二表面的至少一部分上的铁电层；形成在铁电层上由导电膜组成的天线。当天线形成在以上介绍的硅板上的铁电层上时，可以将天线的长度减少到不大于1.2mm。
此时，例如，优选地将锆钛酸盐(PZT)用作铁电材料。PZT为含锆钛酸铅Pb(ZrxTi1-x)O3的混合陶瓷制成的材料。PZT的介电常数约1200。因此，即使当硅板自身的介电常数约10时，当铁电层形成在硅板上时，天线的长度可以显著减少到不超过1.2mm的值。
如电容器、SAW滤波器和电感的电子元件形成在硅板上，在硅板上形成有天线，并结合到组件结构内。由于以上结构，不仅天线而且具有其它功能的电子部件可以安装到一个组件结构上。例如，这种电子元件具有形成为硅板上图形的线圈形结构。
通孔形成在硅板上，在其上形成有天线，导体层借助绝缘层形成在通孔的内壁表面上，导体层与提供在硅板的第一和第二表面上的导体图形连接。当如上所述穿过硅板两面的通孔形成在硅板上时，提供在板两面上的图形可以相互电连接。
此时，接地层借助第一绝缘层形成在通孔内壁表面的下层上，信号层借助第二绝缘层形成在接地层的上表面上，接地层和信号层分别与提供在硅板的第一和第二表面上的接地层和信号图形连接。
附图简介
图1示出了能够用做插入物的本发明的第一实施例的半导体组件的透视图；
图2示出了图1所示半导体组件的通孔部分的剖面图；
图3示出了电感的平面图，作为能够形成在本发明的半导体组件上的电子部件的一个例子；
图4示出了本发明的第二实施例的半导体组件的剖面图；以及
图5示出了本发明的第三实施例的半导体组件的剖面图。
优选实施例的详细说明
下面参考附图介绍本发明的一些实施例。
图1示出了能够用做插入物的本发明的第一实施例的半导体组件的透视图。半导体板1必须平坦和为矩形。此外，半导体板1的热阻必须高。而且，将如IC芯片的电子部件安装在半导体板1上的这种特性必须高。由于以上原因，本发明使用硅板。硅板1自身的介电常数近似10。
在硅板1表面上的部分区域中，也就是，在沿矩形板1的右短边纵向设置的矩形区域中，提供铁电层2。在该铁电层2上，形成由导体膜组成的天线3。
铁电层2例如由PZT制成。PZT为含锆钛酸铅Pb(ZrxTi1-x)O3的混合陶瓷制成的材料。PZT的介电常数近似1200。
天线3的平面轮廓形成F形图形。天线的尺寸小，即，F形天线的长度L不超过1.2mm，F形天线的宽度W不超过1mm。借助形成在板1上的电能提供图形4和铁电层2，电能提供到该天线3。
在除了其中形成有铁电层2的区域之外的板1上的区域中，提供有电路单元或部件，例如多个半导体芯片5、电感6、电容器7以及SAW滤波器。这些电子部件与硅板1形成一个整体，由此组成一个多芯片组件(MCM)。例如，作为电路部件之一的电感6通常安装在板上作为其中一个部件。然而，在本实施例中，电感6整体地结合到硅板1的表面上。
穿过硅板1两个表面的大量通孔9形成在硅板上。虽然在图中没有示出，在大量芯片5的下表面区域中硅板1提供有许多通孔9。通孔9与电路图形10连接。该电路图形10与形成在硅板1上的天线3连接，也与电路图形部分连接，如半导体硅芯片5、电感6、电容器7以及SAW滤波器8。通过通孔9可以有利地实现提供在板表面上的电路图形和提供在板背面上的电路图形之间的电连续性，这是由于用于电源、接地和发送信号的布线可以设置在通孔9的内壁上或通孔之中。
图2示出了图1所示半导体组件的通孔部分的放大剖面图。在硅板1上，借助激光束加工或钻孔预先形成大量的通孔9，使得通孔9穿透板1。在硅板1的两面上和通孔9的壁表面上，形成由例如通过热氧化硅板形成氧化硅(SiO2)制成的绝缘膜11。在该绝缘膜11上，形成需要的导体焊盘12和导体图形10。通过将铜电解镀在已借助化学汽相淀积(CVD)或无电镀形成的镀镍层上，导体层和导体图形可以形成在硅板1的两面上和通孔9的内壁上。
当为图2所示的通孔9时，在绝缘层11上，形成为下层布线的接地层12。此外，在接地层12上，形成由氧化硅(SiO2)制成的绝缘膜13。而且，为表面层的信号层14形成在绝缘膜13上。形成在通孔9中的接地层12和信号层4分别连接形成在硅板1两面上的接地层(下层布线)15和信号图形16。
对于连接到外部的端子，例如在导体焊盘17上提供焊料突点18。如图2所示，导体焊盘17与提供在硅板1两面上的信号图形16连接。此外，导体焊盘17借助通孔的信号层14连接提供在板1相对面上的信号图形。在该实施例中，没有使用用于引线键合的屏蔽线，但导体通过以上介绍的通孔相互连接。因此，天线不可能受噪声影响。
图3示出了电感的平面图，作为能够形成在图1所示的半导体组件的硅板1上的电子部件的一个例子。例如通过化学腐蚀形成在硅板1上的导电铜膜形成该线圈形电感6。
图4示出了本发明的第二实施例的半导体组件的剖面图。当图1中介绍的板用做插入物时，该半导体组件很适合。图4示出了安装芯片电容器(去耦电容器)作为电子部件的情况。借助倒装芯片接合，芯片电容器30安装在另一芯片电容器或插入物31上。该芯片电容器或插入物31具有以上提到的通孔35。此外，借助以上介绍的倒装芯片接合，该硅芯片或插入物31安装在又一芯片电容器或插入物32上。该芯片电容器或插入物32也具有以上介绍的通孔35。按以上介绍的相同方式，借助倒装芯片接合，芯片电容器或插入物32安装在印制板或封装33上。在图4中，参考数字36为用于倒装芯片接合的焊盘，参考数字37为重新布线或二次布线。
图5示出了本发明的第三实施例的半导体组件的剖面图。以图4所示的第二实施例的相同方式，在本实施例中板用做插入物。图5实施例与图4实施例不同之处在下面介绍。省略了设置在中间部分中的硅芯片或插入物31，借助倒装芯片接合，为电子部分的芯片电容器(去耦电容器)30安装在另一硅芯片32上。该硅芯片32也具有与以上介绍相同的通孔。按以前介绍的相同方式借助倒装芯片接合，硅芯片32安装在印制板或封装33上。
如上所述，根据本发明，天线可以制得紧凑并且结合到硅芯片(硅插入物)内。因此，通信设备可以制得很小。此外，如电容器、SAW滤波器和电感的电子部件形成在插入物上，同时形成天线。因此，可以以降低的成本制造出多芯片组件(MCM)。

Claims (6)

1.一种半导体组件结构，包括：
具有第一和第二表面的硅板，形成在硅板的第一表面或第二表面的至少一部分上的铁电层；以及
形成在铁电层上由导电膜组成的天线。
2.根据权利要求1的半导体组件结构，其中铁电层由锆钛酸铅(PZT)制成。
3.根据权利要求1的半导体组件结构，其中如电容器、SAW滤波器和电感的电子元件形成在硅板上并且结合到组件结构内。
4.根据权利要求3的半导体组件结构，其中电子元件具有形成为硅板上图形的线圈形结构。
5.根据权利要求1的半导体组件结构，其中通孔形成在硅板中，借助绝缘层导体层形成在通孔的内壁表面上，导体层与提供在硅板的第一和第二表面上的导体图形连接。
6.根据权利要求5的半导体组件结构，其中接地层借助第一绝缘层形成在通孔的内壁表面的下层上，信号层借助第二绝缘层形成在接地层的上表面上，接地层和信号层分别与提供在硅板的第一和第二表面上的接地层和信号图形连接。
CNA03141317XA 2002-06-13 2003-06-10 结合有天线的半导体组件结构 Pending CN1479407A (zh)

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