CN1466201A - Semiconductor package whose chip carrier has receessed portion - Google Patents
Semiconductor package whose chip carrier has receessed portion Download PDFInfo
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- CN1466201A CN1466201A CNA021231990A CN02123199A CN1466201A CN 1466201 A CN1466201 A CN 1466201A CN A021231990 A CNA021231990 A CN A021231990A CN 02123199 A CN02123199 A CN 02123199A CN 1466201 A CN1466201 A CN 1466201A
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- Prior art keywords
- chip carrier
- chip
- semiconductor package
- package part
- recess
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
A semiconductor packaging unit with a concave part on a chip seat is adhered a chip on a chip seat with at least one aperture on a lead frame composed of a chip seat and multipin so as to cover the back surface of the chip and expose the aperture and a concave part is formed on the seat along the edge of the aperture form top of the seat downward connecting to the aperture, so that packaging resin forming the packing colloid is fully filled in the concave after the packaging colloid solidizes and void between the chip and chip seat will not occur, die crack or popcorn on packaged products will not appear.
Description
Technical field
The invention relates to a kind of semiconductor package part, is the semiconductor package part that chip bearing member and this chip carrier are formed with perforate about a kind of chip carrier with lead frame particularly.
Background technology
With lead frame (Lead Frame) is that the area of the common problem of semiconductor package part of the chip bearing member chip carrier (Die Pad) that is lead frame is big, and itself and relatively poor in order to the cementability that coats between the sticking packing colloid of being located at the chip on this chip carrier, make to produce layering (Delamination) between this chip carrier and packing colloid under the variations in temperature in reliability testing or real work, cause the reliability of this kind semiconductor package part and quality to be affected.And the chip carrier of this semiconductor package part and the bond area of chip chamber are bigger, make chip in manufacture process, under temperature cycles, can be subjected to the thermal stress effects that bigger chip carrier produces, and cause producing between chip and chip carrier layering or the cracked situation of chip.
For addressing the above problem, United States Patent (USP) the 5th, 233, No. 222 cases propose a kind of semiconductor package part of chip carrier tool recess, shown in accompanying drawing 4A.The chip carrier 30 of this kind semiconductor package part 3 is formed with a perforate 300, after borrowing elargol (Silver Paste) 32 to be bonded on this chip carrier 30 at a chip 31, this chip 31 covers this perforate 300, and the part of the bottom surface 310 of chip 31 exposes outside this perforate 300, the bond area of 30 of this chip 31 and chip carriers is significantly reduced, can effectively reduce the thermal stress effects that 30 pairs of chips of chip carrier 31 produce, and avoid between the two layering generation and the cracked situation of chip, simultaneously, the formation of this perforate 300 further promotes the cementability in order to 30 of the packing colloid 33 that coats this chip 31 and chip carriers.In like manner, United States Patent (USP) the 5th, 327, No. 008 case also proposes the semiconductor package part that a kind of chip carrier roughly is the X type, and it is intended to reduce the bond area between chip and chip carrier, because its effect that can reach is analogous to the former, so refuse icon.
Though above-mentioned two United States Patent (USP)s have some advantages, during in order to the elargol of adhering chip to chip carrier, must strictly control the coating weight of elargol in coating.When elargol is coated with when excessive, shown in accompanying drawing 4B, excessive elargol 32 can take place by perforate 300 edges of chip carrier 30 situation toward underflow stream; In case elargol 32 can pollute equipment and product itself toward underflow stream; But when the coating of elargol is not enough, shown in accompanying drawing 4C, then be easy to edge's leaving gap 301 of chip 31 and 30 nearly perforates 300 of chip carrier, the size in this gap 301 is about 25.4 μ m (1mil) usually, because the resin particle diameter (FillerSize) in order to the potting resin that forms packing colloid 33 then has greater than 25.4 μ m persons, make potting resin that the situation that can't flow into smoothly in this gap 301 be arranged when molding operation, cause air in the gap 301 to discharge and cause gas hole (Voids) to produce; After the gas hole produces, easily in follow-up manufacture process, make chip 31 in rhegma (Crack) taking place corresponding to formation place of gas hole.Thereby, no matter be overflow glue or the formation of gas hole, all can have influence on the reliability and the acceptance rate of manufactured goods; But if strictly control the coating weight of elargol, then can cause the increase of manufacturing cost and the complexity of raising manufacture process, but can not avoid the not enough or excessive problem of elargol coating weight to take place fully toward contact.
In view of this, United States Patent (USP) the 4th, 942, No. 452 cases and the 5th, 150, No. 193 cases successively propose a kind of semiconductor package part that forms groove on chip carrier, effectively to address the above problem.As shown in Figure 5, the chip carrier 40 of this semiconductor package part 4 offers groove 401 in nearly perforate 400 places, the formation of this groove 401 is in order to after avoiding elargol 42 to coat on the chip carrier 40, because of the excessive problem of excessive glue that causes occurs, though it can effectively stop elargol 42 overflows to perforate 400, have only when the coating weight of elargol 42 is not enough, the gas hole still can be formed in the uncoated gap 402 that elargol 42 arranged of 40 of chip 41 and chip carriers, and can't solve the puzzlement of gas hole formation.
Summary of the invention
Purpose of the present invention is promptly providing a kind of semiconductor package part of effectively avoiding the problem of formation of gas hole and elargol generation overflow.
Another object of the present invention then is to provide a kind of method for making of effectively avoiding the semiconductor package part of formation of gas hole and elargol generation overflow problem.
For reaching above-mentioned and other purpose, semiconductor package part of the present invention is to comprise that one has the lead frame of a chip carrier and many pins, this chip carrier also offers at least one perforate, and this chip carrier is in the edge of perforate and recessed and form a recess that is communicated with this perforate from the end face of chip carrier; The one sticking chip of establishing to this chip carrier after this chip and chip carrier are bonding, makes this chip cover an end of this perforate; Many in order to be electrically conducted the bonding wire of this chip and pin; And one in order to coating this chip, chip carrier, bonding wire and pin packing colloid partly, and be to be fills up to fully in this recess in order to the potting resin that forms this packing colloid.
The perforate size and shape of this chip carrier does not have specific limited, as long as can make the bond area minimizing between chip and chip carrier and provide this chip to support fully.
Formation as for the recess of this chip carrier, then as long as control the maximum particle diameter of its degree of depth greater than potting resin, so that potting resin is discharged the air in this recess when molding operation is finished fully and filling in wherein, thereby avoid the formation in gas hole, but concave depth still should be greater than 1mil, and should be greater than 3mil.Simultaneously, the consumption of this adhesive should be controlled in this die bonding to the chip carrier after, the overflow of adhesive trace is to this recess, to guarantee that no air exists between the bonding surface of chip and chip carrier, thereby avoid the formation in gas hole fully, and overflow to the adhesive in the recess should only be present in this recess and unlikely excessive overflow to the surface below of chip carrier, so the anxiety of pollution-free sealed in unit and manufactured goods.
For further guaranteeing the unlikely generation overflow situation of adhesive, the bottom surface of this recess so that this concave depth is to successively decrease from inside to outside, roughly must store in the position darker in recess overflow to the adhesive in this recess from tilting outside to inside.Similarly, also can form a groove on the inside, bottom surface of this recess, more effectively block the adhesive of overflow to this recess with the formation of borrowing this groove.
Modes such as the formation of this recess is then available existingly to etch partially, punching press and bending realize.
Description of drawings
Below be described in further detail characteristics of the present invention and effect with the preferred embodiment conjunction with figs.:
Accompanying drawing 1 is the cutaway view of semiconductor package part of the present invention;
Accompanying drawing 2A is the manufacturing flow chart of semiconductor package part of the present invention to accompanying drawing 2E;
Accompanying drawing 3A to accompanying drawing 3H be other of the used lead frame of semiconductor package part of the present invention
The schematic diagram of embodiment;
Accompanying drawing 4A is the cutaway view of an existing semiconductor package part; And accompanying drawing 4B is in order to adhering chip in the semiconductor package part of expression accompanying drawing 4A and the excessive glue of the elargol of the chip carrier schematic diagram to the perforate of chip carrier; Accompanying drawing 4C is in order to there to be the schematic diagram in gap between adhering chip and chip carrier in the semiconductor package part of expression accompanying drawing 4A; And
Accompanying drawing 5 is cutaway views of another existing semiconductor package part.
Symbol description
1 semiconductor package part, 10 lead frames
100 chip carrier 100a perforates
100b end face 100c bottom surface
11 chips, 110 bottom surfaces
12 bonding wires, 13 packing colloids
14 adhesives, 3 semiconductor package parts
300 perforates of 30 chip carriers
301 gaps, 31 chips
310 bottom surfaces, 32 elargol
33 packing colloids, 4 semiconductor package parts
400 perforates of 40 chip carriers
401 grooves, 42 elargol
Embodiment
Embodiment 1
As shown in Figure 1, semiconductor package part 1 of the present invention is by a lead frame 10, one is bonded to the chip 11 on this lead frame 10, many connect the bonding wires 12 of this chip 11 and lead frame 10 in order to conduction, and one in order to coat this chip 11, bonding wire 12 and partly the packing colloid 13 of lead frame 10 constitute.
This lead frame 10 is to have a chip carrier 100 and many pin ones 01 of being located at these chip carrier 100 outsides.This chip carrier 100 also is formed with a perforate 100a, makes this perforate 100a run through the end face 100b and the bottom surface 100c of this chip carrier 100 respectively; Simultaneously, these chip carrier 100 formed perforate quantity can be one or more, and shape does not have specific limited, as long as after making this chip 11 borrow on the end face 100b that the adhesive 14 of used as elargol etc. is bonded to this chip carrier 100, this chip 11 cover nose end on the end face 100b that perforate 100a is positioned at chip carrier 100 fully, and the position that makes the bottom surface 110 of chip 11 correspond to this perforate 100a exposes among this perforate 100a and gets final product.
This chip 11 in the edge of perforate 100a and be formed with one from this end face 100b recess 100d recessed and that lead to this perforate 100a.The degree of depth of this recess 100d must be greater than the maximum particle diameter in order to the filler particles in the potting resin that forms this packing colloid 13, after being bonded on the chip carrier 100 at this chip 11, in the mold pressing manufacture process, this potting resin can unhinderedly flow into this recess 100d, and complete this recess of filling 100d, so that the air in the recess 100d is discharged, after packing colloid 13 moulding, do not have the gas hole and be formed among this recess 100d, do not take place so do not have the problem of gas explosion.The degree of depth of this recess 100d should be greater than about 1mil, and is then better greater than 3mil.
The coating of this adhesive 14 must be controlled at this chip 11 when being bonded on the chip carrier 100, this adhesive 14 gets micro-overflow to this recess 100d, to guarantee that no air exists between the bonding surface of chip 11 and chip carrier 100, thereby avoid the formation in gas hole fully, and overflow to 14 of the adhesives of recess 100d retain in this recess and unlikely excessive overflow to the surface below of chip carrier 100, therefore can effectively avoid adhesive 14 in chip join (Die Bonding) process, to pollute equipment and semi-finished product.
The manufacture method of this semiconductor package part 1 is to shown in the accompanying drawing 2E as accompanying drawing 2A.In accompanying drawing 2A, prepare one earlier by chip carrier 100 and many lead frames 10 that pin one 01 is constituted, this chip carrier 100 also offers one and runs through the end face 100b of this chip carrier 100 and the perforate 100a of bottom surface 100c, and the edge of the perforate 100a of this chip carrier 100 also is arranged with a recess 100d who leads to this perforate 100a downwards from this end face 100b, the formation of this recess 100d can etch partially or existing mode such as punching press for it; Owing to etch partially or process for stamping is a prior art, so do not give unnecessary details for civilian at this.
Shown in accompanying drawing 2B, go up the adhesive 14 that constitutes by elargol with an amount of coating one of existing mode in the end face 100b of this chip carrier 100, the consumption of this adhesive 14 be controlled at chip 11 be bonded to (be shown in accompanying drawing 2C) on this chip carrier 100 after, this adhesive 14 micro-overflow to this recess 100d and unlikely continuation to underflow stream to the surface below of chip carrier 100.
Shown in accompanying drawing 2C, one chip 11 is placed on the end face 100b of this chip carrier 100, make this chip 11 borrow this adhesive 14 and be bonded on the chip carrier 100, and make the bottom surface 110 of chip 11 expose among the perforate 100a, and cover the nose end that this perforate 100a is positioned at the end face 100b of chip carrier 100; Flow among this recess 100d under 100 of chip 11 and chip carriers and trace because the coating of this adhesive 14 is enough to complete filling, thus chip 11 and chip carrier 100 bonding after, air between the two gets discharges fully and does not have an anxiety of gas hole generation; Simultaneously, adhesive 14 only can micro-overflow in this chip join (last slice) manufacture process to recess 100d, and flow to the surface below of chip carrier 100 under the unlikely continuation, chip join of the present invention (last slice) manufacture process is finished after no equipment or semi-finished product suffer the anxiety of adhesive 14 pollutions.
Shown in accompanying drawing 2D, the lead frame 10 that is bonded with chip 11 is carried out bonding wire operation (WireBonging), electrically connect this chip 11 to each corresponding pin one 01 with gold thread 12.Owing to the prior art that is embodied as of this bonding wire operation, so do not repeat them here.
At last, shown in accompanying drawing 2E, the semi-finished product of finishing the bonding wire operation are inserted in the mould 17, form a packing colloid 13 to coat this chip 11, chip carrier 100 and gold thread 12 by potting resin.After this packing colloid 13 forms, respectively this pin one 01 is that part exposes outside this packing colloid 13 for its coating another part, be connected with external device (ED) (not icon) for the exposed parts of this pin one 01, and make chip 11 must borrow itself and external device (ED) formation be electrically conducted relation as printed circuit board (PCB).The carrying out of this molding operation (Molding) is prior art also, so do not repeat them here.
After these packing colloid 13 moulding, give baking-curing and form the semiconductor package part of the present invention 1 shown in the accompanying drawing 1.Remove slag (Trimming), impress (Marking) and clubfoot moulding steps such as (Forming) all is as good as with prior art, so do not give unnecessary details for literary composition in addition thereafter.
Embodiment 2
Be depicted as the schematic diagram of second embodiment of the lead frame that semiconductor package part of the present invention uses as accompanying drawing 3A to accompanying drawing 3H, because roughly the same shown in itself and the accompanying drawing 1,, and only illustrated with regard to its difference so identical part is omitted in the hope of succinctly.
Shown in accompanying drawing 3A figure, this lead frame 20A is to offer a perforate 201A in its chip carrier 200A, form the section of stretching (Down-set Section) 202A downwards along the peritreme of this perforate 201A and in the mode that bends, define a recess 203A by the section of stretching 202A under this, for in order to adhesive (not icon) overflow of adhering chip (not icon) to this chip carrier 200A to this recess 203A, and avoid adhesive to flow to the bottom surface of chip carrier 200A outward.
Shown in accompanying drawing 3B, this lead frame 20B offers a perforate 201B on its chip carrier 200B, be to etch partially or existing mode such as punching press forms a recess 203B, be different from shown in the accompanying drawing 1, at the bottom surface 204B of this recess 203B is to be the state towards the risers 205B inclination of this perforate 201B by perforate 201B, that is, the degree of depth of this recess 203B is to be successively decreased towards the mode of perforate 201B by risers 205B, so, can further avoid overflow (being the direction of perforate 201B) to this recess 203B to continue excessive.
Shown in accompanying drawing 3C, this lead frame 20C is with roughly the same shown in the accompanying drawing 1, difference is in and goes up formed recess 203C in its chip carrier 200C and be arranged with out a groove 206C, makes this groove 206C provide the bigger space of this recess 203C to take in the adhesive of overflow to the recess 203C.The formation of this groove 206C can be a plurality of, or gives concavo-convexization processing on the bottom surface of recess 203C, with so that increase the excessive ability to chip carrier 200C of recess 203C retardance adhesive.
Shown in accompanying drawing 3D, the chip carrier 200D of this lead frame 20D is into the shape of X type, makes the area of the area of chip carrier 200D less than bonding with it chip 21D, and its recess 203D then is formed at the edge at the position of chip carrier 200D; The shape of this chip carrier 200D can make the bond area of chip 21D and chip carrier 200D reduce, and acts on thermal stress on the chip 21D and can reduce chip carrier 200D.Shown in accompanying drawing 3E, then be the cutaway view that the structure shown in the accompanying drawing 3D is cut open along 3E-3E figure.
Shown in accompanying drawing 3F, the chip carrier 200F of this lead frame 20F is into a strip of sheet, and forms an expansion section in its position, stage casing so that the chip 21F proper bearing capacity bonding with chip carrier 200F to be provided, and the area that makes chip 21F is greater than chip carrier 200F; Simultaneously, also be concaved with recess 203F on the edge of this chip carrier 200F, to prevent to overflow outside the adhesive of adhering chip 21F to chip carrier 200F the edge of this chip carrier 200F.Accompanying drawing 3G then is the cutaway view that the structure shown in the accompanying drawing 3F is cut open along the 3G-3G line.
Shown in accompanying drawing 3H, the chip carrier 200H of this lead frame 20H be composition from kenel, that is, chip carrier 200H is relative by two, and half one of spaced apart one suitable distance forms, be bonded to chip 21H on the chip carrier 200H and the bond area between chip carrier 200H with further minimizing, act on thermal stress on the chip 21H and must reduce chip carrier 200H; Similarly, also be concaved with recess 203H on the edge of this chip carrier 200H, to prevent the edge of adhering chip 21H to the excessive chip carrier 200H of going out of the adhesive on the chip carrier 200H.The above only is specific embodiments of the invention, and other is any not to deviate from the equivalence of being done under spirit of the present invention and the technology and change or modify, and all should still be included in claims of this patent.
Claims (17)
1. the semiconductor package part of a chip carrier tool recess is characterized in that, this semiconductor package part comprises:
One lead frame, its tool one chip carrier and many s' pin, wherein, this chip carrier offers at least one perforate, and the recess that leads to of the recessed formation one of end face and this perforate of this chip carrier certainly;
One chip, it is to borrow an adhesive to be bonded on this chip carrier, covers and make the part surface of this chip to expose outside this perforate with the nose end with this perforate;
Many conductive components are in order to connect this chip and pin conductively; And
One packing colloid, in order to coating the part of this chip, chip carrier, conducting element and pin, and to make this recess be the potting resin institute filling fully of this packing colloid of formation.
2. semiconductor package part as claimed in claim 1 is characterized in that, the concave depth of this chip carrier must be greater than the maximum particle diameter of the filler particles in the potting resin that forms this packing colloid.
3. semiconductor package part as claimed in claim 1 is characterized in that, after the consumption of this adhesive must foot make this die bonding to the chip carrier, and no gas hole generation between this chip and chip carrier, and this adhesive gets micro-overflow to this recess.
4. semiconductor package part as claimed in claim 1 is characterized in that this conductive component is a bonding wire.
5. semiconductor package part as claimed in claim 4 is characterized in that this bonding wire is a gold thread.
6. semiconductor package part as claimed in claim 1 is characterized in that, the bottom surface of this recess is to be tilted towards the direction away from this perforate by this perforate, and making this concave depth is to be increased progressively towards the direction away from this perforate by this perforate.
7. semiconductor package part as claimed in claim 1 is characterized in that, the bottom surface of this recess is to be concaved with at least one groove.
8. the semiconductor package part of a chip carrier tool recess is characterized in that, this semiconductor package part comprises:
One lead frame, its tool one chip carrier and many s' pin is characterized in that this chip carrier has many edge, to form from the recessed recess of the end face of chip carrier in this edge;
One chip be to borrow an adhesive to be bonded on this chip carrier, and its area is greater than the area of this chip carrier;
Many conductive components are in order to connect this chip and pin conductively; And
One packing colloid, in order to coating the part of this chip, chip carrier, conducting element and pin, and to make this recess be the potting resin institute filling fully of this potting resin of formation.
9. semiconductor package part as claimed in claim 8 is characterized in that, the concave depth of this chip carrier must be greater than the maximum particle diameter of the filler particles in the potting resin that forms this packing colloid.
10. semiconductor package part as claimed in claim 8 is characterized in that, after the consumption of this adhesive must foot make this die bonding to the chip carrier, and no gas hole generation between this chip and chip carrier, and this adhesive gets micro-overflow to this recess.
11. semiconductor package part as claimed in claim 8 is characterized in that, this conductive component is a bonding wire.
12. semiconductor package part as claimed in claim 11 is characterized in that, this bonding wire is a gold thread.
13. semiconductor package part as claimed in claim 8, it is characterized in that, the bottom surface of this recess is to tilt towards the direction away from the edge of chip carrier from the edge of chip carrier, and making this concave depth is to be increased progressively towards the direction away from the edge of this chip carrier by the edge of this chip carrier.
14. semiconductor package part as claimed in claim 8 is characterized in that, the bottom surface of this recess is to be concaved with at least one groove.
15. semiconductor package part as claimed in claim 8 is characterized in that, this chip carrier is to be X-shaped shape person.
16. semiconductor package part as claimed in claim 8 is characterized in that, this chip carrier is to be strip of sheet person, and its central part is to be formed with an expansion section.
17. semiconductor package part as claimed in claim 8 is characterized in that, this chip carrier is relative and half spaced apart one suitable distance is formed by two.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021231990A CN1466201A (en) | 2002-06-28 | 2002-06-28 | Semiconductor package whose chip carrier has receessed portion |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021231990A CN1466201A (en) | 2002-06-28 | 2002-06-28 | Semiconductor package whose chip carrier has receessed portion |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1466201A true CN1466201A (en) | 2004-01-07 |
Family
ID=34142314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA021231990A Pending CN1466201A (en) | 2002-06-28 | 2002-06-28 | Semiconductor package whose chip carrier has receessed portion |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1466201A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100433302C (en) * | 2004-05-13 | 2008-11-12 | 三菱电机株式会社 | Semiconductor micro device |
| CN100452381C (en) * | 2005-05-30 | 2009-01-14 | 矽品精密工业股份有限公司 | Wire rack type package of semiconductor, and wire rack |
| CN102779804A (en) * | 2011-05-13 | 2012-11-14 | 晶致半导体股份有限公司 | Semiconductor packaging piece |
| CN104103603A (en) * | 2013-04-02 | 2014-10-15 | 三菱电机株式会社 | Semiconductor device and semiconductor module |
-
2002
- 2002-06-28 CN CNA021231990A patent/CN1466201A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100433302C (en) * | 2004-05-13 | 2008-11-12 | 三菱电机株式会社 | Semiconductor micro device |
| CN100452381C (en) * | 2005-05-30 | 2009-01-14 | 矽品精密工业股份有限公司 | Wire rack type package of semiconductor, and wire rack |
| CN102779804A (en) * | 2011-05-13 | 2012-11-14 | 晶致半导体股份有限公司 | Semiconductor packaging piece |
| CN104103603A (en) * | 2013-04-02 | 2014-10-15 | 三菱电机株式会社 | Semiconductor device and semiconductor module |
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