CN1466213A - Multi-chip semiconductor package and mfg. method thereof - Google Patents
Multi-chip semiconductor package and mfg. method thereof Download PDFInfo
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- CN1466213A CN1466213A CNA021231982A CN02123198A CN1466213A CN 1466213 A CN1466213 A CN 1466213A CN A021231982 A CNA021231982 A CN A021231982A CN 02123198 A CN02123198 A CN 02123198A CN 1466213 A CN1466213 A CN 1466213A
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Abstract
A semiconductor packaging unit with multichip and its process method is that multiple first wires are connected with a first chip and the loader electrically on a chip loader, an adhesion is coated on the first chip action surface for adhering a second chip, in which, many filler particles float in the adhesion layer and their diameters must be larger than the maximum height of the first wire arc higher than the chip action surface to prevent short caused by mistouching the first wire by the second chip when it is adhered to the adhesion layer whith can obviously simplify the process and shorten working time.
Description
Technical field
The invention relates to a kind of semiconductor package part and method for making thereof, particularly have a plural chip, and be arranged at multi-chip semiconductor package and method for making thereof on the chip bearing member with folded crystal type (Stacked) about a kind of with multi-chip module.
Background technology
For the performance that improves single semiconductor package part and capacity to meet the demand of miniaturization of electronic products, semiconductor package part gives multi-chip moduleization and is into a trend.Semiconductor package part with multi-chip module (Multi chip Module) is that the chip bearing member (as substrate or lead frame) at single packaging part is gone up bonding chip more than at least two, and the bonding way between chip and chip bearing member generally has two kinds: one turns up the soil for each street is adhered on the chip bearing member, though the whole height of the unlikely increase packaging part of this kind bonding way need be laid large-area chip connecting area territory (Die Attachment Area) to be installed with the chip of requirement on chip bearing member; Simultaneously, the chip bearing member area increases, bigger thermal stress effects is often arranged when encapsulation, easily cause chip bearing member to produce warpage (Warpage) phenomenon so cause chip and chip bearing member between bonding plane peel off (Delamination), so adopt this method can have bigger reliability doubt (Reliability Concern).And another kind of die bonding mode is with folded crystal method (Stacked), chip is vertically spliced on chip bearing member one by one, though the method can increase the whole height of encapsulation finished product, but because of it can avoid the chip bearing member area too huge, and the probability of minimizing packaging part generation warpage or layering, adopt so still extensively obtain industry.
Usually adopting the multi-chip module formula semiconductor package part of the kenel of splicing is as shown in Figure 8.The semiconductor package part 6 of this kind structure is after first chip 61 bonds on the substrate 60, one second chip 64 can be adhered on first chip 61, and respectively this first chip 61 and second chip 64 be electrically connected on the substrate 60 with first gold thread 62 and second gold thread 65.But for avoiding second chip 64 that the welding that interferes with first gold thread 62 and first chip 61 is set, the size of this second chip 64 must limit must be less than these first chip, 61 sizes, therefore be stacked over the chip that leans on the upper strata more, its chip size is littler, relatively can power usable floor area that electronic circuit and electronic building brick lay just can be still less, and be unfavorable for the development trend of packaging part Highgrade integration.
For avoiding above-mentioned semiconductor package part to be subjected to the chip size limitation to have influence on the integrated degree of packaging part.United States Patent (USP) the 5th, 323, No. 060 " Multichip Module Having A StackedChip Arrangement " and the 6th, 005, No. 778 " Chip Stackingand CapacitorMounting Arrangement Including Spacers " proposes the overhanging encapsulating structure of a kind of upper strata chip and responded.Shown in the 9th figure, these semiconductor package part 6 first chips 61 bond to substrate 60, and after with many first bonding wires 62 this first chip 61 and substrate 60 conductions being connected, do not lay the glutinous barriers 63 of a tool preset thickness of establishing on the zone of weld pad in first chip, 61 action face 610, this barriers 63 can be from insulation film (Insulated Tape), do not have a pseudo-chip (Dummy Die) of chip circuit function or select for use by selecting one in the materials such as silicon sheet, but these barriers 63 height H must be greater than first bonding wire, 62 camber (Loop Height, promptly first bonding wire, 62 banks are apart from the maximum height difference of these first chip, 61 action face 610), in order to avoid second chip 64 connects and puts on the barriers 63 mistiming and contact first bonding wire 62 and cause short circuit.
The barriers setting separates the levels chip effectively and forms a difference in height greater than the first bank camber, even if make second chip reach outward the gold thread bank directly over also can not touch first bank and cause short circuit, therefore second chip size need not be restricted and can select to use more than or equal to the chip of first chip area, significantly promotes the integrated degree of multi-chip module semiconductor package part.
Yet, with the insulation film, as Polyimide (Polyimide) the tackness glue material of etc.ing as barriers when second die bonding, often bigger because of glue material flowability, fixed in shape is difficult and have influence on the flatness of second chip; And, the thermal coefficient of expansion of glue material and chip chamber (Coefficient of Thermal Expansion, CTE) difference is very big, thereby as easy as rolling off a logly under the temperature cycles of subsequent manufacturing processes makes the chip join position that warpage, layering take place or cause chip rhegma (Crack).Therefore, be to solve problems such as thermal expansion coefficient difference, the insider develops in addition not have the pseudo-chip (Dummy Die) of circuit propagation function or the silicon sheet identical with the chip material laminated crystal type semiconductor package part as barriers.Shown in the 10th figure, the process steps of this kind packaging part 6 is as follows: at first be ready for a glutinous chip bearing member 60 that first chip 61 is arranged, and on the action face 610 of this first chip 61 coating one first adhesion layer 613, then, with the barriers 63 of a preset height bond on this first adhesion layer 613 baking fixing after, through the routing step this first chip 61 and 60 formation of chip bearing member are electrically conducted, then make second chip 64 borrow second adhesion layer of coating on the barriers 63 614 to bond on the barriers 63, make second chip 64 and chip bearing member 60 form electric connection through baking and routing step again, promptly form the semiconductor package part 6 of the folded crystal structure of a tool.
Though this method can successfully overcome the thermal coefficient of expansion problem between chip and barriers, the cost of said method is very high, and the process steps too complex, and the production cycle is long and be difficult to increase output.Moreover; group spacing body or upper strata chip (i.e. second chip) will use adhesive to coat on the first chip action face or the barriers surface before bonding earlier so that carry out last slice operation; yet mobile high adhesive regular meeting causes barriers or upper strata chip generation off normal or occurs being stained with glue unusual; jelly overflow even pollute situations such as first chip pad is so product still has the doubt of fraction defective height and chip join reliability deficiency.
In view of this, United States Patent (USP) the 6th, 388 is invented again for No. 313 and a kind of part first bonding wire directly to be embedded in the adhesive, makes the laminated crystal type method for packing of the unlikely false touch gold thread of second chip that is engaged on the adhesive.Shown in the 11st figure, this method and aforementioned quite similar as the mode of barriers: at first with adhesive, on first chip, 61 action face, 610 each bond pad locations, form corresponding salient point 620 (Stud), with backstep welding connection technology (Reverse Bond) end is welded on this salient point 620 with the other end of first bonding wire 62 of chip bearing member 60 welding again; Afterwards, borrow screen printing methods such as (Print Screening) that adhesive 63 is applied to and reach certain thickness on first chip, 61 action face 610, make first bonding wire 62 that is positioned at first chip, 61 tops be embedded in adhesive 63 fully, one second chip 64 is pressure bonded to finishes the folded brilliant step of chip on the gluing layer 63 again.
This method for packing is earlier to reduce bonding wire camber (camber only have an appointment 2 Mills) with the backstep welding connection technology, envelope the part bank and the gluing layer is slightly thickened with adhesive again and make the unlikely false touch gold thread of second chip, therefore, the thickness of gluing layer can be reduced to minimum and can reduce the whole height that encapsulates finished product.Yet the salient point that provides bonding wire to link must be provided on first chip earlier above-mentioned backstep welding connection technology, so cost can be spun out and increase to production process; Simultaneously, the thermal expansion coefficient difference between adhesive and gold thread is very big, so the gold thread that also easily causes being coated in the glue material because of different thermal stress under the temperature cycles of subsequent manufacturing processes ruptures, has a strong impact on the gold thread electrical functionality; In addition, in the second chip join process for avoiding the careless false touch gold thread of the non-action face of this chip to produce short circuit, machine must accurate control second chip must be set up the equipment that improves precision to the pressure force (BondForce) of gluing layer, and right this measure also can obviously increase packaging cost.
Summary of the invention
Main purpose of the present invention is promptly providing a kind of utilization existing equipment and method can reach the simplification process steps, shortens the multi-chip semiconductor package and the method for making thereof of production process and reduction packaging cost.
A further object of the present invention reduces gluing layer and levels chip chamber thermal coefficient of expansion gap providing a kind of, obviously promotes the multi-chip semiconductor package and the method for making thereof of product fine rate in order to avoid phenomenon such as layering, chip rhegma or gold thread fracture takes place at the chip join position.
Another object of the present invention is providing a kind of lifting levels chip chamber heat dissipation, and the heat when helping to improve folded crystal structure running accumulates the multi-chip semiconductor package and the method for making thereof of problem.
Another purpose of the present invention is providing a kind of reduction adhesive flowability, makes the upper strata die bonding can keep the multi-chip semiconductor package and the method for making thereof of excellent planar degree to the gluing layer.
Another purpose of the present invention is providing a kind of chip selecting the multi-chip semiconductor package and the method for making thereof of no size restriction for use.
Another purpose of the present invention is providing a kind of gluing layer thickness that reduces the levels chip chamber, to reduce the multi-chip semiconductor package and the method for making thereof of the whole height that encapsulates finished product.
Another purpose of the present invention is providing a kind of gluing layer thickness of controlling the levels chip chamber, causes the multi-chip semiconductor package and the method for making thereof of gold thread fracture or short circuit to avoid the upper strata chip to touch the gold thread on lower floor's chip.
Above-mentioned and other purpose according to the present invention, multi-chip semiconductor package provided by the invention is to comprise a chip bearing member; At least one first chip, it has an action face and a relative non-action face, makes this first chip bonding by its non-action face and this chip bearing member; Many first bonding wire, one end are to be welded on the action face of this first chip, and the other end then is soldered on this chip bearing member, first chip and chip bearing member can be provided by this first bonding wire be electrically conducted; At least one second chip, it has an action face and a relative non-action face; One gluing layer, be to coat on the action face of this first chip, be suspended with the particle of a plurality of decision gluing layer thicknesses in this gluing layer, after making this second chip borrow its non-action face to bond on this first chip, the gluing layer thickness between first and second chip is greater than this first bank camber; Many second bonding wire is in order to electrically connect this second chip and chip bearing member; And a packing colloid, so as to coating this first chip, first bonding wire, second chip and second bonding wire.
Multi-chip semiconductor package method for making of the present invention then comprises following steps: at first be ready for a chip bearing member, more at least one first chip be adhered on this chip bearing member, this first chip has an action face and a non-action face; Then, connect this first chip action face and this chip bearing member, make and form the relation that is electrically conducted between this first chip and chip bearing member with many first bonding wire welderings; Then, an adhesive is applied on this first chip action face, contains the suspended particulate of a plurality of preset height in this adhesive, so as to determining the coating layer thickness of this adhesive; Borrow this adhesive to bond on first chip at least one second chip again, wherein, the gluing layer thickness that is formed at this first and second chip chamber must be greater than this first bank camber; Afterwards, electrically connect this second chip to this chip bearing member with many second bonding wires; Carry out mold pressing and other subsequent manufacturing processes again.
Another embodiment of multi-chip semiconductor package of the present invention is to form the multi-chip module formula encapsulating structure of three chips that splice on the chip bearing member at bonding again one the 3rd chip on second chip, because the height of adhesive inner suspension particle is greater than the bank camber, therefore the 3rd chip must not worried probably the false touch gold thread and chip size is limited to some extent, makes in the same packaging part and can hold more identical chips.
An embodiment again of multi-chip semiconductor package of the present invention is the bank height that utilization backstep welding connection technology (Reverse Bond) reduces first bonding wire, make suspended particulate can adopt the diameter smaller particles to reduce the gluing layer thickness, reach the purpose of reduction packaging part whole height then.
Compared to the many disadvantages that prior art produces, the solution that the present invention proposes is to sneak into many suspended particulates in insulating properties or the agent of conductivity gluing, decides the gluing layer thickness of levels chip chamber by the particle diameter of control suspended particulate.This suspended particulate should cooperate the maximum height (promptly the max line arc-height of being counted by the chip action face is called for short the bank camber) of the first bonding wire bank to select the granular size that is fit to; The camber higher (being about 4 Mills) that when first bonding wire adopts general routing technology to weld, obtains, therefore should select particle diameter the particle of big (the particle height is bigger) can make the gluing layer have bigger height, and if this first bonding wire is to carry out routing with the backstep welding connection technology, owing to oppositely weld the camber less (being about 2 Mills) that forms, so can select the particle diameter smaller particles to mix in the adhesive, cause short circuit for avoiding second chip and first bonding wire to touch, the particle diameter of suspended particulate must not be smaller or equal to the first bonding wire camber.
Suspended particulate can be made by Metal Ball such as insulating properties macromolecule polymer material, copper, aluminium and alloy thereof or other rigidity and all good materials of thermal conductivity, therefore by the adding of suspended particles, can change the constituent characteristic of adhesive, the thermal coefficient of expansion that makes adhesive reduces and can reduce the bigger problem of thermal stress gap between adhesive and chip and bonding wire, in order to avoid problems such as chip join position generation layering, chip rhegma even gold thread fractures.In addition, in the adhesive of semi liquid state, sneak into the flowability that solids also can effectively reduce the glue material, can not produce off normal after making this second chip pressing to the gluing layer and can keep preferable flatness; And the suspended particulate that metal material is made also can strengthen the heat dissipation of chip, so the heat that helps to solve when folding the crystal structure running accumulates problem.
Description of drawings
Below further describe characteristics of the present invention and effect with the preferred embodiment conjunction with figs.:
Accompanying drawing 1 is the cut-away view of the multi-chip semiconductor package of first embodiment of the invention;
Accompanying drawing 2 is after semiconductor package part of the present invention is finished the first gold thread routing and cloth glue, the local enlarged diagram of this gluing layer and the first gold thread bank;
Accompanying drawing 3A is the making flow chart of the multi-chip semiconductor package of first embodiment of the invention to accompanying drawing 3F;
Accompanying drawing 4 is cut-away views of the multi-chip semiconductor package of second embodiment of the invention;
Accompanying drawing 5 is cut-away views of the multi-chip semiconductor package of third embodiment of the invention;
Accompanying drawing 6 is cut-away views of the multi-chip semiconductor package of fourth embodiment of the invention;
Accompanying drawing 7 is cut-away views of the multi-chip semiconductor package of fifth embodiment of the invention;
Accompanying drawing 8 is cut-away views of existing laminated crystal type semiconductor package part;
Accompanying drawing 9 is cut-away views of existing the 5th, 323, No. 060 multi-chip semiconductor package of United States Patent (USP);
Accompanying drawing 10 is cut-away views of existing the 6th, 005, No. 778 multi-chip semiconductor packages of United States Patent (USP); And
Accompanying drawing 11 is cut-away views of existing the 6th, 388, No. 313 multi-chip semiconductor packages of United States Patent (USP).
Symbol description
1,2,3,4,5,6 semiconductor package parts, 10,30,60 substrates
100 substrate top surfaces, 101 substrate bottom surface
50 lead frames, 500 chip carriers
501 pins
11,21,31,41,51,61 first chips
110,310,610 first chip action face
The non-action face of 111 first chips
112 elargol, 613 first adhesion layers
614 second adhesion layers
12,32,42,52,62 first gold thread 320,620 salient points
13,23,33,43 gluing layers, 63 barriers
130,430 glue material matrix
131,231,331,431 suspended particulates, 14,24,34,44,64 second chips
240 second chip action face
The non-action face of 141 second chips
15,25,55,65 second gold thread 16,46 packing colloids
17 soldered balls 28 the 3rd chip
The h first bank camber
H gluing layer height (grain diameter)
H ' second bank the camber
Embodiment
Below promptly cooperate each embodiment to describe multi-chip semiconductor package of the present invention and method for making thereof in detail with accompanying drawing, assembly kind, component count and the structure of each accompanying drawing are only simply drawn by the embodiment content, be not to make according to equal proportion in kind, the enforcement structure of the reality of multi-chip semiconductor package of the present invention and pattern should be more complicated than accompanying drawing.
Embodiment 1
Accompanying drawing 1 is depicted as the generalized section of the multi-chip semiconductor package of first embodiment of the invention.As shown in the figure, this semiconductor package part 1 includes a substrate 10, be attached to one first chip 11 on this substrate 10, many first gold threads 12 that provide this substrate 10 and first chip 11 to electrically connect, coat the gluing layer 13 on this first chip 11, be bonded to second chip 14 on this gluing layer 13, in order to many second gold threads 15 of second chip, 14 electrically connects to substrate 10, and in order to coat the packing colloid 16 of this first chip 11, first gold thread 12, second chip 14 and second gold thread 15.
This substrate 10 is to adopt general bilayer or multiple field substrate, that is the conductive trace (Conductive Trace Pattern) that laying is formed by Copper Foil (Copper Foil) etching on a upper and lower surface of basic unit of being made by materials such as resin, pottery or glass cloth, this kind substrate is for now using structure, so do not repeat in addition to give unnecessary details in this.This substrate 10 has an end face 100 and an opposed bottom surface 101, a plurality of zones that provide chip and gold thread to connect and put (not icon) are provided in definition on this end face 100, substrate 10 bottom surfaces 101 are then planted and are connected to into the array mode and are listed as the soldered ball of putting 17, can borrow this soldered ball 17 to electrically connect with extraneous for first chip 11 and second chip 14 that are adhered on the substrate 10.
This first chip 11 is to bond on the predeterminated position of substrate 10 end faces 100 as elargol (Silver Paste) or Polyimide (PolyimideTape) film 112 etc., it has an action face 110 and a relative non-action face 111, one-sided, bilateral or all sides of these first chip, 11 action face 110 are laid with many weld pads (not icon), make first chip 11 last slice (Die Bonding) to substrate 10 after, this first gold thread 12 can borrow weld pad (not icon) to link with the home loop with this first chip 11.
After first gold thread, 12 weld jobs are finished, this adhesive 13 can be coated the zone of not laying weld pad on first chip, 11 action face 110.This adhesive 13 is to be matrix by insulation such as Polyimide resin, epoxy resin or conductive paste material 130, sneak into a plurality of particles 131 and evenly stir made colloid substance, wherein, the coating layer thickness of this adhesive 13 is to determine by this particle 131 that is suspended in the glue material 130.The size of suspended particulate 131 (is a particle diameter, hereinafter to be referred as particle diameter) must be in advance through control, as shown in Figure 2, the gluing layer 13 coating layer thickness H that are formed at 14 of first chip 11 and second chips depend on particle 131 particle diameters (also claiming H) that are suspended in the glue material 130, grain diameter H scope is generally between 1 to 8 Mill, and the preferably is 5 Mills; The particle diameter H of this particle 131 must exceed the maximum height h (being the bank camber) of first chip, 11 action face 110 greater than these first gold thread, 12 banks, and mistiming contacts the 12 initiation short circuits generations of first gold thread on the adhesive 13 in order to avoid second chip 14 presses to.
Particles 131 in the adhesive 13 are to have the material of good rigidity (Rigidity) and thermal conductivity by the high molecular polymer material or as copper, aluminium, copper alloy (as CuW), aluminium alloy metal materials such as (as AlN) and other, make as carbon-silicon compound or silicon grain etc.Can form improper being electrically conducted when avoiding the good suspended particulate of electrical conductivity 131 to touch gold thread or chip, particle 131 surfaces that have the specified particle diameter size after the polishing must be looked actual needs and cover an insulating properties thin layer (not icon) outward.On the other hand, in the great glue material 130 of thermal coefficient of expansions such as epoxy resin or Polyimide, sneak into suspended particulate 131, can reduce the thermal coefficient of expansion of adhesive 13 finished products, then reduce adhesive 13 and chip 11,14 thermal stress poor be not so cause the chip join position to produce situations such as layering, chip rhegma; Again and, the suspended particulate of making as metal materials such as copper aluminium 131 provides good thermal conductivity for adhesive 13, the heat that produces when therefore first chip 11 and second chip 14 operate must be passed to external environment fast by suspended particulate 131, and the heat that helps to solve folded crystal structure is accumulated problem.
In addition, because this particle 131 particle diameter H only need exceed first gold thread, 12 camber, make these second chip, 14 unlikely first gold threads 12 that touch get final product, therefore interior in the industry scholar can effectively control the thickness of this gluing layer 13, make that second chip 14 is glutinous establishes overall package part 1 height to first chip 11 than aforesaid U.S. Patent the 5th, the packaging part of 323, No. 060 case inventions is low, and suits the thinning trend of semiconductor package part more.Moreover, in the glue material matrix 130 of semi liquid state, add the flowability that solids more can reduce adhesive 13, can keep preferable flatness after making second chip 14 press on the adhesive 13, and the unlikely problems such as chip displacement or jelly overflow that occur.
After second chip 14 bonds to adhesive 13, be to utilize many second gold threads 15 that this second chip 14 is electrically connected on the substrate 10.Because being formed at that gluing layer 13 thickness of 14 of first chip 11 and second chips limit in advance must be greater than first gold thread, 12 camber, therefore, even second chip 14 of finishing slice stretches out first gold thread, 12 tops outward and does not also have the doubt of false touch gold thread, and makes this second chip 14 have bigger selection space on chip kind and chip size.
Then, in addition describe the making flow process of multi-chip semiconductor package of the present invention with accompanying drawing 3A in detail to accompanying drawing 3F, each definition of thin portion and component Name in this package structure have been chatted brightly because of previous embodiment, satisfy heavily not give in addition at this and give unnecessary details.
Shown in accompanying drawing 3A and accompanying drawing 3B, be ready for a substrate 10 earlier, be preset with a chip connecting area (not icon) on this substrate 10, in modes such as a glue or picture glue elargol 112 is coated on this chip connecting area again, bonding for one first chip 11.
Shown in accompanying drawing 3C, now first chip 11 is electrically conducted with substrate 10 with the bonding wire operation; Wherein, this bonding wire operation be after baking procedure (Die Bond Curing) finishes again with wire bonder (Bonder) (not icon) with an end scorification of this first gold thread 12 and be welded on the weld pad (not icon) of first chip, 11 action face 110, drawing outer this first gold thread 12 that draws again welds with the wire bond pad (Fingers) (not icon) with this substrate 10 to substrate 10, so after the bonding wire operation was finished, these first gold thread, 12 banks can exceed first chip, 11 action face, 110 1 bank height h.
Shown in accompanying drawing 3D, now be coated on first chip, 11 action face 110 with screen printing (Print Screening) or other with the adhesive 13 that the cloth gluing method will be mixed with default particle diameter particle 131, the thickness H of these adhesive 13 coatings determined by the suspended particulates 131 in the adhesive 13, and the particle size of this suspended particulate 131 must be greater than the first bank camber (be among the accompanying drawing 3C shown in the h).
Then, shown in accompanying drawing 3E, bestow an operation, make second chip 14 borrow its non-action face 141 to press on this gluing layer 13, because suspended particulate 131 particle diameters of adhesive 13 are greater than first bonding wire, 12 camber, therefore, when machine (not icon) pressing second chip 14 is to gluing layer 13, this machine need not worry that second chip 15 probably forms improper being electrically conducted with first gold thread 12 and control chip pressure force (Bond Force) painstakingly, effectively reduces production cycle and packaging cost then.
Shown in accompanying drawing 3F, this second chip 14 and substrate 10 also can adopt to conduct electricity as aforementioned bonding wire method and be connected.After treating that second gold thread 15 is finished welding, the structure that will be formed with first chip 11, gluing layer 13, second chip 14 and substrate 10 places encapsulating mould (not icon) to carry out molding operation (Molding), to go out to coat the packing colloid (shown in accompanying drawing 116) of this first chip 11, first gold thread 12, second chip 14 and second gold thread 15 by the potting resin curing molding, promptly finish the process steps of multi-chip semiconductor package 1 of the present invention.
Embodiment 2
Accompanying drawing 4 is depicted as the generalized section of the multi-chip semiconductor package of second embodiment of the invention.As shown in the figure, the semiconductor package part structure 2 of this second embodiment is roughly the same with the structure of aforementioned first embodiment, its difference is in this second chip 24 after 25 welding of second gold thread are finished, in addition go up and apply an adhesive 23, bonding at least one the 3rd chip 28 and form the multi-chip module formula encapsulating structure 2 of three chips that splice on the substrate 20 in the weld pad zone (not icon) that is provided with of second chip, 24 action face 240; Coat and also be suspended with many particle diameters particle 231 through screening in advance in the adhesive 23 on this second chip 24, and the particle size of this particle 231 also must be greater than the second bank camber h '.Therefore, also needn't take into account last the time as aforementioned second chip, 24, the three chips 28 and probably touch and to many restrictions of chip size, the 3rd chip 28 also can be selected the semiconductor chip more than or equal to these first or second chip, 21,24 sizes with second gold thread 25.
Embodiment 3
Accompanying drawing 5 is depicted as the generalized section of the multi-chip semiconductor package of third embodiment of the invention.As shown in the figure, the semiconductor package part structure 3 of the 3rd embodiment is roughly the same with the structure of aforementioned first embodiment, and it is to adopt backstep welding connection technology (Reverse Bond) that its difference is in the welding manner of first gold thread 32; That is, on action face 310 weld pads of first chip 31, form pedestal 320 (Stud) earlier, then first gold thread, 32 1 ends elder generations sintering is welded on the wire bond pad (not icon) of substrate 30, the lashing wire line sews the other end of this first gold thread 32 to connect (Stitch Bond) to this salient point 320 and finish the weld job of first gold thread 32 in drawing on again.Utilize the backstep welding connection technology can change the bank trend, make the bank height of first chip, 31 tops become minimum (about 2 Mills are following), therefore the suspended particulate 331 in the gluing layer 33 can adopt the less particle of diameter to reduce gluing layer 33 thickness, with the whole height of reduction packaging part 3 finished products.
Embodiment 4
Accompanying drawing 6 is depicted as the generalized section of the multi-chip semiconductor package of fourth embodiment of the invention.As shown in the figure, the semiconductor package part structure 4 of the 4th embodiment is roughly the same with the structure of aforementioned first embodiment, it is to be filled in fully between first chip 41 and second chip 44 that its difference is in this gluing layer 43, comprise be positioned at first chip, 41 tops first gold thread, 42 parts all complete packet be overlying on this gluing layer 43, so gluing layer 43 is highly unlikely influenced by camber to become blocked up in order to make, and present embodiment encapsulating structure 4 is to adopt the backstep welding connection technology to weld this first gold thread 42.On the other hand, because adhesive has insulating properties matrigel material 430 to isolate for 43 li, and also be coated with an insulating properties thin layer in advance, so even the gold thread 42 that is coated in the adhesive 43 contacts also unlikely short circuit with suspended particulate 431 by suspended particulate 431 surfaces that insulating properties high molecular polymer or copper aluminium material matter make; And, 44 of this first chip 41 and second chips because of 43 coating of gluing layer fully tight exist, so can not form bubble (Void) during these packing colloid 46 moulding at first chip 41 and 44 of second chips, packaging part 4 is unlikely gas explosion (Popcorn) takes place in the follow-up high temperature manufacture process, and can guarantee the property of fine qualities of manufactured goods.
Embodiment 5
Accompanying drawing 7 those shown are the generalized section of the multi-chip semiconductor package of fifth embodiment of the invention.As shown in the figure, the semiconductor package part structure 5 of the 5th embodiment is roughly the same with the structure of aforementioned first embodiment, it is glutinous being located on the chip carrier 500 of a lead frame 50 that its difference is in this first chip 51, so an end of this first gold thread 52 and second gold thread 55 all can be welded on chip carrier 500 lead frame 50 pins 501 on every side, to borrow this pin 501 for this first chip 51 and second chip 54 and extraneous electric connection.
The above is preferred embodiment of the present invention only, is not in order to limit essence technology contents scope of the present invention.Essence technology contents of the present invention is broadly to be defined in claims; any technology entity or method that other people are finished; if identical with the definien of institute in claims, or be a kind of change of equivalence, all will be regarded as being covered by within this scope of patent protection.
Claims (34)
1. a multi-chip semiconductor package is characterized in that, this multi-chip semiconductor package is to comprise:
One chip bearing member;
At least one first chip, this first chip have an action face and a relative non-action face, make this first chip bonding by its non-action face and this chip bearing member;
Many first bonding wire, one end are to be welded on the action face of this first chip, and the other end then is soldered on this chip bearing member, make between this first chip and this chip bearing member to be electrically conducted;
At least one second chip, it has an action face and a relative non-action face;
One gluing layer, be to coat on the action face of this first chip, this gluing layer inner suspension has the particle of many decision gluing layer thicknesses, after making this second chip bond on this first chip with its non-action face, the gluing layer thickness that is formed at first and second chip chamber can be greater than this first bonding wire camber;
Many second bonding wire is in order to electrically connect this second chip and chip carrier; And
One packing colloid is in order to coat this first chip, first bonding wire, second chip and second bonding wire.
2. multi-chip semiconductor package as claimed in claim 1 is characterized in that, this multi-chip semiconductor package is a laminated crystal type semiconductor package part.
3. multi-chip semiconductor package as claimed in claim 1 is characterized in that, this chip bearing member is a substrate.
4. multi-chip semiconductor package as claimed in claim 1 is characterized in that, this chip bearing member is a lead frame.
5. multi-chip semiconductor package as claimed in claim 1 is characterized in that, this first bonding wire is a gold thread.
6. multi-chip semiconductor package as claimed in claim 1 is characterized in that, this gluing layer is the colloid substance that evenly is suspended with a plurality of particles in the glue material matrix.
7. multi-chip semiconductor package as claimed in claim 6 is characterized in that, this glue material matrix is an insulating properties glue material.
8. multi-chip semiconductor package as claimed in claim 6 is characterized in that, this glue material matrix is a conductive paste material.
9. multi-chip semiconductor package as claimed in claim 6 is characterized in that, this glue material matrix is be selected from cohorts that material is formed such as epoxy resin, Polyimide a kind of made.
10. multi-chip semiconductor package as claimed in claim 6 is characterized in that, this suspended particulate is be selected from cohorts that material is formed such as copper, aluminium, copper alloy, aluminium alloy, carbon-silicon compound, silicon a kind of made.
11. multi-chip semiconductor package as claimed in claim 6 is characterized in that, this suspended particulate is made by an insulating properties high molecular polymer material.
12. multi-chip semiconductor package as claimed in claim 6 is characterized in that, this suspended particulate is that the material of a high-termal conductivity and rigidity is made.
13. multi-chip semiconductor package as claimed in claim 6 is characterized in that, this suspended particulate surface-coated one insulating properties thin layer.
14. multi-chip semiconductor package as claimed in claim 1 is characterized in that, the thickness of this gluing layer is that the particle diameter by this suspended particulate is determined.
15. multi-chip semiconductor package as claimed in claim 1 is characterized in that, the particle diameter of this suspended particulate is greater than the camber of this first bonding wire.
16. multi-chip semiconductor package as claimed in claim 1 is characterized in that, this first bonding wire camber is meant that the first bonding wire bank exceeds the maximum height of this first chip action face.
17. a multi-chip semiconductor package method for making is characterized in that, this method for making comprises following steps:
Be equipped with a chip bearing member;
At least one first chip is adhered on this chip bearing member, and this first chip has an action face and a non-action face;
Connect this first chip action face and this chip carrier with many first bonding wire welderings, this first chip is electrically conducted to chip bearing member;
One adhesive is applied on this first chip action face, and this adhesive inner suspension has the particle of many tool preset height, to borrow the formation thickness of this particle decision gluing layer;
Make at least one second chip borrow this adhesive to bond on first chip, it is characterized in that its thickness of gluing layer that is formed at this first and second chip chamber is greater than this first bonding wire camber;
Electrically connect this second chip to this chip bearing member with many second bonding wires; And
Coat this first chip, first bonding wire, second chip and second bonding wire with a packing colloid.
18. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, this multi-chip semiconductor package is a laminated crystal type semiconductor package part.
19. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, this chip bearing member is a substrate.
20. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, this chip bearing member is a lead frame.
21. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, this first bonding wire is to weld with the backstep welding connection technology.
22. multi-chip semiconductor package method for making as claimed in claim 21 is characterized in that, before backstep welding connection technology weldering even this first bonding wire, must form several pedestals earlier on this first wafer action face.
23. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, this gluing layer is to be applied on this first chip with the screen printing technology.
24. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, this gluing layer is the colloid substance that evenly is suspended with a plurality of particles in the glue material matrix.
25. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, this glue material matrix is an insulating properties glue material.
26. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, this glue material matrix is a conductive paste material.
27. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, this glue material matrix is be selected from cohorts that material is formed such as epoxy resin, Polyimide a kind of made.
28. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, this suspended particulate is be selected from cohorts that material is formed such as copper, aluminium, copper alloy, aluminium alloy, carbon-silicon compound, silicon a kind of made.
29. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, this suspended particulate is made by an insulating properties high molecular polymer material.
30. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, this suspended particulate is that the material of a high-termal conductivity and rigidity is made.
31. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, this suspended particulate surface-coated one insulating properties thin layer.
32. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, the thickness of this gluing layer is that the particle diameter by this suspended particulate is determined.
33. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that the particle diameter of this suspended particulate is greater than the camber of this first bonding wire.
34. multi-chip semiconductor package method for making as claimed in claim 17 is characterized in that, this first bonding wire camber is meant that the first bonding wire bank exceeds the maximum height of this first chip action face.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021231982A CN100361301C (en) | 2002-06-28 | 2002-06-28 | Multi-chip semiconductor package and mfg. method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021231982A CN100361301C (en) | 2002-06-28 | 2002-06-28 | Multi-chip semiconductor package and mfg. method thereof |
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| CN1466213A true CN1466213A (en) | 2004-01-07 |
| CN100361301C CN100361301C (en) | 2008-01-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB021231982A Expired - Fee Related CN100361301C (en) | 2002-06-28 | 2002-06-28 | Multi-chip semiconductor package and mfg. method thereof |
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| CN (1) | CN100361301C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100343964C (en) * | 2004-02-13 | 2007-10-17 | 旺宏电子股份有限公司 | Multiple chip packaging arrangement |
| CN100437990C (en) * | 2005-03-17 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Strain silicon wafer with a crystal orientation (100) in flip chip bga package |
| CN102097342A (en) * | 2010-11-29 | 2011-06-15 | 南通富士通微电子股份有限公司 | Packaging system and method for controlling thickness of chip loading adhesive |
| CN110444528A (en) * | 2018-05-04 | 2019-11-12 | 晟碟信息科技（上海）有限公司 | Semiconductor device comprising illusory pull-down wire bonding |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04152642A (en) * | 1990-10-17 | 1992-05-26 | Fujitsu Ltd | Paste for adhesion use |
| US5328079A (en) * | 1993-03-19 | 1994-07-12 | National Semiconductor Corporation | Method of and arrangement for bond wire connecting together certain integrated circuit components |
| US5323060A (en) * | 1993-06-02 | 1994-06-21 | Micron Semiconductor, Inc. | Multichip module having a stacked chip arrangement |
| JP2605970B2 (en) * | 1993-06-21 | 1997-04-30 | 日本電気株式会社 | Die bonding resin for semiconductor chip and semiconductor device using the same. |
| JP2000260912A (en) * | 1999-03-05 | 2000-09-22 | Fujitsu Ltd | Method and structure for mounting semiconductor device |
| US6388313B1 (en) * | 2001-01-30 | 2002-05-14 | Siliconware Precision Industries Co., Ltd. | Multi-chip module |
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2002
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100343964C (en) * | 2004-02-13 | 2007-10-17 | 旺宏电子股份有限公司 | Multiple chip packaging arrangement |
| CN100437990C (en) * | 2005-03-17 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Strain silicon wafer with a crystal orientation (100) in flip chip bga package |
| CN102097342A (en) * | 2010-11-29 | 2011-06-15 | 南通富士通微电子股份有限公司 | Packaging system and method for controlling thickness of chip loading adhesive |
| CN102097342B (en) * | 2010-11-29 | 2013-04-17 | 南通富士通微电子股份有限公司 | Packaging system and method for controlling thickness of chip loading adhesive |
| CN110444528A (en) * | 2018-05-04 | 2019-11-12 | 晟碟信息科技（上海）有限公司 | Semiconductor device comprising illusory pull-down wire bonding |
| CN110444528B (en) * | 2018-05-04 | 2021-04-20 | 晟碟信息科技（上海）有限公司 | Semiconductor device including dummy pull-down wire bond |
| US11031372B2 (en) | 2018-05-04 | 2021-06-08 | Western Digital Technologies, Inc. | Semiconductor device including dummy pull-down wire bonds |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100361301C (en) | 2008-01-09 |
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Granted publication date: 20080109 Termination date: 20170628 |