JPH04152642A - Paste for adhesion use - Google Patents

Paste for adhesion use

Info

Publication number
JPH04152642A
JPH04152642A JP27822090A JP27822090A JPH04152642A JP H04152642 A JPH04152642 A JP H04152642A JP 27822090 A JP27822090 A JP 27822090A JP 27822090 A JP27822090 A JP 27822090A JP H04152642 A JPH04152642 A JP H04152642A
Authority
JP
Japan
Prior art keywords
filler
fillers
particle diameter
binder resin
powder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27822090A
Other languages
Japanese (ja)
Inventor
Masataka Mizukoshi
正孝 水越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP27822090A priority Critical patent/JPH04152642A/en
Publication of JPH04152642A publication Critical patent/JPH04152642A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

PURPOSE:To keep constant the film thickness of an adhesion layer by a method wherein a binder resin and a solvent are added to first fillers, which are spherical insulators, have a particle diameter of a specified value and are made uniform in size, and a second filler, which is insulator powder having a superior heat conductivity and has a particle diameter smaller than that of the first fillers, and the fillers, the binder resin and the solvent are kneaded. CONSTITUTION:An adhesion layer 7 between a substrate 2 and a semiconductor chip 1, which is installed on this substrate 1, is constituted of first fillers 9 to determine the thickness of the layer 7, a second filler 10 to dissipate heat generated in the chip 1 and a binder resin 11 to work as a bonding agent. The fillers 9 are formed of an insulator, which is spherical and has a constant particle diameter, and is limited to fillers of a particle diameter in a range of 50 to 30mum so as to be able to obtain a stable adhesive strength. Glass and heat-resistant plastic are used for the fillers 9. The filler 10 is insulating material powder having a superior heat conductivity, the powder overlaps each other and the filler 10 is limited to a filler of a particle diameter of 2 to 5mum. An aluminum nitride (AlN), boron nitride (BN), diamond powder or the like is used for the filler 10. As the binder resin, a heat-resistant resin, such as an epoxy resin, a polyimide resin or the like, is used.

Description

【発明の詳細な説明】 〔概要〕 半導体チップの搭載に使用する接着用ペーストに関し、 接着強度の安定化を目的とし、 球状の絶縁物よりなり、粒径が５０〜３００μｍで大き
さの揃った第１のフィラーと、熱伝導率の優れた絶縁物
の粉末よりなり、該第１のフィラーに較べて粒径が格段
に小さい第２のフィラーとを主成分とし、該フィラーに
バインダ樹脂と溶剤とを添加して混練してなることを特
徴として接着用ペーストを構成する。[Detailed Description of the Invention] [Summary] Regarding the adhesive paste used for mounting semiconductor chips, for the purpose of stabilizing the adhesive strength, the adhesive paste is made of a spherical insulating material and has a uniform particle size of 50 to 300 μm. The main components are a first filler and a second filler that is made of an insulating powder with excellent thermal conductivity and has a much smaller particle size than the first filler, and the filler is mixed with a binder resin and a solvent. The adhesive paste is made by adding and kneading.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体パッケージを構成する金属板上に半導体
チップを搭載するのに使用する接着用ペーストに関する
。The present invention relates to an adhesive paste used for mounting a semiconductor chip on a metal plate constituting a semiconductor package.

半導体チップをセラミック・パッケージに搭載する方法
として、当初は金・錫（Ａｕ−Ｓｎ）の共晶合金などが
使用されていたが、回路上の特性から半導体チップをパ
ッケージの基板電位から浮かせて使用する場合がある。Initially, a eutectic alloy of gold and tin (Au-Sn) was used to mount a semiconductor chip on a ceramic package, but due to circuit characteristics, the semiconductor chip was floated above the package's substrate potential. There are cases where

特に、高周波用のチップについてはノイズを低減するた
めに基板電位から絶縁して使用することが必要であり、
エポキシ系やポリイミド系の樹脂ペーストを用いて接着
固定が行われている。In particular, high frequency chips must be used insulated from the substrate potential to reduce noise.
Adhesive fixation is performed using epoxy or polyimide resin paste.

〔従来の技術〕[Conventional technology]

第３図は高周波デバイスに使用する半導体パッケージの
断面図を示すものであり、半導体チップｌは基板２より
絶縁して装着されている。FIG. 3 shows a cross-sectional view of a semiconductor package used for a high frequency device, in which a semiconductor chip 1 is mounted insulated from a substrate 2.

こ−で、パッケージの構造を示すと次のようになる。The structure of the package is shown below.

すなわち、基板２はタングステン（Ｗ）やモリブデン（
Ｍｏ）などの焼結体に銅（Ｃｕ）などを浸み込ませた複
合材よりなり、この上に半導体チップエを装着するため
、アルミナ（ＡＩ！ｚｏｓ）などからなるセラミックス
層３が設けられている。That is, the substrate 2 is made of tungsten (W) or molybdenum (
It is made of a composite material in which copper (Cu) etc. is infiltrated into a sintered body such as Mo), and a ceramic layer 3 made of alumina (AI!ZOS) etc. is provided on top of this to attach a semiconductor chip. There is.

また、基板２の上にはＡｌｚＣｈなどのセラミックスよ
りなる枠体４が設けられてあり、リード端子５と半導体
チップ１を結ぶ導体パターンが形成されている。Further, a frame body 4 made of ceramics such as AlzCh is provided on the substrate 2, and a conductive pattern connecting the lead terminals 5 and the semiconductor chip 1 is formed.

また、枠体４の上面はメタライズされており、半導体チ
ップ１の装着が終わった後はコバールなどの金属よりな
る蓋６を半田付けし、これによりインピーダンス整合さ
れたハーメチックシール構造が形成されている。Further, the upper surface of the frame 4 is metallized, and after the semiconductor chip 1 is mounted, a lid 6 made of metal such as Kovar is soldered, thereby forming a hermetic seal structure with impedance matching. .

ニーで、半導体チップｌの搭載法として従来は、セラミ
ック層３の上にエポキシやポリイミドを主成分とする樹
脂ペーストまたは半田を用いて接着が行われていた。Conventionally, the semiconductor chip 1 is mounted on the ceramic layer 3 by using resin paste or solder containing epoxy or polyimide as a main component.

然し、樹脂ペーストを用いて接着を行う場合に接着層７
の厚さが薄いと、半導体チップ１とセラミック層３との
熱膨張係数の違いにより歪み（ストレス）が生じている
が、この歪みを吸収することができず、接着層７にクラ
ックが生じて接着強度が低下すると云う問題がある。However, when bonding is performed using resin paste, the adhesive layer 7
If the thickness of the adhesive layer 7 is thin, distortion (stress) is generated due to the difference in thermal expansion coefficient between the semiconductor chip 1 and the ceramic layer 3, but this distortion cannot be absorbed and cracks occur in the adhesive layer 7. There is a problem that adhesive strength decreases.

一方、接着層７の厚さを厚くすると、ストレスは充分吸
収できるもの＼、半導体チップ１に傾きが生じたりして
安定した接着強度を得ることができない。On the other hand, if the adhesive layer 7 is made thicker, the stress can be absorbed sufficiently, but the semiconductor chip 1 may become tilted and stable adhesive strength cannot be obtained.

そこで、接着層７の膜厚を一定に保つ方法として接着時
の押圧力を規定したり、−旦圧着した後、所定の高さま
で持ち上げて膜厚を規定したり、また抑え治具に枠体を
設け、規定の厚さより薄くはならないようにするなどの
方法が採られている。Therefore, as a method of keeping the thickness of the adhesive layer 7 constant, it is possible to specify the pressing force during bonding, or to specify the film thickness by lifting it to a predetermined height after crimping. Measures are taken to prevent the thickness from becoming thinner than a specified thickness.

然し、このような方法は接着操作が面倒なわりには接着
層７の厚さを充分にコントロールすることはできなかっ
た。However, although such a method requires a troublesome adhesion operation, it is not possible to sufficiently control the thickness of the adhesive layer 7.

また、セラミック層３を介して接着が行われているため
に、パッケージの厚さが厚くなることが問題であった。Furthermore, since the bonding is performed through the ceramic layer 3, there is a problem in that the package becomes thick.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

以上記したように、半導体チップのパッケージへの装着
はセラミック層を備えた基板上に樹脂ペーストを用いて
行われているが、安定した接着強度を得るには接着層の
厚さを一定に保つ必要がある。As mentioned above, semiconductor chips are attached to packages using resin paste on a substrate with a ceramic layer, but in order to obtain stable adhesive strength, the thickness of the adhesive layer must be kept constant. There is a need.

そこで、簡単な方法で一定の膜厚に保持することが課題
である。Therefore, the challenge is to maintain a constant film thickness using a simple method.

〔課題を解決するための手段〕[Means to solve the problem]

上記の課題は球状の絶縁物よりなり、粒径が５０〜３０
０μｍで大きさの揃った第１のフィラーと、熱伝導率の
優れた絶縁物の粉末よりなり、第１のフィラーに較べて
粒径が格段に小さい第２のフィラーとを主成分とし、こ
のフィラーにバインダ樹脂と溶剤とを添加して混練して
なる接着用ペーストを使用することにより解決すること
ができる。The above problem consists of a spherical insulator with a particle size of 50 to 30
The main components are a first filler with a uniform size of 0 μm and a second filler made of insulating powder with excellent thermal conductivity and whose particle size is much smaller than that of the first filler. This problem can be solved by using an adhesive paste made by adding a binder resin and a solvent to a filler and kneading the mixture.

〔作用〕[Effect]

本発明は接着層の膜厚を一定に保持する方法として、必
要とする膜厚に等しい粒径をもつ球状の第１のフィラー
を接着層中に配置するものである。In the present invention, as a method for keeping the thickness of the adhesive layer constant, a spherical first filler having a particle size equal to the required thickness is arranged in the adhesive layer.

また、接着層は半導体チップの放熱性を高めるために熱
伝導が優れていることが望ましい。Furthermore, it is desirable that the adhesive layer has excellent thermal conductivity in order to improve the heat dissipation of the semiconductor chip.

そこで、本発明は必要とする接着層の厚さに等しい直径
をもつ真球状の第！のフィラー９に合わせて熱伝導率の
優れた材料粉末よりなる第２のフィラ−１０を従来の接
着用ペーストに混合して使用するものである。Therefore, in the present invention, a perfectly spherical ball with a diameter equal to the thickness of the required adhesive layer is used. In addition to the filler 9, a second filler 10 made of powdered material with excellent thermal conductivity is mixed with a conventional adhesive paste.

第１図は本発明に係る接着用ペーストの原理図であって
、基板２とこの上に装着する半導体チップｌとの間の接
着層７は厚さを決める第１のフィラー９と、半導体チッ
プ１に発生した熱を逃がす第２のフィラー１０と、接着
剤として働くバインダ樹脂１１とで構成されている。FIG. 1 is a principle diagram of an adhesive paste according to the present invention, in which an adhesive layer 7 between a substrate 2 and a semiconductor chip l mounted thereon has a first filler 9 that determines the thickness, and a semiconductor chip l. The second filler 10 dissipates the heat generated in the first filler 1, and the binder resin 11 acts as an adhesive.

こ−で、第１のフィラー９の必要条件は、■　球状で一
定の粒径をもつ絶縁物であること、■　安定した接着強
度を得るために５０〜３００μｍの範囲の大きさである
こと、 で、ガラスや耐熱性プラスチックスを用いて作ることが
できる。Therefore, the necessary conditions for the first filler 9 are: (1) It is a spherical insulator with a constant particle size; (2) It has a size in the range of 50 to 300 μm in order to obtain stable adhesive strength; It can be made from glass or heat-resistant plastic.

また、第２のフィラー１０の必要条件は、■　熱伝導率
の優れた絶縁材料粉であること、■　優れた放熱性を示
すためには粉末が相互に重なりあっていること、 ■　粒径は２〜５μｍであること、 で、窒化アルミニウム（ＡＩ！Ｎ）、窒化硼素（ＢＮ）
。In addition, the necessary conditions for the second filler 10 are: ■ It must be an insulating material powder with excellent thermal conductivity; ■ The powder must overlap each other in order to exhibit excellent heat dissipation; ■ The particle size must be Must be 2 to 5 μm, Aluminum nitride (AI!N), Boron nitride (BN)
.

ダイアモンド粉などが該当する。This includes diamond powder, etc.

また、バインダ樹脂としてはエポキシ樹脂、ポリイミド
樹脂など従来接着用として使用されてきた耐熱性樹脂が
適当である。Further, as the binder resin, heat-resistant resins conventionally used for adhesives such as epoxy resins and polyimide resins are suitable.

次に、第１のフィラー９の添加量は基板２と半導体チッ
プ１との間の間隔を決めて半導体チップ１に傾きを生じ
ない程度に少なくてよく、実験した結果、ペーストを第
１のフィラー９の径の厚さに伸ばした場合、第１のフィ
ラーの占める面積は全面積の５％以上、３０％以下あれ
ば充分であることが判った。Next, the amount of the first filler 9 to be added may be small enough to determine the distance between the substrate 2 and the semiconductor chip 1 and prevent the semiconductor chip 1 from tilting. It has been found that when the film is stretched to a thickness of diameter 9, it is sufficient that the area occupied by the first filler is 5% or more and 30% or less of the total area.

次に、第２のフィラー１０は優れた放熱性を保つために
は相互に重なり合うことが必要で、ＢＮのように低比重
（２，３４）のものは４０重量％あればよいが、高比重
の材料を使用する場合でも、導体ペーストを構成する金
属粉の含有量から最高でも８５重量％あれば充分である
。Next, the second filler 10 needs to overlap each other in order to maintain excellent heat dissipation, and 40% by weight is sufficient for fillers with low specific gravity (2,34) like BN, but with high specific gravity Even when using the above material, it is sufficient that the content of the metal powder constituting the conductive paste is at most 85% by weight.

第２図はか−る接着用ペーストを用いたパッケージの断
面図であって、基板２の上に直接に接着層７を形成でき
るので、放熱性がよく、また、第１のフィラー９により
接着層７の厚さを一定に保つことができる。FIG. 2 is a cross-sectional view of a package using such an adhesive paste. Since the adhesive layer 7 can be formed directly on the substrate 2, heat dissipation is good, and the adhesive layer 7 is bonded by the first filler 9. The thickness of layer 7 can be kept constant.

なお、第１のフィラー９の大きさは半導体チップの大き
さに依存するが、５０〜３００μｍである。Note that the size of the first filler 9 depends on the size of the semiconductor chip, but is 50 to 300 μm.

〔実施例〕〔Example〕

第１のフィラーとして粒径か１００μｍのシリカ（Ｓｉ
ｎ、）ガラスを用い、また第２のフィラーとして平均粒
径が１０μｍのＡｆＮ　（比重３．０５）を用いた。Silica (Si) with a particle size of 100 μm is used as the first filler.
n,) glass was used, and AfN (specific gravity 3.05) with an average particle size of 10 μm was used as the second filler.

すなわち、 ＳｉＯ□ガラス（第１のフィラー）　　・・・　６重量
部Ａ１７Ｎ　　（第２のフィラー）　　　　・・・　４
４〃ポリイミド前駆体（バインダ樹脂）・・・　２０＃
Ｎ−メチルピロリドン（溶剤）　　　　・・・　３０＃
を三本ロールミルを用いて混練し、接着用ペーストを作
った。That is, SiO□ glass (first filler)... 6 parts by weight A17N (second filler)... 4
4〃Polyimide precursor (binder resin)... 20#
N-methylpyrrolidone (solvent)...30#
were kneaded using a three-roll mill to make an adhesive paste.

このペーストをＷ−Ｃｕの複合材よりなる基板のチップ
装着位置に塗布し、半導体チップを当接して圧着した後
、２５０℃に加熱して沸点が２０２℃のＮ−メチルピロ
リドンを蒸発させた後、３００　”Ｃで３０分加熱し、
架橋重合させ接着させた。This paste was applied to the chip mounting position of a substrate made of a W-Cu composite material, and the semiconductor chip was pressed against it, and then heated to 250°C to evaporate N-methylpyrrolidone, which has a boiling point of 202°C. , heated at 300"C for 30 minutes,
It was bonded by cross-linking polymerization.

このようにして接着した接着層の厚さは１００μｍであ
り、また半導体チップの傾きは認められなかった。The thickness of the adhesive layer thus bonded was 100 μm, and no tilting of the semiconductor chip was observed.

〔発明の効果〕〔Effect of the invention〕

本発明に係る接着用ペーストの使用により、従来の樹脂
ペーストと同様に使用して半導体チップの傾きがなく、
また接着強度の優れたチップ搭載を行うことができる。By using the adhesive paste according to the present invention, there is no tilting of semiconductor chips when used in the same way as conventional resin pastes.
Furthermore, it is possible to mount a chip with excellent adhesive strength.

なお、この実施例で使用した接着用ペーストは絶縁接続
を必要とする用途に使用するが、導電性を必要とする用
途に使用する場合はＡｆＮ、ＢＮ。Note that the adhesive paste used in this example is used for applications that require insulated connections, but when used for applications that require conductivity, AfN and BN are used.

ダイアモンド粉などの絶縁粉末に換えて、銀（Ａｇ）や
金（Ａｕ）などの金属粉末を用いれば、厚さが均一な導
電層をもつ接着を行うことができる。If metal powder such as silver (Ag) or gold (Au) is used instead of insulating powder such as diamond powder, it is possible to bond with a conductive layer having a uniform thickness.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明に係る接着用ペーストの原理図、第２図
は本発明に係る接着用ペーストを用いたパッケージの断
面図、 第３図は従来の半導体パッケージの断面図、である。 図において、 ■は半導体チップ、　　　　２は基板、３はセラミック
層、　　　　６は蓋、 ７は接着層、　　　　　　　９は第１のフィラーｌＯは
第２のフィラー　　　１１はバインダ樹脂、である。 本発明に係る接着用ペーストの原理９ 第　１　図 第 凶 従来の半導体パッケージの助゛面図 晃 凶FIG. 1 is a principle diagram of an adhesive paste according to the present invention, FIG. 2 is a cross-sectional view of a package using the adhesive paste according to the present invention, and FIG. 3 is a cross-sectional view of a conventional semiconductor package. In the figure, 2 is a semiconductor chip, 2 is a substrate, 3 is a ceramic layer, 6 is a lid, 7 is an adhesive layer, 9 is a first filler IO is a second filler, and 11 is a binder resin. Principle 9 of the adhesive paste according to the present invention FIG. 1 A front view of a conventional semiconductor package

Claims (2)

【特許請求の範囲】[Claims] （１）半導体パッケージを構成する金属板上に半導体チ
ップを搭載するのに使用する接着ペーストが、 球状の絶縁物からなる、大きさの揃った第１のフィラー
と、熱伝導率の優れた絶縁物の粉末よりなり、該第１の
フィラーに較べて粒径が格段に小さい第２のフィラーと
を主成分とし、該フィラーにバインダ樹脂と溶剤とを添
加して混練してなることを特徴とする接着用ペースト。(1) The adhesive paste used to mount the semiconductor chip on the metal plate that makes up the semiconductor package consists of a first filler of uniform size made of a spherical insulator and an insulator with excellent thermal conductivity. The main component is a second filler, which is made of a powder of a substance, and whose particle size is much smaller than that of the first filler, and the filler is kneaded with a binder resin and a solvent. Adhesive paste. （２）請求項１記載の第１のフィラーの粒径が５０〜３
００μｍであることを特徴とする接着用ペースト。(2) The first filler according to claim 1 has a particle size of 50 to 3.
An adhesive paste characterized by having a diameter of 00 μm.
JP27822090A 1990-10-17 1990-10-17 Paste for adhesion use Pending JPH04152642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27822090A JPH04152642A (en) 1990-10-17 1990-10-17 Paste for adhesion use

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27822090A JPH04152642A (en) 1990-10-17 1990-10-17 Paste for adhesion use

Publications (1)

Publication Number Publication Date
JPH04152642A true JPH04152642A (en) 1992-05-26

Family

ID=17594286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27822090A Pending JPH04152642A (en) 1990-10-17 1990-10-17 Paste for adhesion use

Country Status (1)

Country Link
JP (1) JPH04152642A (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0714859A (en) * 1993-06-21 1995-01-17 Nec Corp Die-bonding resin for semiconductor chip and semiconductor device using the same
JP2001019928A (en) * 1999-07-08 2001-01-23 Dow Corning Toray Silicone Co Ltd Adhesive and semiconductor apparatus
JP2001196394A (en) * 2000-01-14 2001-07-19 Denso Corp Semiconductor device
US6489668B1 (en) 1997-03-24 2002-12-03 Seiko Epson Corporation Semiconductor device and method for manufacturing the same
JP2003021732A (en) * 2001-07-05 2003-01-24 Hamamatsu Photonics Kk Image pick-up device
WO2003025081A1 (en) * 2001-09-17 2003-03-27 Dow Corning Corporation Die attached adhesives for semiconductor devices, an efficient process for producing such devices and the devices per se produced by the efficient processes
WO2003025080A1 (en) * 2001-09-17 2003-03-27 Dow Corning Corporation Die attach adhesives for semiconductor applications, processes for producing semiconductor devices and semiconductor devices produced by such processes
JP2004031495A (en) * 2002-06-24 2004-01-29 Denso Corp Heat radiation structure for electronic equipment
JP2007245670A (en) * 2006-03-17 2007-09-27 Sony Corp Thermal head and printer device
CN100361301C (en) * 2002-06-28 2008-01-09 矽品精密工业股份有限公司 Multi-chip semiconductor package and mfg. method thereof
EP2083949A1 (en) * 2006-11-21 2009-08-05 Gyros Patent AB Method of bonding a micrifluidic device and a microfluidic device
US7843476B2 (en) 2006-03-17 2010-11-30 Sony Corporation Thermal head and printer
CN102195157A (en) * 2010-03-18 2011-09-21 Smk株式会社 Connector
JP2014149192A (en) * 2013-01-31 2014-08-21 Denso Corp Physical quantity sensor
CN108534922A (en) * 2017-03-06 2018-09-14 精工爱普生株式会社 Sensor component, force checking device and robot

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0714859A (en) * 1993-06-21 1995-01-17 Nec Corp Die-bonding resin for semiconductor chip and semiconductor device using the same
JP2605970B2 (en) * 1993-06-21 1997-04-30 日本電気株式会社 Die bonding resin for semiconductor chip and semiconductor device using the same.
US6489668B1 (en) 1997-03-24 2002-12-03 Seiko Epson Corporation Semiconductor device and method for manufacturing the same
JP2001019928A (en) * 1999-07-08 2001-01-23 Dow Corning Toray Silicone Co Ltd Adhesive and semiconductor apparatus
JP2001196394A (en) * 2000-01-14 2001-07-19 Denso Corp Semiconductor device
JP2003021732A (en) * 2001-07-05 2003-01-24 Hamamatsu Photonics Kk Image pick-up device
WO2003025081A1 (en) * 2001-09-17 2003-03-27 Dow Corning Corporation Die attached adhesives for semiconductor devices, an efficient process for producing such devices and the devices per se produced by the efficient processes
WO2003025080A1 (en) * 2001-09-17 2003-03-27 Dow Corning Corporation Die attach adhesives for semiconductor applications, processes for producing semiconductor devices and semiconductor devices produced by such processes
US6784555B2 (en) 2001-09-17 2004-08-31 Dow Corning Corporation Die attach adhesives for semiconductor applications utilizing a polymeric base material with inorganic insulator particles of various sizes
JP2005503468A (en) * 2001-09-17 2005-02-03 ダウ・コ−ニング・コ−ポレ−ション Die attach adhesives for semiconductor devices, efficient methods of manufacturing such devices, and devices manufactured by this method
JP2005503467A (en) * 2001-09-17 2005-02-03 ダウ・コ−ニング・コ−ポレ−ション Die attach adhesives for semiconductor applications, methods of manufacturing semiconductor devices, and semiconductor devices manufactured by such methods
JP2011157559A (en) * 2001-09-17 2011-08-18 Dow Corning Corp Die attach adhesive for semiconductor application, method for producing semiconductor device, and semiconductor device produced by the same
DE10297224B4 (en) * 2001-09-17 2008-06-19 Dow Corning Corp., Midland Wafer attachment adhesives for semiconductor applications, methods of bonding substrates, and use of such an adhesive to bond and bond substrates of a semiconductor device
KR100880091B1 (en) * 2001-09-17 2009-01-23 다우 코닝 코포레이션 Die attached adhesives for semiconductor devices, an efficient process for producing such devices and the devices per se produced by the efficient processes
JP2004031495A (en) * 2002-06-24 2004-01-29 Denso Corp Heat radiation structure for electronic equipment
CN100361301C (en) * 2002-06-28 2008-01-09 矽品精密工业股份有限公司 Multi-chip semiconductor package and mfg. method thereof
JP2007245670A (en) * 2006-03-17 2007-09-27 Sony Corp Thermal head and printer device
JP4506696B2 (en) * 2006-03-17 2010-07-21 ソニー株式会社 Thermal head and printer device
US7843476B2 (en) 2006-03-17 2010-11-30 Sony Corporation Thermal head and printer
EP2083949A4 (en) * 2006-11-21 2010-07-28 Gyros Patent Ab Method of bonding a micrifluidic device and a microfluidic device
EP2083949A1 (en) * 2006-11-21 2009-08-05 Gyros Patent AB Method of bonding a micrifluidic device and a microfluidic device
CN102195157A (en) * 2010-03-18 2011-09-21 Smk株式会社 Connector
JP2011198542A (en) * 2010-03-18 2011-10-06 Smk Corp Connector
JP2014149192A (en) * 2013-01-31 2014-08-21 Denso Corp Physical quantity sensor
CN108534922A (en) * 2017-03-06 2018-09-14 精工爱普生株式会社 Sensor component, force checking device and robot

Similar Documents

Publication Publication Date Title
US5550408A (en) Semiconductor device
US5436503A (en) Semiconductor device and method of manufacturing the same
US4436785A (en) Silver-filled glass
JPH04152642A (en) Paste for adhesion use
JPH11150135A (en) Conductive paste of superior thermal conductivity and electronic device
JPH04162756A (en) Semiconductor module
JP3336240B2 (en) Semiconductor element mounting board
US5164885A (en) Electronic package having a non-oxide ceramic bonded to metal and method for making
JP2002231850A (en) Semiconductor device storing wiring board
JPH06132425A (en) Semiconductor device
GB2103250A (en) Silver-filled glass
JPH10275522A (en) Conductive resin paste, package board using it, and semi-conductor package
JP2517024B2 (en) Ceramic package and its manufacturing method
JP3426827B2 (en) Semiconductor device
JP2012064616A (en) Storage package for high heat radiation type electronic component
JP2828553B2 (en) Semiconductor device
JPH10284643A (en) Substrate for semiconductor device
JP2000183253A (en) Package for housing semiconductor element
JP3471595B2 (en) Bare IC mounting method and sealing material
JPH10275878A (en) Semiconductor package
JPH0568801B2 (en)
JPH0997865A (en) Radiation part
JP2001210769A (en) Semiconductor device
JPH10275879A (en) Semiconductor package
JPH0536864A (en) Semiconductor element package