CN1452241A - 具有连接到导线的焊盘电极的半导体器件 - Google Patents
具有连接到导线的焊盘电极的半导体器件 Download PDFInfo
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- CN1452241A CN1452241A CN03110161A CN03110161A CN1452241A CN 1452241 A CN1452241 A CN 1452241A CN 03110161 A CN03110161 A CN 03110161A CN 03110161 A CN03110161 A CN 03110161A CN 1452241 A CN1452241 A CN 1452241A
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- semiconductor device
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- H01L2924/20752—Diameter ranges larger or equal to 20 microns less than 30 microns
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
本发明涉及具有半导体基片和在其上形成并被电连接到导线的焊盘电极的半导体器件。在具有半导体基片的半导体器件中,内部电极层形成在半导体基片上。阻挡金属层形成在内部电极上。外部电极层形成在阻挡金属层上。焊盘电极由内部电极层,阻挡金属层和外部电极层构成。导线被电连接到焊盘电极。外部电极层的面积被设置在处于焊盘电极上的导线的聚合部分的面积和阻挡金属层的平面面积之间的中间。
Description
本申请要求在先申请的JP2002-110874的优先权,在此结合参考其公开的内容。
技术领域
本发明广泛涉及具有半导体基片和在其上形成并被电连接到导线的焊盘电极(Pad electrode)的半导体器件。特别的,本发明涉及一种半导体器件,它在焊盘电极和导线之间具有改进的电连接。
背景技术
通过在半导体晶片上被划分的预定的面积中形成每个半导体元件来制造半导体器件,电气的把每个半导体元件的基本部分与在每个面积的表面上形成的焊盘电极相连接,并把半导体晶片切成单独的各个半导体片状器件。使用半导体片状器件,半导体元件和外部器件经焊盘电极能被电连接。在半导体器件中,在具有用树脂涂半导体片状器件以防止外部压力或腐蚀气体的半导体器件中,焊盘电极通常经导线与暴露在涂层的树脂的外表面上的外部电极相连接。
在这种类型的半导体器件中,作为主要部件的铝或包含铝的合金通常被当作用于焊盘电极的材料,以便电阻的连接焊盘电极到半导体元件。诸如金、铜或铝之类的高电传导性的金属或合金被用作导线。通过主要考虑电气特性来确定导线的材料和直径,比如工作电流,成本和可靠性。如果要求较低的电阻和可靠性,通常使用金。
现在,参考图1,将作出有关半导体器件的描述。
在图1中,参考数字1表示在其上形成半导体元件的半导体基片。通过在硅元素或化合物半导体中扩散杂质,半导体元件包括有源器件,比如晶体管,和无源器件,比如电阻器或电容器。尽管未示出,但在半导体基片1的表面上形成了布线层。在基片1上,形成了保护薄膜2。保护薄膜2保护性的覆盖包括布线层的半导体基片1的表面。焊盘电极3电连接到半导体基片1中的半导体元件。焊盘电极3由阻挡金属层5和外部电极层6组成,它们以这样的顺序被淀积在被电连接到布线层(未示出)的内部电极层4上。参考数字7表示外部连接到焊盘电极3的导线。
通过制造圆形开口来形成内部电极层4,其在覆盖半导体基片1的保护薄膜2的部分中具有(例如)100μm的直径,以便暴露具有(例如)几微米厚度的铝-铜合金层。阻挡金属层5具有多层结构,其中多层通常由金属组成,比如钛或钛镍,或具有阻挡特性的合金,其被沉积到预定的厚度。在阻挡金属层5的顶部,由铝和铜的合金组成的层被沉积以形成外部电极层6。
通过熔化从金属导线底部伸出的末端部分来形成导线7,该金属导线经电子放电被插入毛细管(未示出)中,借此形成一个球。将球施压于毛细管底部上的焊盘电极以挤压该球。挤压的部分7a的直径被增加到导线直径的几倍大小,借此增加接合区,从而确保电连接。通过最大可允许的半导体器件的电流来确定导线7的直径,并且基于导线直径确定挤压部分7a的直径。
同时,焊盘电极3的直径被设置到大于挤压部分7a的直径,以便允许容易地进行布线焊接。这就使得易于把导线7连接到焊盘电极3,即使半导体片状器件是错位的。
通常通过热压焊接、超声波焊接或结合前者的两个的其他的连接方法来连接焊盘电极和导线7。因此,连接接口的温度被设置在连接的最佳的温度上。
另一方面,大家都知道,如果铝被用作外部电极层6和金被用作导线7,并且如果整个或在连接处理过程之后连接接口受到高温,则产生金和铝的金属间的化合物。还知道的是,金属间的化合物的类型和产生率根据连接接口的温度而变化。
紫色合金(AuAI2)通常称作紫斑。如果金的量大于紫斑的量,则产生白色合金(Au2AI)。这种合金展现较高的电阻和易碎性,导致机械强度的恶化,这意味着连接强度的恶化。而且,产生的金属间化合物被直接连接在导线和半导体元件之间,以至于它严重的影响了半导体器件的电阻值。这就引起一个问题,在电极上增加了ON(导通)电阻,对该电极提供了主电流,以及在一个电极上增加了DC输入电阻,对该电极提供了输入信号。
为了解决上述问题,日本未审专利公开号(JP-A)No.4-10632(现有技术)已经公开了一种方法,其中在导线焊接到半导体片器件的焊盘电极之后,在它进行树脂密封步骤之前半导体片状器件被保持在高温上。更特别的是,如果半导体片状器件被保持在大约200℃上持续大约两个小时,大约80%或更多的合金能被产生为完成的产品以便获得稳定的半导体器件。此外,还公开了在200℃上加热半导体片状器件持续200小时,不利的是这使得铝和金的金属间的化合物易碎。
按照上述的现有技术,导线被连接到焊盘电极,并接着,焊盘电极和导线在预定的温度上被加热预定的时间,以促进铝和金的金属间化合物的生成,从而稳定半导体器件的特性。然而,按照该现有技术,金属间化合物的产生不能被完全地完成,而延长的加热时间会引起连接接口易碎。
当半导体器件被反复的打开ON和关闭OFF,它的温度反复的上升和下降。作为结果,焊盘电极和导线的接合部反复地受到由于热膨胀的膨胀和收缩的应力。在接合部的电阻中的增加引起接合部本身发热,进一步表现为易于破碎。在相当短的时间周期中,这导致导线的受损坏的电连接。
在半导体器件操作在超高频的情况下,在频段范围从几百MHz-GHz中,在半导体器件和连接到它的电路之间执行阻抗匹配以便最大化功率效率。半导体器件中的导线构成匹配电路的一部分。
如果焊盘电极和导线之间的电阻随时间改变,匹配条件也随时间改变从而增加损耗。这需要再调整外部电路以恢复最佳条件。为此,焊盘电极和导线之间的接合部的稳定性就成为了重要的因素。
发明内容
因此,本发明的目的是提供一种高可靠的半导体器件,它能够工作很长的时间周期而不会产生在导线和焊盘电极间的电阻随时间的波动(改变)。
在按照本发明的一个方面的半导体器件中,内部电极层形成在半导体基片上。阻挡金属层形成在内部电极上。外部电极层形成在阻挡金属层上。焊盘电极由内部电极层,阻挡金属层,和外部电极层组成。导线被电连接到焊盘电极。外部电极层的面积被设置在焊盘电极上的导线的聚合部分的面积和阻挡金属层的平面面积之间的中间。
优选地的,外部电极层由铝形成,或由包含作为主要成分的铝的合金形成,并且导线由金形成,或由包含作为主要成分的金的合金形成。
优选地的,焊盘电极的外部电极层的面积大小被设置到导线的聚合部分的1.2-10倍。
优选地的,半导体基片包括超高频电路器件。导线构成超高频电路器件的一部分。
优选地的,把外部电极层做成阻挡金属层上的岛屿形状,并设置焊盘电极的外部电极层的面积大小,以便抑制导线和焊盘电极间的电阻随时间发生波动(改变)。
附图说明
图1是现有半导体器件的主要部分的放大的侧部断面图;和
图2是按照本发明的实施例的半导体器件的主要部分的放大的侧部断面图。
具体实施方式
在按照本发明的半导体器件中,焊盘电极的外部电极层的面积大小由内部电极层、阻挡金属层和外部电极层确定,它们以这样的顺序被沉淀,被设置为焊盘电极上的导线的聚合部分的面积大小和阻挡金属层的平面面积的大小之间的中间。这种安排被理想地用于半导体器件,其中由金或由包含金作为主要成分的合金形成的导线被连接到配备了外部电极层的焊盘电极,该外部电极层由铝或由包含铝作为主要成分的合金形成。这里注意的是,按照本发明的半导体器件的焊盘电极的外部电极层的面积最好可以被设置为导线的聚合部分的面积的1.2-2倍。
按照本发明的半导体器件可以包括超高频半导体元件,并可以适用于半导体器件,其中导线构成超高频电路元件的一部分。
现在,参考图2,将详细解释本发明的实施例。在图2中,图1中相同的部件将被分配相同的参考数字,并不再重复相同的描述。
参考图2,焊盘电极8形成在包括半导体元件(未示出)的半导体基片1的表面上。焊盘电极8由内部电极层4、阻挡金属层5和外部电极层9构成,其中内部电极层4由包含铜的铝合金形成,并具有几微米的厚度,外部电极层9由包含铜的铝合金形成。阻挡金属层5由金属层的多层叠片或由展现阻挡特性的钛或者氮化钛的合金层构成。由金形成的导线7连接在外部的电极层9上。
按照本发明的半导体器件不同于图1所示的有关的半导体器件之处在于,其中外部电极层9的平面面积的大小被设置在焊盘电极8的导线7的聚合部分的面积大小和阻挡金属层5的平面面积的大小之间的中间。通过以此方式设置外部电极层9的平面面积,外部电极层9被设置在阻挡金属层5上的岛屿形状中。
按照本发明,将半导体器件在树脂铸模步骤和跟随导线焊接步骤的树脂固化步骤中加热并保持在高温上,直到装运成完全的产品。在整个加热步骤期间,金从导线7被扩散到外部电极层9中,同时铝从外部电极层9被扩散到在导线7和焊盘电极8之间的接合接口的导线7中。因此,产生金属间的化合物。
在此情况下,外部电极层9的面积小于图1所示的有关的半导体器件的外部电极层的面积,以至于扩散到铝中的金快速的达到平衡状态,完成相互的扩散。这样,没有产生附加的金属间化合物。以此方式结束的金属间化合物的产生最小化了导线和焊盘电极间的电阻中的时间相关波动。因此,稳定性被提高。
具有100μm直径和0.35μm厚度的外部电极层9形成在具有130μm直径的圆形阻挡金属层5上。具有直径0.25μm(膨胀部分的直径大约是80μm)的导线7被连接到焊盘电极8。导线电阻的初始值是0.12Ω。这种装配被放在250℃的空气中持续2000小时,以检查导线电阻值中的时间相关波动。在2000小时过去之后,初始值保持不变,表明特别的高稳定性。
如同在典型的半导体器件中一样,按照本发明的导线7的接合部分和半导体器件的焊盘电极8在边缘试验处理等中也被加热。然而,在接合部分上的电阻仍然保持稳定直到器件达到电气检查步骤为止。因此,不需要特殊的加热步骤,以致于能够容易地完成半导体器件的生产。
形成的外部电极层9具有0.35μm厚度和具有100μm直径的圆形。导线7的膨胀部分(聚合部分)7a被设置到70-90μm,并且外部电极层9的面积对聚合部分的面积的比率在1.2-10的范围内变化,以便测量导线电阻中的时间相关波动。测量结果表明由于初始值造成的波动被抑制。
如果前述的面积比率被设置到大于10,就是说,如果外部电极层9的面积被增加或导线的聚合部分7a被减少,相对于导线7来说,外部电极的容量变得相对较大。这就引起金从导线7扩散到外部电极层9持续很长的时间,导致导线电阻中的时间相关波动。
相反,如果面积比率被设置到小于1.2,就是说,如果外部电极层9的直径被减小或导线聚合部分7a的面积被增加,相对于导线7来说,外部电极层9的容量相对被减少。这是所期望的能防止导线电阻中的时间相关波动,因为从导线7提供的金的浓度快速地达到饱和点。然而,不利的是,需要高精度的导线焊接,并且如果焊接位置不准确,焊盘电极可能会受到损坏。为此,适当的面积比率范围是1.2-10。
在按照本发明的半导体器件中,在导线7和焊盘电极8之间的接合部分上不出现电阻中的时间相关波动。因此,即使提供了主电流,在接合部分上电压不会下降,导致没有功率损失。因此,该半导体器件适于作为功率半导体器件。
而且,当在几百兆赫兹到吉赫兹的超高频上工作时,按照本发明的半导体器件能够长时间周期的保持与连接到它的电路的匹配。因此,包括再调整的维护操作是不需要的。
因此,按照本发明,能够实现高可靠性的半导体器件而不会产生导线和电极间的电阻的时间相关波动,从而允许持续长时间的稳定的工作。
尽管已经结合几个实施例全面地公开了本发明,但对于本领域技术人员来说,完全可以容易的对本发明以各种其它的方式进行实施。
Claims (8)
1.一种具有半导体基片的半导体器件,包括:
内部电极层,它形成在半导体基片上,
阻挡金属层,它形成在内部电极上,
外部电极层,它形成在阻挡金属层上,焊盘电极,其由内部电极层、阻挡金属层和外部电极层构成,以及
导线,其被电连接到焊盘电极,
其中外部电极层的面积被设置在处于焊盘电极上的导线的聚合部分的一个面积和阻挡金属层的平面面积之间的中间。
2.按照权利要求1所述的半导体器件,其中:
所述外部电极层由铝或包含铝作为主要成分的合金组成。
3.按照权利要求2所述的半导体器件,其中:
所述导线由金或包含金作为主要成分的合金组成。
4.按照权利要求1所述的半导体器件,其中:
所述外部电极层的面积被设置为导线的聚合部分的1.2-10倍。
5.按照权利要求1所述的半导体器件,其中:
所述半导体基片包括超高频电路器件。
6.按照权利要求5所述的半导体器件,其中
所述导线构成超高频电路器件的一部分。
7.按照权利要求1所述的半导体器件,其中:
将所述外部电极层在阻挡金属层上形成岛屿的形状。
8.按照权利要求1所述的半导体器件,其中:
设置焊盘电极的外部电极层的面积大小以便抑制导线和焊盘电极间的电阻中的时间相关波动。
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JP2593965B2 (ja) * | 1991-01-29 | 1997-03-26 | 三菱電機株式会社 | 半導体装置 |
JPH0555296A (ja) | 1991-08-26 | 1993-03-05 | Clarion Co Ltd | 半導体装置 |
JPH06196526A (ja) | 1992-12-25 | 1994-07-15 | Toyota Motor Corp | 半導体装置の製造方法 |
GB2307103B (en) * | 1993-06-25 | 1997-09-17 | Mitsubishi Electric Corp | Electrode connections for semiconductor devices |
JP3906522B2 (ja) * | 1997-06-10 | 2007-04-18 | ソニー株式会社 | 半導体装置の製造方法 |
JP4564113B2 (ja) * | 1998-11-30 | 2010-10-20 | 株式会社東芝 | 微粒子膜形成方法 |
JP2002076051A (ja) | 2000-09-01 | 2002-03-15 | Nec Corp | 半導体装置のボンディングパッド構造及びボンディング方法 |
-
2002
- 2002-04-12 JP JP2002110874A patent/JP2003303848A/ja active Pending
-
2003
- 2003-04-11 KR KR10-2003-0023125A patent/KR20030081178A/ko not_active Application Discontinuation
- 2003-04-11 US US10/411,109 patent/US6784545B2/en not_active Expired - Fee Related
- 2003-04-11 TW TW092108490A patent/TWI229932B/zh not_active IP Right Cessation
- 2003-04-11 EP EP03008028A patent/EP1353377A3/en not_active Withdrawn
- 2003-04-14 CN CN03110161A patent/CN1452241A/zh active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100399559C (zh) * | 2006-02-16 | 2008-07-02 | 上海交通大学 | 微电极防短路隔离胶结构 |
Also Published As
Publication number | Publication date |
---|---|
TWI229932B (en) | 2005-03-21 |
TW200402136A (en) | 2004-02-01 |
JP2003303848A (ja) | 2003-10-24 |
KR20030081178A (ko) | 2003-10-17 |
EP1353377A2 (en) | 2003-10-15 |
US20030214033A1 (en) | 2003-11-20 |
US6784545B2 (en) | 2004-08-31 |
EP1353377A3 (en) | 2005-07-20 |
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