CN1452234A - Double inlaying method for barriering gas release and generating projective structure - Google Patents
Double inlaying method for barriering gas release and generating projective structure Download PDFInfo
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- CN1452234A CN1452234A CN 02105710 CN02105710A CN1452234A CN 1452234 A CN1452234 A CN 1452234A CN 02105710 CN02105710 CN 02105710 CN 02105710 A CN02105710 A CN 02105710A CN 1452234 A CN1452234 A CN 1452234A
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Abstract
A dual-inlay process for preventing gas release and removing boss structure includes etching on anti-reflection layer, the second low dielectric constant layer, the second etch stop layer, and the first low dielectric constant layer to form a channel in them; depositing a barrier layer; defining a photoresist pattern as mask; etching on barrier layer, antireflection layer and the second dielectric constant layer to form a window; dry etching to remove the surface barrier layer and the first etch stop layer on the bottom of channel; depositing a barrier layer in channel and on window surface; generating an electric conducting layer; and chemicomechanical grinding.
Description
Technical field
The present invention system is about the formation method of a kind of dual-damascene structure or interlayer hole, particularly produce and prevent the method that sidewall surfaces is coarse about a kind of gas that prevents, utilization forms the barrier layer of layer of metal in the two side walls of porous material irrigation canals and ditches, makes matsurface in the two side walls of irrigation canals and ditches be improved and eliminates bulge-structure.
Background technology
Along with the quick evolution of semiconductor technology, dwindling component size becomes a kind of trend.Therefore, semiconductor technology constantly increases the aggregation density of integrated circuit in the wafer.Element manufactured very closely on the semiconductor with within.Because continuing to increase of encapsulation, the process technique of aligning, little shadow becomes more important.Many elements comprise transmission line or structure in order to carry out specific function, show according to test, after the processing procedure of integrated circuit entered the technical field of 0.18 micron even 0.13 micron, the key factor that influences the element operation rate had been converted to resistance-capacitance sluggishness (RC delay) effect of metal interconnecting (Meta1interconnection) from the width of gate.Because of resistance and its sectional area of lead is inversely proportional to, along with the raising of the aggregation density of integrated circuit, the live width and the thickness of metal interconnecting all dwindle thereupon, thereby cause the coupling capacitor between the lead to raise.Therefore after the processing procedure of integrated circuit entered the field of deep-sub-micrometer, the resistance-capacitance sluggishness of metal interconnecting significantly improved, and also therefore influenced the arithmetic speed and the access rate of integrated circuit.In order to improve the aggregation density of integrated circuit, under the condition that live width and line-spacing all should not improve, the material of changing metal interconnecting and interlayer dielectric layer is best selection.Aspect metal interconnecting, metal material changes the copper metal into by original aluminium silicon copper alloy or aluminium copper, except having low-resistance characteristic, have more good anti-electron transfer and good anti-stress, except the operation rate that can improve element, reliability that simultaneously can lift elements.On the other hand, interlayer dielectric layer then must select the material of low-k (Dielectric Constant) to replace original silicon, to reduce the coupling capacitor between the metal interconnecting.The dielectric constant of silicon is about 3.9, therefore must choose dielectric constant less than 3.9 dielectric medium as interlayer dielectric layer, can reach the effect that reduces the resistance-capacitance sluggishness, for example: the silicon (SiOF) that fluorine mixes, organic spin-coating glass (HSQ) or the like.
After the processing procedure of integrated circuit entered 0.1 micron technical field, the low-k material of porous material (dielectric constant is between between 2.0～2.5) was applied among the copper wiring.In the processing procedure of integrated circuit, be favourable less than 2.5 porous material (porous) for the integration of integrated circuit manufacture process with low-k (K).Only, the dielectric material that present processing procedure is commonly used is easy to generate matsurface in the trench sidewall surface of dual-damascene structure, and disengages gas in follow-up heat treatment process.The above-mentioned gas that overflows will cause the structure of convex shape or claim in the irrigation canals and ditches that mushroom-shaped structure (mushroom) is formed at dual damascene (consulting Fig. 1), and be unfavorable for follow-up processing procedure.Cause the main cause of gas ejection may be NH
3Cause in the evaporation of Celsius temperature 100-400 degree.The matsurface that also produces in the two side of irrigation canals and ditches also is unfavorable for the covering of subsequent film.
Summary of the invention
Because the shortcoming of above-mentioned prior art, purpose of the present invention is that a kind of dual-damascene method is provided, utilization forms the side wall surface of a barrier layer at porous material irrigation canals and ditches with chemistry or physical vaporous deposition, to improve the irrigation canals and ditches roughness and to eliminate above-mentioned convex shape structure.
A kind of dual-damascene method that blocks gas release and projective structure generation of the present invention comprises:
Form first etching stopping layer on wafer;
Form first dielectric layer on this first etching stopping layer;
Form second etching stopping layer on this first dielectric layer;
Form second dielectric layer on this second etching stopping layer;
Form anti-reflecting layer on this second dielectric layer;
Form irrigation canals and ditches among above-mentioned anti-reflecting layer, second dielectric layer, second etching stopping layer and first dielectric layer;
Form a metal barrier layer on the surface and this anti-reflecting layer of above-mentioned irrigation canals and ditches;
Forming one is opened among this metal barrier layer, this anti-reflecting layer, second dielectric layer;
With this metal barrier layer of anisotropic etching processing procedure etching, make it residue in the surface of these irrigation canals and ditches;
Form metal material and be beneficial to make dual damascene in these irrigation canals and ditches, opening in above-mentioned second etching stopping layer and backfill; And grind this metal material to form dual-damascene structure.
Said method is anti-reflecting layer, second dielectric layer with low dielectric constant, second etching stopping layer, first dielectric layer with low dielectric constant to be etched with form irrigation canals and ditches among above-mentioned rete.Afterwards, deposit a barrier layer on the surface and anti-reflecting layer of irrigation canals and ditches.The material of barrier layer can adopt metallic diaphragm to adopt chemical vapour deposition technique to make, and material can be selected Ta, TaN, TiN, WN, TiSiN for use.Define a photoresistance pattern in the barrier layer upper surface, it has the opening of broad.Re-using the photoresistance pattern is etch mask, and barrier layer, anti-reflecting layer, second dielectric layer with low dielectric constant are carried out etching, till arriving at second etching stopping layer to form an opening.With the barrier layer on the dry ecthing removal horizontal surface, residual rete is positioned at the sidewall surfaces of irrigation canals and ditches afterwards.Above-mentioned steps is removed first etching stopping layer that is positioned at the irrigation canals and ditches bottom in the lump.One barrier layer is deposited on the surface of irrigation canals and ditches and opening in advance, the conductive layer that continues then be formed on the barrier layer and backfill in opening and irrigation canals and ditches.This conductive layer part is removed to reach planarization by cmp, finishes dual-damascene structure.
Description of drawings
Fig. 1 produces the electron micrograph of mushroom-shaped structure for prior art.
Fig. 2 forms the generalized section that anti-reflecting layer, second dielectric layer with low dielectric constant, second etching stopping layer, first dielectric layer with low dielectric constant, first dielectric layer with low dielectric constant pile up rete for the present invention.
Fig. 3 piles up in the rete in Fig. 2 for the present invention forms irrigation canals and ditches, and forms metal barrier layer in the generalized section on irrigation canals and ditches surface.
Fig. 4 forms the generalized section of opening for the present invention.
Fig. 5 carries out the generalized section of etching step for the present invention.
Fig. 6 forms generalized section after the metal double-insert structure for the present invention.
Fig. 7 is the electron micrograph according to dual-damascene structure of the present invention, wherein eliminates mushroom-shaped structure.
Embodiment
The present invention discloses a kind of method that prevents to produce matsurface and convex shape (mushroom) structure on low-k material irrigation canals and ditches surface.Method of the present invention can be used in makes interlayer hole or dual-damascene structure.Referring to Fig. 2, a substrate 2 at first is provided, this substrate 2 can be silicon, GaAs and germanium etc.For example, use a crystal orientation＜100〉monocrystalline silicon substrate.Has one or more semiconductor element among this substrate.Yet this is non-to be theme of the present invention, and element or its function and the present invention there is no too big connection, so untired stating.It is formed thereon that above-mentioned wafer or substrate 2 comprise an insulating barrier 4, and a bottom conductive structure 6 is formed among the above-mentioned insulating barrier 4.Deposit first etching stopping layer 8, first dielectric layer with low dielectric constant 10, second etching stopping layer 12, second dielectric layer with low dielectric constant 14 and anti-reflecting layer 16 in regular turn.For an embodiment, anti-reflecting layer 16 can adopt nitrogen oxidation silicon material (oxynitride), and etching stopping layer 8,12 can use silicon nitride (SiN), nitrogen carbonization silicon (SiCN), carbonization silicon (SiC), nitrogen oxidation of coal silicon materials such as (SiOCN).
Then see also Fig. 3, by traditional micro-photographing process, utilize photoresistance to be etch mask, with anti-reflecting layer 16, second dielectric layer with low dielectric constant 14, second etching stopping layer 12,10 etchings of first dielectric layer with low dielectric constant, to form irrigation canals and ditches 18 among above-mentioned rete, remove photoresistance again, as shown in Figure 3.Afterwards, deposit a barrier layer 20 on the surface and anti-reflecting layer 16 of irrigation canals and ditches 18.The material of barrier layer 20 can adopt metallic diaphragm to adopt chemical vapour deposition technique to make, and material can be selected Ta, TaN, TiN, WN, TiSiN for use.This step can be protected the sidewall and the level and smooth coarse sidewall surfaces of irrigation canals and ditches 18.The metal material that chemistry or physical vaporous deposition form has preferable ladder compared to oxide and covers (step coverage), and can utilize metal level to keep the critical dimension of interlayer hole.And generally use oxide also to cause the variation of critical dimension.For example the thickness of oxide layer when sidewall reaches more than 120 dusts, just can block the generation of gas release or projective structure.Utilize mode of the present invention can reduce to below 80 dusts.
Redefine a photoresistance pattern 22 again in barrier layer 20 upper surfaces, it has the opening of broad.Re-use photoresistance pattern 22 and be etch mask, barrier layer 20, anti-reflecting layer 16, second dielectric layer with low dielectric constant 14 are carried out etching, till arriving at second etching stopping layer 12, so, transferable irrigation canals and ditches pattern 24 is to rete.Then, remove photoresistance pattern 22, as shown in Figure 4.
With the barrier layer 20 on the dry ecthing removal horizontal surface, residual rete is positioned at the sidewall surfaces of irrigation canals and ditches 18, as shown in Figure 5 afterwards.Above-mentioned steps remove in the lump be positioned at irrigation canals and ditches 18 bottoms first etching stopping layer 8 to expose underlying metal 6.Consult Fig. 6, a barrier layer 26 can be deposited on the surface of irrigation canals and ditches 18 and opening 24 in advance, the electric conducting material 28 that continues then be formed on the barrier layer 26 and backfill in opening 24 and irrigation canals and ditches 18.These electric conducting material 28 parts are removed to reach planarization by cmp, finish dual-damascene structure.Above-mentioned electric conducting material 28 can use copper material to make.Advantage of the present invention can prevent the formation of disengaging of gas and projective structure, can prevent the trench sidewall rough surface, consults Fig. 7.In other words, the present invention deposits a metal barrier layer with chemistry or physical vaporous deposition, to cover the porous material wall of dielectric medium, the oxide that the more electric oar of the effect that its ladder covers strengthens vapour deposition (PECVD) is good, and will originally coarse wall smoothing.
The present invention with preferred embodiment explanation as above and is familiar with this field skill person, in not breaking away from spiritual scope of the present invention, retouches when doing a little change, and its scope of patent protection is defined by claims.
Claims (10)
1. one kind is blocked the dual-damascene method that gas release and projective structure produce, and it is characterized in that this method comprises:
Form first etching stopping layer on wafer;
Form first dielectric layer on this first etching stopping layer;
Form second etching stopping layer on this first dielectric layer;
Form second dielectric layer on this second etching stopping layer;
Form anti-reflecting layer on this second dielectric layer;
Form irrigation canals and ditches among above-mentioned anti-reflecting layer, second dielectric layer, second etching stopping layer and first dielectric layer;
Form a metal barrier layer on the surface and this anti-reflecting layer of above-mentioned irrigation canals and ditches;
Forming one is opened among this metal barrier layer, this anti-reflecting layer, second dielectric layer;
With this metal barrier layer of anisotropic etching processing procedure etching, make it residue in the surface of these irrigation canals and ditches;
Form metal material and be beneficial to make dual damascene in these irrigation canals and ditches, opening in above-mentioned second etching stopping layer and backfill; And
Grind this metal material to form dual-damascene structure.
2. the dual-damascene method that blocks gas release and projective structure generation according to claim 1 is characterized in that: before forming this metal material, more comprise formation one barrier layer in the surface of these irrigation canals and ditches and this opening.
3. the dual-damascene method that blocks gas release and projective structure generation according to claim 1, it is characterized in that: wherein this metal barrier layer is the TaN chemical vapor deposition layer.
4. the dual-damascene method that blocks gas release and projective structure generation according to claim 1, it is characterized in that: wherein this metal barrier layer is the TiN chemical vapor deposition layer.
5. the dual-damascene method that blocks gas release and projective structure generation according to claim 1, it is characterized in that: wherein this metal barrier layer is the WN chemical vapor deposition layer.
6. the dual-damascene method that blocks gas release and projective structure generation according to claim 1, it is characterized in that: wherein this metal barrier layer is the TiSiN chemical vapor deposition layer.
7. the dual-damascene method that blocks gas release and projective structure generation according to claim 1, it is characterized in that: wherein this metal barrier layer is the Ta chemical vapor deposition layer.
8. the dual-damascene method that blocks gas release and projective structure generation according to claim 1 is characterized in that: wherein this second etching stopping layer system is selected from the group that is made up of silicon nitride (SiN), carbonization silicon (SiC), nitrogen carbonization silicon (SiCN) and nitrogen oxidation of coal silicon (SiOCN).
9. the dual-damascene method that blocks gas release and projective structure generation according to claim 2, it is characterized in that: wherein this barrier layer utilizes physical vaporous deposition to form.
10. the dual-damascene method that blocks gas release and projective structure generation according to claim 2, it is characterized in that: wherein this barrier layer utilizes chemical vapour deposition technique to form.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 02105710 CN1215551C (en) | 2002-04-12 | 2002-04-12 | Double inlaying method for barriering gas release and generating projective structure |
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| CN 02105710 CN1215551C (en) | 2002-04-12 | 2002-04-12 | Double inlaying method for barriering gas release and generating projective structure |
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| CN1452234A true CN1452234A (en) | 2003-10-29 |
| CN1215551C CN1215551C (en) | 2005-08-17 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1324652C (en) * | 2003-11-10 | 2007-07-04 | 美格纳半导体有限公司 | Method for fabricating semiconductor device |
| CN100550316C (en) * | 2006-04-24 | 2009-10-14 | 台湾积体电路制造股份有限公司 | The formation method and the semiconductor structure of semiconductor structure |
| CN102386126A (en) * | 2010-09-03 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing structure of semiconductor device for forming structure of dual damascene |
| CN102569167A (en) * | 2010-12-16 | 2012-07-11 | 中芯国际集成电路制造(北京)有限公司 | Method for forming dual damascene structure |
| CN103000568A (en) * | 2011-09-15 | 2013-03-27 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnection layer manufacturing method |
| CN110739269A (en) * | 2019-10-25 | 2020-01-31 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method of forming the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8791549B2 (en) * | 2009-09-22 | 2014-07-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer backside interconnect structure connected to TSVs |
-
2002
- 2002-04-12 CN CN 02105710 patent/CN1215551C/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1324652C (en) * | 2003-11-10 | 2007-07-04 | 美格纳半导体有限公司 | Method for fabricating semiconductor device |
| CN100550316C (en) * | 2006-04-24 | 2009-10-14 | 台湾积体电路制造股份有限公司 | The formation method and the semiconductor structure of semiconductor structure |
| CN102386126A (en) * | 2010-09-03 | 2012-03-21 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing structure of semiconductor device for forming structure of dual damascene |
| CN102386126B (en) * | 2010-09-03 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing structure of semiconductor device for forming structure of dual damascene |
| CN102569167A (en) * | 2010-12-16 | 2012-07-11 | 中芯国际集成电路制造(北京)有限公司 | Method for forming dual damascene structure |
| CN103000568A (en) * | 2011-09-15 | 2013-03-27 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnection layer manufacturing method |
| CN110739269A (en) * | 2019-10-25 | 2020-01-31 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method of forming the same |
| CN110739269B (en) * | 2019-10-25 | 2020-11-20 | 武汉新芯集成电路制造有限公司 | Semiconductor device and method of forming the same |
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| CN1215551C (en) | 2005-08-17 |
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