CN102569167A - Method for forming dual damascene structure - Google Patents
Method for forming dual damascene structure Download PDFInfo
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- CN102569167A CN102569167A CN2010105928935A CN201010592893A CN102569167A CN 102569167 A CN102569167 A CN 102569167A CN 2010105928935 A CN2010105928935 A CN 2010105928935A CN 201010592893 A CN201010592893 A CN 201010592893A CN 102569167 A CN102569167 A CN 102569167A
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Abstract
A method for forming a dual damascene structure comprises the following steps: a semiconductor substrate is provided; a first dielectric layer and a second dielectric layer are sequentially formed on the semiconductor substrate; a trench is formed in the second dielectric layer, and a via hole is formed in the first dielectric layer at the bottom of the trench; the trench and the via hole are filled with metal Cu; Co-W-P alloy is formed on the surface of the metal Cu; the second dielectric layer is removed; and a third dielectric layer is formed on the first dielectric layer and on the side wall of metal Cu. The method avoids metal ions from diffusing and getting into the dielectric layers, and improves the reliability.
Description
Technical field
The present invention relates to semiconductor fabrication, relate in particular to a kind of formation method of dual-damascene structure.
Background technology
Along with development of semiconductor, the integrated level of VLSI chip is up to the scale of several hundred million and even tens devices, and two-layer above multiple layer metal interconnection technique is widely used.Traditional metal interconnectedly process by aluminum metal; But along with constantly reducing of device feature size in the IC chip; Current density in the metal interconnecting wires constantly increases, and the response time of requirement constantly reduces, and the conventional aluminum interconnection line can not meet the demands; Process less than 130nm after, the copper interconnecting line technology has replaced aluminum interconnecting technology.Compare with aluminium, the resistivity of metallic copper is lower, and the resistance capacitance (RC) that copper interconnecting line can reduce interconnection line postpones, and improves electromigration, improves the reliability of device.The copper interconnecting line technology of current main-stream is dual damascene technology (Dual Damascene).
Metallic copper also has shortcoming as interconnect material, and copper diffuses in substrate or the dielectric layer easily, after copper interconnection layer forms, need form dielectric cap above that and prevent its diffusion.But the adhesive force between copper and the commonly used dielectric cap material is relatively poor; Therefore still can cause copper to diffuse in its dielectric layer on every side; Make puncture voltage (Voltage Breakdown between the adjacent interconnection line; VBD) reduce, cause time correlation dielectric breakdown (TDDB, the Time Dependent DielectricBreakdown) problem of device.
In order to solve the sticking problem between copper and the dielectric cap; Solution commonly used is the metal cap that after forming dual-damascene structure, forms cobalt tungsten phosphorus material above that; Prevent the copper diffusion with this; Avoiding electromigration, can be the formation method of the disclosed a kind of metal cap of Chinese patent of 200510105104.x referring to application number specifically.
Fig. 1 shows the generalized section of a kind of dual-damascene structure of prior art formation, comprising: Semiconductor substrate 10; Dielectric layer 11 covers said Semiconductor substrate 10, and said dielectric layer 11 is generally low k (low k) dielectric layer or ultralow k (ultra low k) dielectric layer; Be formed with opening in the said dielectric layer 11, said opening can be a through hole, or the combining structure of through hole in the dual-damascene structure and groove, is filled with copper embolism 12 in the said opening; The surface coverage of said copper embolism has cobalt tungsten phosphorus 13.The formation method of said cobalt tungsten phosphorus 13 generally is to use and contains that cobalt, tungstenic and phosphorous plating bath electroless plating form; Cause damage owing to form the dielectric layer 11 of meeting pairs of openings sidewall in the said opening process in etching, metal ion 14 particularly cobalt ions diffuses in the said dielectric layer 11 easily.Because low-k materials and ultralow k material are more loose, wherein have a large amount of cavities, therefore cause the diffusion of metal ion 14 more easily, cause the TDDB problem, influence the reliability of dual-damascene structure.
Summary of the invention
The problem that the present invention solves is that metal ion diffuses into dielectric layer easily, influences the reliability of dual-damascene structure in the process that forms cobalt tungsten phosphorus.
For addressing the above problem, the invention provides a kind of formation method of dual-damascene structure, comprising:
Semiconductor substrate is provided, is formed with first dielectric layer and second dielectric layer on the said Semiconductor substrate successively;
In said second dielectric layer, form groove (trench), in first dielectric layer of said channel bottom, form through hole (via);
In said groove and through hole, fill metallic copper;
Form cobalt tungsten phosphorus on the surface of said metallic copper;
Remove said second dielectric layer;
On said first dielectric layer, the sidewall of said metallic copper forms the 3rd dielectric layer.
Optional, the material of said first dielectric layer is low-k materials or ultralow k material.
Optional, said second dielectric layer is different with the material of first dielectric layer, and the dielectric constant of said second dielectric layer is greater than the dielectric constant of said first dielectric layer.
Optional, the material of said second dielectric layer be selected from silicon nitride, silica or black diamond (BD, BlackDiamond).
Optional, the thickness of said second dielectric layer equals the degree of depth of said groove.
Optional, the material of said the 3rd dielectric layer is low-k materials or ultralow k material.
Optional, said the 3rd dielectric layer is gluey low-k materials or ultralow k material, spin coating (spin on) forms said the 3rd dielectric layer.
Optional, the material of said the 3rd dielectric layer is SiLK, polyimides (polyimide), norbornene polymer (polynorbornenes), benzocyclobutene (Benzocyclobutene) or polytetrafluoroethylene (PTFE).
Optional, after spin coating forms said the 3rd dielectric layer, also comprise: said the 3rd dielectric layer is freezed.
Optional, said the 3rd dielectric layer is freezed to comprise: said the 3rd dielectric layer is made public and/or cures.
Compared with prior art, the present invention has the following advantages:
The present technique scheme forms first dielectric layer and second dielectric layer successively on Semiconductor substrate; In second dielectric layer, form groove; In first dielectric layer, form through hole; In said groove and through hole, fill metallic copper afterwards, after the surface of said metallic copper forms cobalt tungsten phosphorus, remove said second dielectric layer and on said first dielectric layer, the sidewall of said metallic copper forms the 3rd dielectric layer.Because the formation after forming cobalt tungsten phosphorus of the 3rd dielectric layer, the forming process of cobalt tungsten phosphorus is to its not influence, the metal ion that does not therefore spread in the 3rd dielectric layer; And when forming cobalt tungsten phosphorus, first dielectric layer is positioned at second dielectric layer below, and therefore the influence of the metal ion that also can not be spread can effectively avoid the TDDB problem, helps improving the reliability of dual-damascene structure.
Further; The material of second dielectric layer of present technique scheme is different with the material of first dielectric layer; The thickness of second dielectric layer equals the degree of depth of groove; Therefore in second dielectric layer, form in the process of said groove, first dielectric layer can be used as etching barrier layer, helps the simplification of manufacturing process.
Further, the material of said the 3rd dielectric layer is gluey low-k materials or ultralow k material, and its formation method is spin coating, can effectively improve fillibility.
Description of drawings
Fig. 1 is the profile of a kind of dual-damascene structure of prior art;
Fig. 2 is the schematic flow sheet of formation method of the dual-damascene structure of the embodiment of the invention;
Fig. 3 to Fig. 8 is the profile of intermediate structure of formation method of the dual-damascene structure of the embodiment of the invention.
Embodiment
When prior art formed cobalt tungsten phosphorus on the surface of dual-damascene structure, metal ion diffused into dielectric layer easily, causes the TDDB problem easily, has reduced the reliability of dual-damascene structure.
The present technique scheme forms first dielectric layer and second dielectric layer successively on Semiconductor substrate; In second dielectric layer, form groove; In first dielectric layer, form through hole; In said groove and through hole, fill metallic copper afterwards, after the surface of said metallic copper forms cobalt tungsten phosphorus, remove said second dielectric layer and on said first dielectric layer, the sidewall of said metallic copper forms the 3rd dielectric layer.Because the formation after forming cobalt tungsten phosphorus of the 3rd dielectric layer, the forming process of cobalt tungsten phosphorus is to its not influence, the metal ion that does not therefore spread in the 3rd dielectric layer; And when forming cobalt tungsten phosphorus, first dielectric layer is positioned at second dielectric layer below, and therefore the influence of the metal ion that also can not be spread can effectively avoid the TDDB problem, helps improving the reliability of dual-damascene structure.
Further; The material of second dielectric layer of present technique scheme is different with the material of first dielectric layer; The thickness of second dielectric layer equals the degree of depth of groove; Therefore in second dielectric layer, form in the process of said groove, first dielectric layer can be used as etching barrier layer, helps the simplification of manufacturing process.
Further, the material of said the 3rd dielectric layer is gluey low-k materials or ultralow k material, and its formation method is spin coating, can effectively improve fillibility.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth detail in the following description so that make much of the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention does not receive the restriction of following disclosed embodiment.
Fig. 2 shows the schematic flow sheet of formation method of the dual-damascene structure of the embodiment of the invention, comprising:
Step S21 provides Semiconductor substrate, is formed with first dielectric layer and second dielectric layer on the said Semiconductor substrate successively;
Step S22 forms groove in said second dielectric layer, in first dielectric layer of said channel bottom, form through hole;
Step S23 fills metallic copper in said groove and through hole;
Step S24 forms cobalt tungsten phosphorus on the surface of said metallic copper;
Step S25 removes said second dielectric layer;
Step S26 is on said first dielectric layer, the sidewall of said metallic copper forms the 3rd dielectric layer.
Fig. 3 to Fig. 8 shows the profile of intermediate structure of formation method of the copper interconnection structure of the embodiment of the invention, below in conjunction with Fig. 2 and Fig. 3 to Fig. 8 embodiments of the invention is elaborated.
In conjunction with Fig. 2 and Fig. 3, execution in step S21 provides Semiconductor substrate, is formed with first dielectric layer and second dielectric layer on the said Semiconductor substrate successively.Concrete, Semiconductor substrate 20 is provided, be formed with first dielectric layer 21 and second dielectric layer 22 on the said Semiconductor substrate 20 successively, wherein, first dielectric layer 21 is positioned on the Semiconductor substrate 20, and second dielectric layer 22 is positioned on first dielectric layer 21.
Said Semiconductor substrate 20 can be a monocrystalline silicon; It also can be silicon Germanium compound; Can also be silicon-on-insulator (SOI; Silicon On Insulator) epitaxial layer structure on structure or the silicon wherein can also be formed with semiconductor device (not shown)s such as MOS transistor, and Semiconductor substrate described in the present embodiment 20 is a silicon substrate.
Said first dielectric layer 21 can be interlayer dielectric layer (ILD) material commonly used in the semiconductor technology, and in the present embodiment, said first dielectric layer 21 is a low-k materials; Like fluorine silex glass (FSG); Carbon doped silicon oxide (SiOC) etc. also can be ultralow k material, like nanoporous silica (NPS) etc.
The material of said second dielectric layer 22 also can be the inter-level dielectric layer material of using always; As a preferred embodiment; Second dielectric layer 22 is different with the material of first dielectric layer 21, and the dielectric constant of second dielectric layer 22 is greater than the dielectric constant of said first dielectric layer 21.Concrete, the material of second dielectric layer 22 is selected from silica, silicon nitride or black diamond in the present embodiment.
In conjunction with Fig. 2 and Fig. 4, execution in step S22 forms groove in said second dielectric layer, in first dielectric layer of said channel bottom, form through hole.Concrete, in said second dielectric layer 22, form groove 24, in said first dielectric layer 21, form through hole 23.The formation method of said groove 24 and through hole 23 can be the method for groove behind method or the first through hole of through hole behind the first groove in the traditional double mosaic texture forming process; Even with photoresist or hard mask layer define the figure of said groove 24 and through hole 23 respectively, etching forms groove 24 and through hole 23 respectively afterwards.
As a preferred embodiment, the material of said second dielectric layer 22 is different with first dielectric layer 21, and the thickness of second dielectric layer 22 equals the degree of depth of groove 24; Thereby form in the process of said groove 24 in etching; First dielectric layer 21 can be used as etching barrier layer, makes etching process stop on the surface of first dielectric layer 21, and need not go to regulate the etching menu or form extra etching barrier layer again; Help simplified manufacturing technique, raise the efficiency.
In conjunction with Fig. 2 and Fig. 5, execution in step S23 fills metallic copper in said groove and through hole.Concrete, in said groove and through hole, fill metallic copper 25, the formation method of said metallic copper 25 can be electrochemistry plating (ECP).In one embodiment, before forming metallic copper 25, can also form the barrier layer at the bottom and the sidewall of said groove and through hole, be used to prevent the diffusion of copper ion, the material on said barrier layer can be tantalum or tantalum nitride, and its formation method is a sputtering method.After the electrochemistry plating forms metallic copper 25, can also carry out planarization to its surface, so that the flush of the surface of metallic copper 25 and said second dielectric layer 22, the method for planarization can be chemico-mechanical polishing (CMP).
In conjunction with Fig. 2 and Fig. 6, execution in step S24 forms cobalt tungsten phosphorus on the surface of said metallic copper.Concrete; Form cobalt tungsten phosphorus 26 on the surface of said metallic copper 25; Its formation method can be to use and contain cobalt, tungstenic and phosphorous plating bath and carry out electroless plating; At the said cobalt tungsten of the surperficial self aligned formation phosphorus 26 of metallic copper 25, certainly, the formation method of said cobalt tungsten phosphorus 26 can also be to well known to a person skilled in the art additive method.
In conjunction with Fig. 2 and Fig. 7, execution in step S25 removes said second dielectric layer.Concrete, remove said second dielectric layer, expose the surface of said first dielectric layer 21 and the sidewall of metallic copper 25.The removal method of said second medium can be dry etching or wet etching.
In conjunction with Fig. 2 and Fig. 8, execution in step S26 is on said first dielectric layer, the sidewall of said metallic copper forms the 3rd dielectric layer.Concrete, on said first dielectric layer 21, form the 3rd dielectric layer 27 on the sidewall of said metallic copper 25.The material of said the 3rd dielectric layer 27 can be low-k materials or ultralow k material, and its formation method can be prior art common chemical vapour deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) etc.
As a preferred embodiment, the material of said the 3rd dielectric layer 27 is gluey low-k materials or ultralow k material, and its formation method is spin coating; Concrete, the material of the 3rd dielectric layer 27 can be SiLK, polyimides; Norbornene polymer, benzocyclobutene or polytetrafluoroethylene etc.Because after removing said second dielectric layer; The surface of metallic copper 25 exceeds the surface of said first dielectric layer 21; Make that whole surface topography is uneven; Adopt conventional formation method such as chemical vapour deposition (CVD) or plasma enhanced chemical vapor deposition, can cause the fillibility problem, produce like problems such as step coverage (step coverage) are low.Adopt the method for spin coating can make that gluey material is evenly distributed on first dielectric layer 21, the sidewall of metallic copper 25, effectively improved fillibility; In addition, in order further to improve fillibility, the 3rd dielectric layer 27 that spin coating forms in the present embodiment also covers the surface of said cobalt tungsten phosphorus 26.
After spin coating forms the 3rd dielectric layer 27,, also it is freezed in order to make gluey material setting; The method of freezing can be exposure and/or cure, in one embodiment, can use ultraviolet ray (UV) that it is made public; Adopt suitable temperature to cure afterwards; Make it freeze setting, the pattern after keeping forming forms other retes above that after being convenient to.Certainly, the difference of the concrete material of selecting according to the 3rd dielectric layer 27, also can be only through exposure or only it is freezed through curing.
Because said the 3rd dielectric layer 27 just forms, therefore do not receive the pollution of the forming process of cobalt tungsten phosphorus 26, the metal ion that does not wherein diffuse into after forming cobalt tungsten phosphorus 26; And in the process that forms cobalt tungsten phosphorus 26; First dielectric layer 21 receives the protection of second dielectric layer that covers on it, also can not receive the metal ion diffusion influence, therefore; Present embodiment can effectively be avoided the TDDB problem, helps improving the reliability of the dual-damascene structure of formation.
To sum up; The present technique scheme forms first dielectric layer and second dielectric layer successively on Semiconductor substrate; In second dielectric layer, form groove, in first dielectric layer, form through hole, in said groove and through hole, fill metallic copper afterwards; After the surface of said metallic copper forms cobalt tungsten phosphorus, remove said second dielectric layer and on said first dielectric layer, the sidewall of said metallic copper forms the 3rd dielectric layer.Because the formation after forming cobalt tungsten phosphorus of the 3rd dielectric layer, the forming process of cobalt tungsten phosphorus is to its not influence, the metal ion that does not therefore spread in the 3rd dielectric layer; And when forming cobalt tungsten phosphorus, first dielectric layer is positioned at second dielectric layer below, and therefore the influence of the metal ion that also can not be spread can effectively avoid the TDDB problem, helps improving the reliability of dual-damascene structure.
Further; The material of second dielectric layer of present technique scheme is different with the material of first dielectric layer; The thickness of second dielectric layer equals the degree of depth of groove; Therefore in second dielectric layer, form in the process of said groove, first dielectric layer can be used as etching barrier layer, helps the simplification of manufacturing process.
Further, the material of said the 3rd dielectric layer is gluey low-k materials or ultralow k material, and its formation method is spin coating, can effectively improve fillibility.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (11)
1. the formation method of a dual-damascene structure is characterized in that, comprising:
Semiconductor substrate is provided, is formed with first dielectric layer and second dielectric layer on the said Semiconductor substrate successively;
In said second dielectric layer, form groove, in first dielectric layer of said channel bottom, form through hole;
In said groove and through hole, fill metallic copper;
Form cobalt tungsten phosphorus on the surface of said metallic copper;
Remove said second dielectric layer;
On said first dielectric layer, the sidewall of said metallic copper forms the 3rd dielectric layer.
2. the formation method of dual-damascene structure according to claim 1 is characterized in that, the material of said first dielectric layer is low-k materials or ultralow k material.
3. the formation method of dual-damascene structure according to claim 2 is characterized in that, said second dielectric layer is different with the material of first dielectric layer, and the dielectric constant of said second dielectric layer is greater than the dielectric constant of said first dielectric layer.
4. the formation method of dual-damascene structure according to claim 3 is characterized in that, the material of said second dielectric layer is selected from silicon nitride, silica or black diamond.
5. the formation method of dual-damascene structure according to claim 3 is characterized in that, the thickness of said second dielectric layer equals the degree of depth of said groove.
6. the formation method of dual-damascene structure according to claim 1 is characterized in that, the material of said the 3rd dielectric layer is low-k materials or ultralow k material.
7. the formation method of dual-damascene structure according to claim 6 is characterized in that, said the 3rd dielectric layer is gluey low-k materials or ultralow k material, and spin coating forms said the 3rd dielectric layer.
8. the formation method of dual-damascene structure according to claim 7 is characterized in that, the material of said the 3rd dielectric layer is SiLK, polyimides, norbornene polymer, benzocyclobutene or polytetrafluoroethylene.
9. the formation method of dual-damascene structure according to claim 7 is characterized in that, after spin coating forms said the 3rd dielectric layer, also comprises: said the 3rd dielectric layer is freezed.
10. the formation method of dual-damascene structure according to claim 9 is characterized in that, said the 3rd dielectric layer is freezed to comprise: said the 3rd dielectric layer is made public and/or cures.
11. the formation method of dual-damascene structure according to claim 7 is characterized in that, said the 3rd dielectric layer also covers the surface of said cobalt tungsten phosphorus.
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Application publication date: 20120711 |