CN1567548A - Method and structure for forming barrier layer - Google Patents
Method and structure for forming barrier layer Download PDFInfo
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- CN1567548A CN1567548A CN 03143027 CN03143027A CN1567548A CN 1567548 A CN1567548 A CN 1567548A CN 03143027 CN03143027 CN 03143027 CN 03143027 A CN03143027 A CN 03143027A CN 1567548 A CN1567548 A CN 1567548A
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Abstract
The invention is a method of forming blocking layer, firstly making a double inserted structure on a metallic layer, where the structure contains a first dielectric layer and a second one, the former containing a hole and the latter containing a groove, successively forming a first tantalum metal layer on the structure, then forming a tantalum nitride layer on the first tantalum metal layer, eliminating the tantalum metal layer above the bottom of the hole in the first dielectric layer in an ion spattering mode, where the tantalum atoms in the eliminated tantalum nitride layer will deposit on the side wall of the hole in the first dielectric layer, and finally forming a second tantalum metal layer on the remained tantalum nitride layer, where there are only the first and second tantalum metal layers above the bottom of the hole, and the made blocking layer will have lower resistivity at the bottom of the hole and an ability to completely block copper atoms from diffusing to the dielectric layer.
Description
(1) technical field
The present invention is the method for making for a kind of semiconductor, especially is a kind of method of making barrier layer in the mosaic texture.
(2) background technology
In semiconductor fabrication, after the active member of finishing semiconductor element above the ground is made, next be the making that will carry out at the active member upper metal lead of finishing semiconductor element, desire is made the circuit connection of semiconductor element inside to finish.In the manufacturing process of above-mentioned plain conductor, normally above the active member of semiconductor element, form a metal level earlier, finishing the ground floor metal level by last photoresistance, little shadow, etching again makes, then again in ground floor metal level top deposition one dielectric layer, the needs of corresponding different semiconductor elements, the making of the back multiple layer metal layer that carries out again.
For many years, the material of plain conductor is based on aluminum metal or aluminum metal alloy always in the semiconductor, but the trend of dwindling day by day along with the semiconductor element size, service speed improves the demand that reduces with power consumption, therefore just need to use the lower material of lower metal material of resistivity and dielectric constant to finish the making of metal connecting line in the semiconductor element, United States Patent (USP) US 6,489, mentioned in 240 B1 numbers and used copper metal and dielectric constant to make the making of metal connecting line in the semiconductor element less than 4 dielectric layer, when using the copper metal to be used as the material of plain conductor, consider that the copper metal is difficult for forming the characteristic of gas molecule after etching, shown in Figure 1A, normally utilize a dual-damascene structure 10 to carry out the processing procedure that the copper metal is formed at this dual-damascene structure 10, United States Patent (USP) the 6th, 492, mention the mode of in a dual-damascene structure 10, making the copper plain conductor for 270 B1 numbers in detail, this dual-damascene structure 10 is by first etch stop 120, first dielectric layer 160, second etch stop and 140 second dielectric layers 180 form, before desiring in the dual-damascene structure 10 above copper metal layer 100 to finish the processing procedure that forms the copper metal, shown in Figure 1B, must on dual-damascene structure 10, form a barrier layer 190 earlier, diffuse in the dielectric layer on every side to prevent the copper metallic atom.
In the prior art; in order to prevent that the copper metallic atom from spreading in dielectric layer; usually can use as titanium nitride (TiN) or tantalum nitride (TaN) and carry out the making of barrier layer; United States Patent (USP) US 6; 541; promptly mention for 374 B1 numbers and utilize TiN to form barrier layer; but it is actual when carrying out the deposition of barrier layer 190; because the direction of deposition is approximately perpendicular to wafer surface; so thickness that is deposited at the sidewall position of dual-damascene structure 10; / 5th to 1/2nd of first dielectric layer, 160 inside aperture bottom and second dielectric layer, 180 an internal channel bottom top institute deposit thickness will be had only approximately; the copper metallic atom that not exclusively makes formation in the back dual-damascene structure 10 that causes side wall deposition easily is toward the interior diffusion of dielectric layer; and then influence dielectric layer electrically damage whole semiconductor element, therefore barrier layer deposition with dual-damascene structure 10 madial wall positions is just arranged fully to stop that the copper metallic atom diffuses to the demand in the dielectric layer.
On the other hand, the resistivity of metal nitride is high far beyond the resistivity of metal material in the prior art, therefore use as titanium nitride or tantalum nitride during as the interior barrier layer 190 of dual-damascene structure 10, to make intermetallic resistivity in the dual-damascene structure 10 too high and influence the service speed and the power consumption of semiconductor element, therefore just have the demand that reduces barrier layer 190 resistivity above first dielectric layer, the 160 inside aperture bottom.
(3) summary of the invention
A main purpose of the present invention is three layers of barrier layer structure utilizing the first metal layer, metal layer and second metal level to form, diffuses in the dielectric layer to stop the copper metallic atom fully.
Another main purpose of the present invention is for reducing the resistivity of top, the bottom of the hole in dielectric layer barrier layer in the mosaic texture, and make barrier layer and its below copper metal layer and with mosaic texture backward in the copper metal layer of formation good Ohmic contact is arranged.
The present invention utilizes chemical vapour deposition (CVD) or physical vapour deposition (PVD) mode to form a barrier layer structure on a conductor layer of semiconductor element, and the ion mode of splashing of using is removed the higher metal layer of conductor layer top resistivity to reduce the resistivity of the barrier layer structure that is connected with conductor layer.
(4) description of drawings
Figure 1A is the dual-damascene structure schematic diagram of a prior art;
Figure 1B is for forming the schematic diagram of one deck barrier layer on the dual-damascene structure of a prior art;
Fig. 2 A ~ E forms the formation step schematic diagram of multilayer barrier layer on a dual-damascene structure in one embodiment of the invention;
Fig. 3 A ~ E forms the formation step schematic diagram of multilayer barrier layer on a mosaic texture in another embodiment of the present invention;
Fig. 4 is for carrying out the schematic diagram of physical vapour deposition (PVD) reaction in the ionic medium precursor reactant device of the present invention; And
Fig. 5 carries out the schematic diagram that ion splashes reaction in the ionic medium precursor reactant device of the present invention.
(5) embodiment
Some embodiments of the present invention can be described in detail as follows.Yet except describing in detail, the present invention can also be widely implements at other embodiment.That is, the restriction of the embodiment that scope of the present invention is not subjected in this proposition, and should be as the criterion with the claim institute restricted portion that proposes later.
In first embodiment of the present invention, shown in Fig. 2 A ~ E, metal level 200 tops in a wafer have formed a dual-damascene structure 20, this dual-damascene structure 20 is by first etch stop 220, first dielectric layer 260 of first etch stop, 220 tops, second dielectric layer 280 of second etch stop 240 of first dielectric layer, 260 tops and second etch stop, 240 tops constitutes, wherein metal level 200 is to be a copper metal layer, and the material of first etch stop 220 and second etch stop 240 is for preventing that the copper metallic atom from diffusing to the material in the dielectric layer, as silicon nitride (Si
3N
4), with regard to first dielectric layer, 260 materials and second dielectric layer, 280 materials, its material can be silicon dioxide (SiO
2) or dielectric constant less than 4 material, the fluorinated silica glass (fluorinated silicate glass is called for short FSG) that forms in chemical vapour deposition (CVD) (chemical vapor deposition is called for short CVD) mode for example, silicone glass (organo silicate glass), fluoride amorphous carbon (fluorinated amorphouscarbon), hydrogenated amorphous carbon (hydrogenated amorphous carbon), tetrafluoro Parylene (tetrafluoro-poly-p-xylylene), or make the inorganic spin-on glasses HSQ (Hydrogenated Silsesquioxane) of formation in spin coating (spin) mode, aromatic polyether PAE (polyarylene ethers), the copolymerized macromolecule of divinyl siloxanes and two methylbenzene cyclobutane, aerosil (Aerogel), silica xerogel (Xerogel).
Shown in Fig. 2 A, above above-mentioned dual-damascene structure 20, form one first tantalum metal layer 300, the mode that forms this first tantalum metal layer 300 is to be chemical vapour deposition (CVD) mode (chemical vapordeposition is called for short CVD) or physical vapour deposition (PVD) mode (physical vapor deposition is called for short PVD), be to form this first tantalum metal layer 300 in the present embodiment with physical vapour deposition (PVD) mode PVD, as shown in Figure 4, in a plasma reactor 60, one wafer 62 is fixed on the chip-bearing disc 61, this chip-bearing disc 61 is connected a direct current bias voltage 65, fix the metal target stand 63 of a tantalum metallic target 64 again in these plasma reactor 60 tops, and with these metal target stand 63 ground connection, when carrying out the PVD reaction, argon ion in the plasma will be toward tantalum metallic target 64 bumps, wafer 62 tops will form first tantalum metal layer 300 and will be attracted to deposit so far by above-mentioned Dc bias 65 by the knocking-on tantalum atom of argon ion or tantalum ion, when carrying out the PVD reaction, between 0 Hao Alto ear to 50 Hao Alto ear between, process temperatures plasma reactor 60 in approximately between to Celsius 400 spend between approximately by 0 degree Celsius for processing procedure pressure in the plasma reactor 60.
Shown in Fig. 2 B, above established first tantalum metal layer 300, form tantalum nitride layer 320 again, the mode that forms this tantalum nitride layer 320 is to be CVD mode or PVD mode, be to make this tantalum nitride layer 320 in the present embodiment in the PVD mode, as form the mode of first tantalum metal layer 300, in plasma reactor 60, feed nitrogen, make nitrogen molecule and tantalum atom 67 that from tantalum metallic target 64, is clashed into out or tantalum ion 66 form this tantalum nitride layer 320 in wafer 62 reactions by argon ion, when carrying out this PVD reaction, between 0 Hao Alto ear to 50 Hao Alto ear between, process temperatures plasma reactor 60 in approximately between to Celsius 400 spend between approximately by 0 degree Celsius for processing procedure pressure in the plasma reactor 60.
Since the resistivity of tantalum nitride layer 320 with the difference of nitrogen-atoms component ratio approximately between 95 microhm-centimetres between 14800 microhm-centimetres, the resistivity of tantalum nitride layer 320 much larger than the resistivity of tantalum metal layer (α phase resistance rate approximately between 15 microhm-centimetres between 30 microhm-centimetres, β phase resistance rate approximately between 150 microhm-centimetres between 220 microhm-centimetres), and the resistivity of copper metal layer is about 1.7 microhm-centimetres, therefore in order to reduce the resistivity of first dielectric layer, 260 inside aperture bottom, just the tantalum nitride layer 320 of first dielectric layer, 260 inside aperture bottom must be removed.
Shown in Fig. 2 C, in the present embodiment in order to remove the tantalum nitride layer 320 of the hole bottom in first dielectric layer 260, taked an ion mode of splashing to remove the tantalum nitride layer 320 of the hole bottom in first dielectric layer 260, this ion splashes mode as shown in Figure 5, connect a plasma generation power supply 84 and an AC bias power supply 83 in a plasma reactor 80, fix again on the chip-bearing disc 81 of a wafer 82 in this plasma reactor, carrying out ion splashes when reacting, the direct current oneself bias voltage that utilizes AC bias power supply 83 to produce on chip-bearing disc 81 attracts the argon ion 86 in the plasma 85 to splash toward wafer 82 surfaces, the tantalum nitride layer 320 of the hole bottom in first dielectric layer 260 is splashed out tantalum atom 360, make the tantalum atom 360 that splashes out be deposited on hole sidewall in first dielectric layer 260, and remove the tantalum nitride layer 320 of the hole bottom in first dielectric layer 260, because the direct of travel of argon ion 86 is approximately perpendicular to wafer 82 surfaces, therefore the tantalum nitride layer 320 that originally is deposited on the hole sidewall in first dielectric layer 260 will bear than the hole bottom in first dielectric layer 260 and splash for few ion, in the present embodiment, the direct current oneself bias voltage that is produced on chip-bearing disc 81 will carry out the Dc bias of PVD reaction for high.
Finish the tantalum nitride layer 320 of the top, hole bottom of removing in first dielectric layer 260 via the above-mentioned ion mode of splashing after, this moment, the structure of metal level 200 tops will be shown in Fig. 2 D, first tantalum metal layer 300 is only deposited in top, hole bottom in first dielectric layer 260, the tantalum atom 360 that is hit by bottom of the hole in first dielectric layer 260 and channel bottom in second dielectric layer 280 forms the trenched side-wall below in the hole sidewall below and second dielectric layer 280 that are deposited on respectively in first dielectric layer 260 profile shown in Fig. 2 D, for another example shown in Fig. 2 E, form the mode of first tantalum metal layer 300 as described above, above tantalum nitride layer 320, form second tantalum metal layer 340, second tantalum metal layer 340 can use PVD or the mode of CVD forms, be to make second tantalum metal layer in the present invention in the PVD mode, as shown in Figure 4, in a plasma reactor 60, one wafer 62 is fixed on the chip-bearing disc 61, this chip-bearing disc 61 is connected a direct current bias voltage 65, fix the metal target stand 63 of a tantalum metallic target 64 again in these plasma reactor 60 tops, and with these metal target stand 63 ground connection, when carrying out the PVD reaction, argon ion in the plasma will be toward tantalum metallic target 64 bumps, wafer 62 tops will form second tantalum metal layer 340 and will be attracted to deposit so far by above-mentioned Dc bias 65 by the knocking-on tantalum atom 67 of argon ion or tantalum ion 66, when carrying out the PVD reaction, between 0 Hao Alto ear to 50 Hao Alto ear between, process temperatures plasma reactor 60 in approximately between to Celsius 400 spend between approximately by 0 degree Celsius for processing procedure pressure in the plasma reactor 60.
The barrier layer of this dual-damascene structure 20 will be shown in Fig. 2 E after completing, top, hole bottom in dual-damascene structure 20 interior first dielectric layers 260 is only by outside the tantalum metal layer of forming first tantalum metal layer 300 and second tantalum metal layer 340 as can be seen, these dual-damascene structure 20 interior other positions are all three layers of barrier layer and cover, these three layers of barrier layers are respectively first tantalum metal layer 300, the tantalum nitride layer 320 and second tantalum metal layer 340, use the former of tantalum metal because copper metal pair tantalum metal has good adhesive ability, and tantalum nitride can stop that the copper metallic atom spreads in dielectric layer, after the barrier layer of this three-decker finished, can obtain diffusing to dielectric layer to stop the copper metallic atom than sidewall barrier layer thicker in the prior art, and surpass 30% tantalum metal layer, and then good Ohmic contact is arranged with the copper metal layer of its below and the copper metal layer made backward than first dielectric layer, 260 inside aperture bottom top barrier layer resistivity decreased in the prior art.
In another embodiment of the present invention, shown in Fig. 3 A ~ E, metal level 400 tops in a wafer have formed a mosaic texture 40, this mosaic texture 40 is that the dielectric layer 440 by etch stop 420 and etch stop 420 tops is constituted, wherein metal level 400 is to be a copper metal layer, and the material of etch stop 420 is for preventing that the copper metallic atom from diffusing to the material in the dielectric layer 440, as silicon nitride (Si
3N
4), with regard to dielectric layer 440 materials, its material can be silicon dioxide (SiO
2) or dielectric constant less than 4 material, the fluorinated silica glass (fluorinated silicate glass is called for short FSG) that forms in chemical vapour deposition (CVD) (chemical vapor deposition is called for short CVD) mode for example, silicone glass (organo silicate glass), fluoride amorphous carbon (fluorinated amorphous carbon), hydrogenated amorphous carbon (hydrogenated amorphous carbon), tetrafluoro Parylene (tetrafluoro-poly-p-xylylene), or make the inorganic spin-on glasses HSQ (Hydrogenated Silsesquioxane) of formation in spin coating (spin) mode, aromatic polyether PAE (polyarylene ethers), the copolymerized macromolecule of divinyl siloxanes and two methylbenzene cyclobutane, aerosil (Aerogel), silica xerogel (Xerogel).
As shown in Figure 3A, above above-mentioned mosaic texture 40, form one first tantalum metal layer 460, the mode that forms this first tantalum metal layer 460 is to be chemical vapour deposition (CVD) mode (chemical vapor deposition is called for short CVD) or physical vapour deposition (PVD) mode (physical vapor deposition is called for short PVD), be to form this tantalum metal layer 460 in the present embodiment with physical vapour deposition (PVD) mode PVD, as shown in Figure 4, in a plasma reactor 60, one wafer 62 is fixed on the chip-bearing disc 61, this chip-bearing disc 61 is connected a direct current bias voltage 65, fix the metal target stand 63 of a tantalum metallic target 64 again in these plasma reactor 60 tops, and with these metal target stand 63 ground connection, when carrying out the PVD reaction, argon ion in the plasma will be toward tantalum metallic target 64 bumps, wafer 62 tops will form first tantalum metal layer 460 and will be attracted to deposit so far by above-mentioned Dc bias 65 by the knocking-on tantalum atom 67 of argon ion or tantalum ion 66, when carrying out the PVD reaction, between 0 Hao Alto ear to 50 Hao Alto ear between, process temperatures plasma reactor 60 in approximately between to Celsius 400 spend between approximately by 0 degree Celsius for processing procedure pressure in the plasma reactor 60.
Shown in Fig. 3 B, above established first tantalum metal layer 460, form tantalum nitride layer 480 again, the mode that forms this tantalum nitride layer 480 is to be CVD mode or PVD mode, be to make this tantalum nitride layer 480 in the present embodiment in the PVD mode, as form the mode of first tantalum metal layer 460, in plasma reactor 60, feed nitrogen, make nitrogen molecule and tantalum atom 67 that from tantalum metallic target 64, is clashed into out or tantalum ion 66 form this tantalum nitride layer 480 in wafer 62 reactions by argon ion, when carrying out this PVD reaction, between 0 Hao Alto ear to 50 Hao Alto ear between, process temperatures plasma reactor in approximately between to Celsius 400 spend between approximately by 0 degree Celsius for processing procedure pressure in the plasma reactor 60.
Since the resistivity of tantalum nitride layer 480 with the difference of nitrogen-atoms component ratio approximately between 95 microhm-centimetres between 14800 microhm-centimetres, the resistivity of tantalum nitride layer 320 much larger than the resistivity of tantalum metal layer (α phase resistance rate approximately between 15 microhm-centimetres between 30 microhm-centimetres, β phase resistance rate approximately between 150 microhm-centimetres between 220 microhm-centimetres), and the resistivity of copper metal layer is about 1.7 microhm-centimetres, therefore in order to reduce the resistivity of dielectric layer 440 inside aperture bottom, just the tantalum nitride layer 480 of dielectric layer 440 inside aperture bottom must be removed.
Shown in Fig. 3 C, in the present embodiment in order to remove the tantalum nitride layer 480 of the hole bottom in the dielectric layer 440, taked an ion mode of splashing to remove the tantalum nitride layer 480 of the hole bottom in the dielectric layer 440, this ion splashes mode as shown in Figure 5, connect a plasma generation power supply 84 and an AC bias power supply 83 in a plasma reactor 80, fix again on the chip-bearing disc 81 of a wafer 82 in this plasma reaction 80, carrying out ion splashes when reacting, the direct current oneself bias voltage that utilizes AC bias power supply 83 to produce on chip-bearing disc 81 attracts the argon ion 86 in the plasma 85 to splash toward wafer 82 surfaces, the tantalum nitride layer 480 of the bottom of the hole in the dielectric layer 440 is splashed out tantalum atom 520, make the tantalum atom 520 that splashes out be deposited on hole sidewall in the dielectric layer 440, and the tantalum nitride layer 480 of the hole bottom in the removal dielectric layer 440, because the direct of travel of argon ion 86 is approximately perpendicular to wafer 82 surfaces, therefore the tantalum nitride layer 480 that originally is deposited on the hole sidewall in the dielectric layer 440 will bear than the bottom of the hole in the dielectric layer 440 and splash for few ion, in the present embodiment, the direct current oneself bias voltage that is produced on chip-bearing disc 81 will carry out the Dc bias of PVD reaction for high.
Finish the tantalum nitride layer 480 of the top, hole bottom of removing in the dielectric layer 440 via the above-mentioned ion mode of splashing after, this moment, the structure of metal level 400 tops will be shown in Fig. 3 D, first tantalum metal layer 460 is only deposited in top, hole bottom in the dielectric layer 440, the tantalum atom 520 that is hit by the bottom of the hole in the dielectric layer 440 will be deposited on the hole sidewall below in first dielectric layer 440 and form profile shown in Fig. 3 D, for another example shown in Fig. 3 E, form the mode of first tantalum metal layer 460 as described above, above tantalum nitride layer 480, form second tantalum metal layer 500, second tantalum metal layer 500 can use PVD or the mode of CVD forms, be to make second tantalum metal layer in the present invention in the PVD mode, as shown in Figure 4, in a plasma reactor 60, one wafer 62 is fixed on the chip-bearing disc 61, this chip-bearing disc 61 is connected a direct current bias voltage 65, fix the metal target stand 63 of a tantalum metallic target 64 again in these plasma reactor 60 tops, and with these metal target stand 63 ground connection, when carrying out the PVD reaction, argon ion in the plasma will be toward tantalum metallic target 64 bumps, wafer 62 tops will form second tantalum metal layer 500 and will be attracted to deposit so far by above-mentioned Dc bias 65 by the knocking-on tantalum atom of argon ion or tantalum ion, when carrying out the PVD reaction, between 0 Hao Alto ear to 50 Hao Alto ear between, process temperatures plasma reactor 60 in approximately between to Celsius 400 spend between approximately by 0 degree Celsius for processing procedure pressure in the plasma reactor 60.
The barrier layer of this mosaic texture 40 of back that completes will be shown in Fig. 3 E, top, hole bottom in mosaic texture 40 inner-dielectric-ayers 440 is only by outside the tantalum metal layer of forming first tantalum metal layer 460 and second tantalum metal layer 500 as can be seen, these mosaic texture 40 interior other positions are all three layers of barrier layer and cover, these three layers of barrier layers are respectively first tantalum metal layer 440, the tantalum nitride layer 480 and second tantalum metal layer 500, use the former of tantalum metal because copper metal pair tantalum metal has good adhesive ability, and tantalum nitride can stop that the copper metallic atom spreads in dielectric layer, with the barrier layer of this three-decker finish after, can obtain diffusing to dielectric layer 440 to stop the copper metallic atom than sidewall barrier layer thicker in the prior art, and surpass 30% tantalum metal layer, and then good Ohmic contact is arranged with the copper metal layer 400 of its below and the copper metal layer of making backward than dielectric layer inside aperture bottom top barrier layer resistivity decreased in the prior art.
The above is preferred embodiment of the present invention only, is not in order to limit claim of the present invention.Still can be changed in the category that does not break away from flesh and blood of the present invention and implemented, these variations should still belong to scope of the present invention.Therefore, category of the present invention is defined by following claim.
Claims (23)
1. method that forms barrier layer comprises:
One conductor layer is provided, has one first dielectric layer on this conductor layer, and have a hole in this first dielectric layer;
Form a first metal layer on this dielectric layer and this conductor layer;
Form a metal layer on this first metal layer;
Ionic bombardment is positioned at this metal layer of a bottom of this hole, a feasible sidewall that is deposited on this hole by the metallic atom in this metal layer that hits; And
Form one second metal level on this metal layer.
2. the method for formation barrier layer as claimed in claim 1 is characterized in that, described conductor layer comprises a copper metal layer.
3. the method for formation barrier layer as claimed in claim 1 is characterized in that, the dielectric layer material of described first dielectric layer comprises dielectric constant less than 4 insulation material.
4. the method for formation barrier layer as claimed in claim 1, it is characterized in that, before forming this first metal layer, also comprise and form one second dielectric layer on this first dielectric layer, wherein have a groove in this second dielectric layer, and this interior hole of this groove and this first dielectric layer in this second dielectric layer is communicated with.
5. the method for formation barrier layer as claimed in claim 4 is characterized in that, the dielectric layer material of described second dielectric layer comprises dielectric constant less than 4 insulation material.
6. the method for formation barrier layer as claimed in claim 1 is characterized in that, described the first metal layer comprises in the physical vapour deposition (PVD) mode and forms.
7. the method for formation barrier layer as claimed in claim 1 is characterized in that, described the first metal layer comprises in the chemical vapour deposition (CVD) mode and forms.
8. the method for formation barrier layer as claimed in claim 1 is characterized in that, described the first metal layer comprises a tantalum metal layer.
9. the method for formation barrier layer as claimed in claim 1 is characterized in that, described metal layer comprises in the physical vapour deposition (PVD) mode and forms.
10. the method for formation barrier layer as claimed in claim 1 is characterized in that, described metal layer comprises in the chemical vapour deposition (CVD) mode and forms.
11. the method for formation barrier layer as claimed in claim 1 is characterized in that, described metal layer comprises the tantalum nitride layer.
12. the method for formation barrier layer as claimed in claim 1 is characterized in that, described ionic bombardment mode intermediate ion source comprises argon ion.
13. the method for formation barrier layer as claimed in claim 1 is characterized in that, described second metal level comprises in the physical vapour deposition (PVD) mode and forms.
14. the method for formation barrier layer as claimed in claim 1 is characterized in that, described second metal level comprises in the chemical vapour deposition (CVD) mode and forms.
15. the method for formation barrier layer as claimed in claim 1 is characterized in that, described second metal level comprises a tantalum metal layer.
16. a barrier layer structure comprises:
One first dielectric layer, this first dielectric layer are formed at conductor layer top, and have a hole in this first dielectric layer, and the hole in this first dielectric layer is communicated with this conductor layer;
One the first metal layer, this first metal layer ladder are covered in this first dielectric layer top;
One metal layer, this metal layer ladder are covered in this first metal layer top, but this metal layer is not covered in this first metal layer of this hole top that is communicated with this conductor layer in this first dielectric layer; And
One second metal level, this second metal level ladder are covered in this metal layer top, and this second metal level is covered in this first metal layer of this hole top that is communicated with this conductor layer in this first dielectric layer.
17. barrier layer structure as claimed in claim 16 is characterized in that described conductor layer comprises a copper metal layer.
18. barrier layer structure as claimed in claim 16 is characterized in that, the dielectric layer material of described first dielectric layer comprises dielectric constant less than 4 insulation material.
19. barrier layer structure as claimed in claim 16 also comprises one second dielectric layer on this first dielectric layer, have a groove in this second dielectric layer, and this interior hole of this groove and this first dielectric layer in this second dielectric layer is communicated with.
20. barrier layer structure as claimed in claim 19 is characterized in that, the dielectric layer material of described second dielectric layer comprises dielectric constant less than 4 insulation material.
21. barrier layer structure as claimed in claim 16 is characterized in that described the first metal layer comprises a tantalum metal layer.
22. barrier layer structure as claimed in claim 16 is characterized in that described metal layer comprises the tantalum nitride layer.
23. barrier layer structure as claimed in claim 16 is characterized in that, described second metal level comprises a tantalum metal layer.
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| CNB031430279A CN1317745C (en) | 2003-06-13 | 2003-06-13 | Method and structure for forming barrier layer |
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| US6541374B1 (en) * | 2000-12-18 | 2003-04-01 | Novellus Systems, Inc. | Method of depositing a diffusion barrier for copper interconnection applications |
| US6383920B1 (en) * | 2001-01-10 | 2002-05-07 | International Business Machines Corporation | Process of enclosing via for improved reliability in dual damascene interconnects |
-
2003
- 2003-06-13 CN CNB031430279A patent/CN1317745C/en not_active Expired - Lifetime
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| US8679972B1 (en) | 2001-03-13 | 2014-03-25 | Novellus Systems, Inc. | Method of depositing a diffusion barrier for copper interconnect applications |
| US9508593B1 (en) | 2001-03-13 | 2016-11-29 | Novellus Systems, Inc. | Method of depositing a diffusion barrier for copper interconnect applications |
| US9099535B1 (en) | 2001-03-13 | 2015-08-04 | Novellus Systems, Inc. | Method of depositing a diffusion barrier for copper interconnect applications |
| US8043484B1 (en) | 2001-03-13 | 2011-10-25 | Novellus Systems, Inc. | Methods and apparatus for resputtering process that improves barrier coverage |
| US9117884B1 (en) | 2003-04-11 | 2015-08-25 | Novellus Systems, Inc. | Conformal films on semiconductor substrates |
| US8765596B1 (en) | 2003-04-11 | 2014-07-01 | Novellus Systems, Inc. | Atomic layer profiling of diffusion barrier and metal seed layers |
| US7855147B1 (en) * | 2006-06-22 | 2010-12-21 | Novellus Systems, Inc. | Methods and apparatus for engineering an interface between a diffusion barrier layer and a seed layer |
| US8298936B1 (en) | 2007-02-01 | 2012-10-30 | Novellus Systems, Inc. | Multistep method of depositing metal seed layers |
| US8449731B1 (en) | 2007-05-24 | 2013-05-28 | Novellus Systems, Inc. | Method and apparatus for increasing local plasma density in magnetically confined plasma |
| US7922880B1 (en) | 2007-05-24 | 2011-04-12 | Novellus Systems, Inc. | Method and apparatus for increasing local plasma density in magnetically confined plasma |
| US7897516B1 (en) | 2007-05-24 | 2011-03-01 | Novellus Systems, Inc. | Use of ultra-high magnetic fields in resputter and plasma etching |
| US8017523B1 (en) | 2008-05-16 | 2011-09-13 | Novellus Systems, Inc. | Deposition of doped copper seed layers having improved reliability |
| CN102569167A (en) * | 2010-12-16 | 2012-07-11 | 中芯国际集成电路制造(北京)有限公司 | Method for forming dual damascene structure |
| CN106158733A (en) * | 2015-04-22 | 2016-11-23 | 中国科学院微电子研究所 | A kind of copper interconnection structure and manufacture method thereof |
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| CN1317745C (en) | 2007-05-23 |
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