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Stabilized surface between a fluorosilicate glass dielectric and a liner/barrier layer

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Publication number
WO2002013234A2
WO2002013234A2 PCT/US2001/024177 US0124177W WO2002013234A2 WO 2002013234 A2 WO2002013234 A2 WO 2002013234A2 US 0124177 W US0124177 W US 0124177W WO 2002013234 A2 WO2002013234 A2 WO 2002013234A2
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Prior art keywords
layer
plasma
process
fsg
surface
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PCT/US2001/024177
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French (fr)
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WO2002013234A3 (en )
Inventor
Farhad Moghadam
Dana Tribula
Hichem M'saad
Nety M. Krishna
Nirmalya Maity
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Applied Materials, Inc.
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76826Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric

Abstract

A method of stabilizing a fluorosilicate glass (FSG) (36, 40) used as an inter-level dielectric layer and having via or other holes (42, 44) formed therethrough for contacting an aluminium or copper metallization. The FSG layer including the hole is subjected first to a plasma of nitrogen and possibly hydrogen and then to an argon plasma. The nitrogen plasma creates a nitrogen-rich surface, which reacts with the after deposited titanium to form a thin stable TiN layer. The nitrogen plasma may be applied at relatively low power. The hydrogen plasma removes free fluorine in the FSG which can create problems with peeling. The hydrogen/nitrogen may be supplied in the form of forming gas containing less than 7 % hydrogen. The subsequent argon plasma cleans the surface, including possibly removing a nitrided aluminium surface formed by the nitrogen plasma from an aluminium metallization. The process may also be applied to a copper dual-damascene metallization. After the two plasma treatments, a liner/barrier layer, preferably of Ti/TiN for Al and Ta/TaN for Cu, is coated on the walls of the hole and over the top of the FSG layer, and a metal is deposited in the hole to fill it.

Description

Stabilized Surface between a Fluorosilicate Glass Dielectric and a Liner/Barrier Layer

FIELD OF THE INVENTION

The invention relates generally to the fabrication of silicon integrated circuits. The invention relates particularly to a surface treatment of an inter-level dielectric layer.

BACKGROUND ART

The increasing level of integration in silicon integrated circuits is being accomplished in large part by the decreasing separation between adjacent features. However, the thickness of many of the layers is restrained to remain at moderately large values. For example, the thickness of inter-level dielectric layers needs to be no less than about 0.7μm to prevent inter-level discharge and cross talk. The thickness of horizontal metal interconnects needs to be kept moderately high so that the current density does not become too high. These requirements impose the restraints that the ratio of the width to the depth of many features, known as the aspect ratio, needs to be relatively high. Such high aspect ratios introduce difficulties in etching and filling these features. Various techniques have been found to achieve such high aspect-ratio features, but these techniques often introduce further problems which need to be addressed.

An example of such a problem occurs in an inter-level dielectric. Three steps in the fabrication process of such an inter-level dielectric are illustrated in the three cross- sectional views of FIGS. 1-3. A lower-level dielectric layer 10 has formed on its upper surface a wiring patterning including metal lines 12, some of the details of which are omitted from the drawings. Typically, the metal lines 12 are formed of aluminum, which may be alloyed with less than 5 wt% of an alloying element, for example, copper or silicon. The metal lines 12 of the illustrated wiring layer are connected to wiring layers above and below by vias and contacts through the lower inter-level dielectric 10 and an upper dielectric layer to be shortly described. As illustrated, these metal lines 12 are formed to have a moderately high aspect ratio and to be spaced with a narrow gap 14 between them. Aspect ratios for the lines 12 may be 1 : 1, and higher values are contemplated. The gap 16 between the lines 12 may have a width of less than 0.4μm and an aspect ratio of 2 or greater. As mentioned, such high aspect ratios enable yet higher levels of integration on a single integrated circuit chip.

The metal lines 12, after they have been formed, need to be covered by a dielectric layer forming the next inter-level dielectric layer, and the dielectric needs to fill the gap 14 as well. Filling dielectric into such a naπow gap 14 is a challenge for the typically used TEOS silica produced by plasma-enhanced chemical vapor deposition (PECVD) using tetraethylorthosilicate (TEOS) as the precursor. Any void in the dielectric creates serious reliability problems. Furthermore, neighboring lines 12 are capacitively coupled across the gap 14, and the coupling increases with decreasing gap width. Excessive coupling, particularly for long buses, introduces electronic cross talk between bus channels. TEOS silica typically has a relatively high dielectric constant of about 3.9. For this reason, it is desired to use an inter-level dielectric material having a lower dielectric constant, often referred to as a low-k dielectric. For reasons to be described later in more detail, a preferred inter-level dielectric for advanced applications is fluorosilicate glass (FSG). As illustrated schematically in the cross-sectional view of FIG. 1, a FSG dielectric layer 16 deposited by HDP-CVD tends to be conformal so that it effectively fills the deep gap 14. However, the conformality also results in hillocks 18 formed over the wiring lines 12. The hillocks 18 present a problem because the vias to be formed through the upper inter-level dielectric layer 16 need to be photo lithographically formed over the wiring lines 12, and the irregular surface topography around the overlying hillocks 18 would prevent accurate patterning of the photoresist. To overcome this problem, the structure of FIG. 1 is subjected to dielectric chemical mechanical polishing (CMP) to remove any surface irregularities including those arising from a wavy substrate and to produce a smooth dielectric surface 20, illustrated in the cross-sectional view of FIG. 2.

The smooth surface 20 produced by CMP allows accurate photolithography, which allows etching, as illustrated in the cross-sectional view of FIG.3, of deep and narrow via holes through the upper-level dielectric layer 16. These via holes have relatively high aspect ratios of 2: 1 or more and, unlike the illustration, have widths considerably naπower than do the lines 12 so that inter-level registration is less of a problem. As a result, the via holes in advanced devices have widths of 0.25μm or less. Metal tends do not adhere well to silica so that an adhesion layer is needed. The metal, particularly if it is aluminum, tends to diffuse into the silica and degrade its dielectric properties, and the oxygen in the silica tends to diffuse into the metal and degrade its electrical conductivity. As a result, a barrier is needed between the silica and the metal. Furthermore, filling metal into a deep, narrow hole is difficult and may require an adhesion layer to promote planar deposition of the metal. For one or more of these reasons, a barrier/liner is typically coated onto the substrate after the etching of the via hole and before the metallization. For FSG in combination with aluminum metallization, the barrier/liner usually includes an adhesion layer 24 of titanium (Ti) and a barrier layer 26 of titanium nitride (TiN). After the barrier/liner has been deposited, a metal layer 28 is filled into the hole and over the top surface 20. The metal layer 28 may be composed of tungsten to form a tungsten plug in the via hole. In this case, the tungsten is deposited to only a minimal thickness outside the via hole, and the excess tungsten is removed by either etching or CMP. The metal layer 28 alternatively may be composed of aluminum. In this case, a relatively thick layer of aluminum is deposited outside the via hole, and the aluminum thereafter is patterned into horizontal interconnects.

However, the interface between a metal and silica is not a favorable one. We have observed that the interface between the CMP -processed upper FSG surface 20 and the liner/barrier 24, 26 is a source of problems. If the titanium layer 24 exceeds a thickness of about lOnm, it tends to peel away from the FSG layer 16, both inside the via hole and on the planar top surface, obviously not a good effect. The thicker the titanium, the greater the tendency to peel. We believe that the problem originates in the tendency of CMP -processed FSG layer to absorb hydrogen, which generally destabilizes FSG. Further, the hydrogen forms hydrofluoric acid (HF), which etches oxide. Also, the titanium and fluorine in FSG tend to form islands of titanium fluoride (TiFJ. This material is poorly lattice matched to Ti and introduces significant stress with larger thicknesses of titanium. Such stress promotes peeling.

Copper metallization is being rapidly established for advanced integrated circuits because of its lower resistivity and reduced electromigration. Typically, copper may contain up to 5 at% of an alloying element such as aluminum or magnesium. However, copper is difficult or at least expensive to etch. As a result, copper metallization is usually practiced on a dual-damascene structure illustrated in the cross-sectional view of FIG. 4. Assuming that an inter-level dielectric layer is being formed, a lower-level dielectric layer 30 already has formed in its surface a copper-filled trench 32. Again, some of the details are not illustrated. Chemical mechanical polishing (CMP) is usually used to polish a smooth and level upper surface 34 for the lower-level dielectric 30 and its metallization 32. Thereafter, an unpattemed structure is formed including a lower dielectric layer 36, a thin etch stop layer 38, and an upper dielectric layer 40 to complete the inter-level dielectric. When the dielectric is an oxide, the etch stop may be silicon nitride. Other layers may be present. Two steps of photolithography produce a via hole 42 and a trench 44. The via hole 42 is a vertical hole of small width providing electrical contact to the underlying metal line 32 while the trench 44 is wider and extends laterally in the other direction in a horizontal interconnect pattern. A barrier layer 46 is conformally coated on the structure. For copper in combination with oxide, the barrier layer 46 may be a Ta/TaN bilayer, but a TaN layer alone has been demonstrated to be effective. The TaN preferably has a composition of about 65 at% Ta and 35 at% N.

Copper is simultaneously filled into the via hole 42 and the trench 44. In a preferred process, a copper layer is first deposited by a nearly conformal process to form a thin seed and electrode layer. Then, the copper deposition is completed by electrochemical plating (ECP). The ECP copper is coated to a sufficient depth to overflow the trench and coat the top of the illustrated structure. A subsequent CMP step polishes away the copper and nitride and stops on the oxide, but leaving copper filling the trench 44.

The dual-damascene process does not present a significant dielectric filling problem, but cross talk is even more of a problem because copper and dual damascene are being applied to integrated circuits with very small lateral separation between features with potentially correspondingly increased horizontal capacitance and cross talk.

The filling and cross talk problems resulting from aluminum and copper metallization have both been met by the deposition of fluorosilicate glass (FSG) by chemical vapor deposition (CVD) including a high-density plasma (HDP). FSG is a one of a class of halogenated silicate glasses that exhibit a reduced dielectric constant relative to silicon dioxide. Depositing this material by HDP-CVD promotes deep gap filling. Orczyk et al. in U.S. Patent 5,937,323 describe depositing FSG in the Ultima HDP-CVD reactor available from Applied Materials, Inc. of Santa Clara, California, but FSG may also be deposited by plasma enhanced chemical vapor deposition (PECVD) in a chamber relying only on capacitive coupling of RF power in contrast to the additional inductive coupling in the typical HDP CVD reactor.

For depositing FSG in an HDP reactor, the typical precursors are SiH4, SiF4, O2, and Ar. The HDP CVD process typically uses 3 to lOkW of RF power with a 200mm wafer and typically including inductively coupling power RF power into a separate plasma source region with a chamber pressure of 1 to 20 milliTorr to produce a plasma density of at least 10I2cm"3. Power levels scale generally with the area of the wafer.

For depositing FSG in a PECVD reactor, two recipes are typically practiced. The first includes SiH4, SiF4, and either N2O or O2. The second includes tetraethyl orthosilicate (TEOS), SiF4, and either N2O or O2. The PECVD process typically uses a 100 to 400W of RF power with a chamber pressure of between 1 and 100 Torr to produce a plasma density of typically 109cm"3 and no more than 1010cm"3. CVD is normally a conformal deposition process that more easily reaches into deep, narrow holes.

For aluminum metallization, such as in the configuration shown in FIG. 1, FSG typically has a fluorine content of 6 to 8 at%. However, it is known to vary the fluorine content at the different depths. When the gap 14 between the metal lines 12 is being filled, the fluorine content is elevated up to 10 at%, which produces a dielectric constant of 3.3 to 3.4, but in the volume above the lines and gap the fluorine content is reduced to 6 to 8 at%, which produces a dielectric constant of 3.5 to 3.6. HDP CVD can be used for depositing all the FSG, or the deposition can be divided into two steps. The first step uses HDP CVD and fills FSG into the gap and deposits a relatively thin FSG layer above the lines. The second step uses either of the PECVD recipes to complete the planar FSG layer.

Copper metallization usually is formed in the previously described dual- damascene process. In this case, the FSG dielectric layer is deposited by either HDP CVD or PECVD with a fluorine content of 9 to 12 and possibly 13 at%, which produces a dielectric constant of 3.3 to 3.5.

Various methods have been suggested for treating the FSG surface. Ryu et al. have suggested in U.S. Patent Application, Serial No. 08/950,923, filed October 15, 1997 depositing a titanium nitride layer over the FSG layer, but this process has not been integrated with hole filling. M'Saad et al. have suggested in U.S. Patent Application, Serial No. 09/337,983, filed June 22, 1999 the nitrogen plasma treatment of polished FSG and related glasses. Because their nitrogen plasma is performed on an unetched FSG layer, the nitriding must reach through the entire thickness of the FSG layer, 800nm and more, if it is to be effective at providing treated FSG on the via sidewalls. As a result, their treatment is performed at high power of 2000W total RF power to the two coils and 400W RF power to bias the electrode and for a relatively long time of 40 to 70s. Swope et al. describe a related process in "Improvement of adhesion properties of fluorinated silica glass film by nitrous oxide plasma treatment," Journal of the Electrochemical Society, vol. 144, no. 7, July 1997, pp. 2559-2564. A disadvantage of this approach is the expense of a high-power reactor, particularly one using inductively coupled power to increase the plasma density. Also, a prolonged treatment time, or subsequent anneal, is required to treat to the depth of the entire inter-level dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 through 3 are cross-sectional view illustrating the formation of a inter- level metallization including a dielectric deep fill, particularly applicable to aluminum metallization. FIG. 4 is a cross-sectional view illustrating a dual-damascene structure, particularly useful with copper metallization.

FIG. 5 is a flow diagram of a first process of the invention for forming inter-level vias and filling them with aluminum.

FIG. 6 is a flow diagram of a second process of the invention for forming inter- level vias trench horizontal interconnects and filling them with copper.

SUMMARY OF THE INVENTION

The invention includes the plasma treatment of a surface of a halogenated silicate glass, for example, fluorinated silicate glass (FSG). The glass surface may have been chemically mechanically polished prior to the plasma treatment. The plasma treatment includes exposure to a nitrogen plasma, optionally containing hydrogen, such as in forming gas containing 5-7% H2 and the remainder being N2.

The nitrogen plasma treatment may be followed by an argon plasma preclean treatment. The argon plasma preclean is particularly useful when an aluminum metallization has been exposed to the nitrogen plasma and as a result has been nitrided. The invention is particularly useful in stabilizing the oxide walls of a via or contact hole in preparation for the deposition of a liner/barrier comprising Ti/TiN, Ta/TaN, or other material, whereby peeling of the liner/barrier is reduced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

According to one aspect of the invention, the surface of a fluorosihcate glass can be stabilized by treating it with a nitrogen-containing plasma, preferably a plasma of nitrogen gas, for example, of forming gas which additionally contains hydrogen.

A process including the surface stabilization of the invention is summarized in the flow diagram of FIG. 5. This process is particularly useful for aluminum metallization having the structure generally illustrated in FIG. 1. In step 60 of the process, a dielectric layer of fluorosilicate glass (FSG) is deposited by plasma-enhanced chemical vapor deposition (PECVD) using a capacitively coupled reactor or by high- density plasma (HDP) CVD. The recipes for these two types of FSG deposition have been discussed in the background section, but other recipes are possible.

The process optimized for conformal deposition so as to fill deep gaps usually produces hillocks in the top FSG surface. These hillocks are removed in step 52 by dielectric chemical mechanical polishing. In step 54, the via holes or other types of holes are photolithographically formed in the FSG layer by first a photomask definition step and then by a plasma etching process. It is understood that the photolithography may involve many steps and be facilitated by additional layers not illustrated or described here. However, it is assumed that a surface in the fluorosilicate glass possibly processed by CMP is left exposed to air before the start of a sequence 60 of treatment and hole filling, preferably performed in large part in a single integrated processing tool, such as the Endura platform from Applied Materials, in which wafers are transferred between processing stations in a vacuum environment so as to reduce particle contamination and oxidation.

In step 62, the wafer with an etched hole and an exposed FSG surface is transfeπed into the integrated processing tool and is oriented and degassed. Thereafter, as long as the wafer remain under vacuum in the processing tool, the wafer surface remains clean, and the processing is continued in a controlled vacuum environment. In step 64, the wafer having the pre-formed via holes is subjected to a nitrogen gas plasma treatment. The nitrogen is preferably supplied in gaseous form as one component of forming gas. Forming gas is conventionally used in a non-plasma oxide anneal treatment to tie up dangling electronic bonds at the interface of silica and an electrode that would be subject to undesired biasing by such dangling bonds. Forming gas typically contains 5 to 7% H2 in an N2 diluent. The hydrogen fraction in a conventional forming gas is limited for safety reasons to 7% with the remainder being essentially nitrogen. The hydrogen/nitrogen fraction in the surface treatment step may be freely varied from all nitrogen and no hydrogen up to very large fractions of hydrogen. For safety reasons, it may be desired to limit the hydrogen content to 7% with the remainder being principally nitrogen. The nitrogen is believed to getter any residual hydrogen produced by CMP at the FSG surface. The use of hydrogen alone only may be sufficient to clean fluorine from the FSG surface, which is believed to be a significant cause of poor adhesion, but it does not nitride the FSG. On the other hand, use of nitrogen alone accomplishes the important nitriding.

The nitriding, we believe, accomplishes several important functions. It reduces the reactivity of the FSG to the hydroxyl ion OH" because of the reduced reactivity of the Si-N bond relative to the Si-O bond because nitrogen is less electronegative than oxygen. Also, nitriding FSG stabilizes the Si-F bond by forming Si-N bonds near the Si-F bonds. The nitrogen in the plasma creates a nitrogen-rich surface of the FSG, which may react with the later deposited titanium to form a very thin TiN interface. We have never observed peeling of a TiN film in direct contact with FSG.

Whatever hydrogen is in the plasma produces very reactive ions which attach themselves to free fluorine on the FSG surface. Any resultant HF volatizes and is pumped from the system. The reduced fluorine concentration at the interface helps to stabilize the film and promotes good adhesion and integration with the rest of the layered structure.

It is noted that the hydrogen introduced during CMP differs in at least two ways from that introduced by a hydrogen plasma. In CMP (performed at atmospheric pressure), any HF produced is in the liquid phase and does not volatize. Also, CMP tends to drive the hydrogen deeply into the FSG.

Although a simultaneous H2/N2 plasma treatment is convenient, the H2 plasma treatment and N2 plasma treat could be separately performed. Also, it is understood that minor amounts of gases other than H2 and N2 may be included in the treatment gas without major effects on the chemistry, for example, to less than 20%, preferably less than 10%.

In step 66, the wafer may optionally be subjected to a conventional argon preclean plasma prior to sputtering. The plasma pre-clean 66 is intended to remove all impurities and possibly surface defects from the underlayer prior to its being coated with sputtered material. The need for an argon pre-clean is partially eliminated because the H2/N2 plasma is also pre-cleaning. However, the aluminum wiring at the bottom of the via hole in the lower wiring level is also exposed to nitrogen plasma, and the aluminum may be nitrided into aluminum nitride, which is a tough, electrically resistive material. The argon plasma removes the aluminum nitride as well as any aluminum oxide remaining from the etching and wafer transfer. The argon preclean sputtering also removes the top layers of the FSG that have been most affected by the CMP processing, for example, by absorbing moisture.

In step 68, a titanium adhesion layer is deposited, and in step 70 the titanium nitride barrier layer is deposited. Sometimes, a gradated TiNx transition layer is formed between the Ti and TiN. Different forms of CVD and sputtering have been suggested for depositing these two layers. However, it is recommended that the titanium layer be sputter deposited by ion metal plating (IMP), which involves sputtering in a high density plasma. Such an IMP sputter reactor is available from Applied Materials. It is further recommended that the titanium nitride layer be deposited in a thermal CVD process using TDMAT as the precursor gas. CVD is recommended for depositing the TiN because the previous Ti deposition has further increased the aspect ratio of the via hole. The CVD process may be performed in the Endura 5500 CVD TxZ TiN reactor, also available from Applied Materials. Aluminum metal is filled into the lined hole in step 72. The metal material and its deposition method are not the direct subject of this invention. Further, the process is not limited to aluminum, and may be used for tungsten, copper, other metals, and alloys of various metals. Sputtering of aluminum continues to be important and may involve multiple deposition steps with possible annealing. Tungsten plugs are often deposited for contacting underlying silicon. Electroplating is the preferred method for filling copper. In step 74, the wafer is cooled down from the relatively high temperatures used in sputtering aluminum and returned to the cassette.

The invention may also be advantageously applied to copper metallization, particularly using the dual-damascene structure generally illustrated in FIG. 4. The copper process, illustrated in the flow diagram of FIG. 6, resembles the aluminum process of FIG. 5 but with some differences.

A photolithography step 80 is more complex and involves two steps of photolithography to form the vias and the trench. Typically no dielectric CMP is performed before the photolithography step 80.

A barrier/liner sequence 82 is performed in an integrated processing tool and includes the previously described step 62 for orienting and degassing and the hydrogen/nitrogen plasma surface treatment step 64 for treating all exposed FSG surfaces including sidewalls of both the via holes and trenches. The argon plasma pre-cleaning step 66 is no longer so necessary since no aluminum nitride is forming. However, copper forms many phases of unstable residues, and nitrogen-based residues should be removed. The preferred liner layer for copper is a Ta TaN bilayer. In step 84, the Ta sublayer is deposited preferably by a high-density plasma sputtering or other form of ionized metal plating (IMP), and in step 86 the TaN sublayer is deposited by PVD.

After cool down in step 74, the cassette of wafers is transferred to an integrated copper filling tool for an integrated copper fill step 90. In step 92, a thin copper seed layer is deposited by semi-ionized metal plating (SIMP) or other process capable of coating copper onto silica sidewalls deep within a high aspect-ratio hole. SIMP is a specialized form of DC magnetron sputtering using various techniques to increase the ionization density of the copper ions without the need for an HDP sputter reactor. The process is described by Chiang et al. in U.S. Patent Application 09/414,614, filed October 8, 1999, by Fu et al. in U.S. Patent Application 09/546,798, filed April 11, 2000, and by Gopalraja et al. in U.S. Patent Application 09/518,180 filed March 2, 2000. Alternatively, an inductively coupled HDP sputter reactor may be used. The thin copper layer serves as a nucleation layer and as an electrode for filling the via hole and trench with copper in a step 94 of electrochemical plating (ECP). The ECP step also deposits copper over the top of the FSG layer. A step 96 of chemical mechanical polishing CMP step removes the copper and Ta/TaN liner layer exposed at the top of the wafer outside of the trenches until the harder FSG is encountered.

Thereby, the copper is isolated within the trenches forming the horizontal interconnects. Similarly to the dielectric CMP step 52 for the aluminum filling process of FIG. 6, the copper CMP step 96 attacks the FSG layer on which it stops.

The nitriding of the FSG layer has been observed to prevent the delamination of TaN having 35% N. One technique for preventing delamination has been to use TaN with 40 to 45% N, which however disadvantageously increases the TaN resistivity. The liner and filling process sequence 60 for aluminum or the liner process sequence 82 for copper, as mentioned previously, is preferably performed in an integrated processing tool, such as the Endura 5500 available from Applied Materials. An advantage of the process of the invention is that conventional reactors may be easily modified and integrated onto the Endura for the addition H2/N2 plasma treatment step.

The plasma surface pretreatment can be performed in a simple modification of a plasma reactor typically used for the argon preclean, such as the PCIJ preclean reactor available from Applied Materials and integrable onto the Endura 5500 platform. The PCI! is a domed inductively coupled plasma reactor that is plumbed with argon for precleaning. For use to pretreat the surface, the PCJJ needs to be plumbed with gas lines for H2 and N2 or, if forming gas is used, with a single H2/N2 line. It is possible to use the PCIJ for both sequential steps of pretreating and precleaning, in which case the gas supply is changed between the two steps. A typical pretreatment recipe for pretreating in the PCU is a chamber pressure of up to 50 or 80 milliTorr of H2/N2, 100 to 500W of 400kHz power applied to the coil, 100 to 500W of 13.56MHz power applied to the pedestal electrode supporting the wafer and creating a wafer self-bias of -100 to -500VDC, and generally room temperature operation. Another chamber that can be easily adapted to pretreating is the previously described TxZ reactor, which was originally designed for PECVD of TiN. The TxZ is designed to operate at higher temperatures and pressures, if desired, thus providing a wider process window. It is designed for use with many gas lines and includes safety features allowing the use of hydrogen fractions up to pure hydrogen. Zhao et al. have described such a chamber in U.S. Patents 5,558,717 and 5,846,332.

A typical recipe for pretreating FSG in the TxZ chamber includes a floating pedestal electrode, a pedestal temperature of 360 to 370°C, 750W of 450kHz power applied to the showerhead electrode, a chamber pressure of 1.3 Torr, a hydrogen flow of 225sccm and a nitrogen flow of 150sccm. The high temperature quoted above is derived from the TDMAT recipe for CVD and is not necessary for the surface pretreatment. Temperatures of less than 300°C can be used. The processes described above for either the PCU preclean chamber or the TxZ chamber are characterized by their relatively low power, no more than 1000W for a 200mm wafer and only 500W for the plasma source power, and temperatures of less than 400°C, preferably less than 300°C. Powers generally scale with the area of the substrate. The treatment need nitride only the small depth of the FSG layer which would likely interact with the after deposited liner layer, approximately 1 Ohm. The use of lower power reduces the possibility of damage and dielectric charging and allows the use of less expensive lower-power chambers.

The process illustrated in FIG. 5 has been experimentally tested. It has been shown to be effective at preventing peeling of the tungsten film from the planar FSG surface and of preventing voids between the tungsten and the side walls of the vias. Although the Ti/TiN or Ta/TaN barrier/liner is preferably deposited by a combination of sputtering and CVD, the invention is not so limited. Depositing the entire liner by either sputtering or CVD is known. Also, the multi-layer liner may have a somewhat more complicated stack structure, other barrier/liner materials have been suggested.

Although gaseous nitrogen N2 is the preferred gas for the plasma treatment, nitrous oxide (N2O) and ammonia (NH3) are widely used in plasma treatments, and should provide at least some of the benefits of the invention.

Thus, the invention uses conventional plasma reactors and processing gases to over a problem associated with process of low-k dielectric materials in advanced structures.

Claims

What is claimed is:
1. A process for treating a surface of a halogenated silicate glass including a hole extending downwardly from a generally planar top of said glass, said process comprising subjecting said surface including said hole to a plasma excited from a processing gas comprising a nitrogen containing treatment gas.
2. The process of Claim 1, wherein said treatment gas consists essentially of nitrogen gas.
3. The process of Claim 1, wherein said treatment gas comprises nitrogen gas.
4. The process of Claim 3, where said treatment gas additionally comprises hydrogen gas.
5. The process of Claim 4, wherein said wherein said treatment gas contains no more than 7% hydrogen gas.
6. The process of Claim 5, wherein said treatment gas contains at least 5% hydrogen gas.
7. The process of Claim 1, wherein said halogenated silicate glass is a fluorosilicate glass containing between 6 and 13 at% fluorine.
8. The process of Claim 1, wherein said plasma is excited with no more than 1000W of power normalized to a 200mm wafer.
9. The process of Claim 8, wherein said plasma is excited with a plasma source power of no more than 500W normalized to a 200mm wafer.
10 The process of Claim 8, wherein said substrate is maintained at a temperature of less than 400°C.
11. The process of Claim 10, wherein said temperature is less than 300°C.
12. The process of Claim 1, further comprising a preceding step of chemical mechanical polishing said halogenated silicate glass.
13. A process for treating a surface of a fluorinated silicate glass formed on a substrate, comprising the steps of: injecting a treatment gas comprising gaseous nitrogen into a plasma processing chamber; exciting said treatment gas into a plasma with no more than 1000W or power normalized to said substrate being a 200mm wafer; maintaining a temperature of said substrate contained in said chamber to less than 300°C; and subjecting said surface to said plasma.
14. The process of Claim 13, wherein said treatment gas additionally comprises gaseous hydrogen.
15. The process of Claim 13, wherein said fluorinated silicate glass contains between 6 and 13 at% fluorine.
16. The process of Claim 13, further comprising a preceding step of chemical mechanically polishing said surface.
17. The process of Claim 13, further comprising a subsequent step of subjecting said surface to a plasma of a gas principally comprising argon.
18. A process of treating a halogenated silicate glass formed in a substrate, comprising the steps of: a first step of subjecting a surface of said glass to a first plasma of a first gas comprising a nitrogen-containing treatment gas; and a subsequent second step of subjecting said surface to a second plasma of a second gas comprising argon.
19. The process of Claim 18, wherein said second step further subjects a metal surface formed in said substrate to said second plasma, thereby removing a metal nitride formed in said first step from said metal surface.
20. The process of Claim 18, wherein said halogenated silicate glass contains between 6 and 13 at% fluorine.
21. The process of Claim 18, further comprising a subsequent step depositing a barrier/liner layer over said halogenated silicate glass.
22. The process of Claim 18, wherein said barrier/liner layer comprises titanium and nitrogen.
23. The process of Claim 22, further comprising the subsequent step of sputter depositing an aluminum layer.
24. The process of Claim 18, wherein said barrier/liner layer comprises tantalum and nitrogen.
25. The process of Claim 24, further comprising the subsequent step of depositing copper by electrochemical plating.
26. The process of Claim 18, further comprising a step performed prior to first step of mechanically polishing said surface of said glass.
27. The process of Claim 18, wherein said treatment gas comprises gaseous nitrogen.
28. The process of Claim 27, wherein said treatment gas additionally comprises gaseous hydrogen.
29. A method of treating a surface of a fluorosilicate glass comprising between 6 and 13 at% fluorine exposed on a surface of a substrate and including a hole formed therein having an aspect ratio of at least 1:1, comprising a sequence of steps performed in a vacuum controlled integrated processing tool of: a first step of subjecting said surface to a first plasma consisting essentially of a nitrogen-containing treatment gas; and a subsequent second step of said surface to a second plasma of a second gas consisting essentially of argon; and depositing a liner layer into said hole.
30. The method of Claim 29, wherein said treatment gas comprises gaseous nitrogen.
31. The method of Claim 30, wherein said treatment gas consists essentially of gaseous nitrogen.
32. The method of Claim 30, wherein said treatment gas additionally comprises gaseous hydrogen.
33. The method of Claim 29, further comprising a step performed in said vacuum controlled integrated processing tool of sputter depositing aluminum metallization into said hole.
34. The method of Claim 33, wherein said liner layer comprises titanium and nitrogen.
35. The method of Claim 29, further comprising a step of electrochemically plating copper into said hole.
36. The method of Claim 35, wherein said liner layer comprises tantalum and nitrogen.
PCT/US2001/024177 2000-08-04 2001-07-31 Stabilized surface between a fluorosilicate glass dielectric and a liner/barrier layer WO2002013234A3 (en)

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