CN101661897B - Interconnector structure and manufacturing method thereof - Google Patents
Interconnector structure and manufacturing method thereof Download PDFInfo
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- CN101661897B CN101661897B CN2008100421024A CN200810042102A CN101661897B CN 101661897 B CN101661897 B CN 101661897B CN 2008100421024 A CN2008100421024 A CN 2008100421024A CN 200810042102 A CN200810042102 A CN 200810042102A CN 101661897 B CN101661897 B CN 101661897B
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Abstract
The invention discloses an interconnector structure and a manufacturing method thereof. The manufacturing method comprises the following steps: firstly, providing a substrate, and forming a first dielectric layer with an opening on the substrate; secondly, forming a conductor layer in the opening, wherein the top surface height of the conductor layer is lower than that of the first dielectric layer; thirdly, forming a first blocking layer on the first dielectric layer and the conductor layer, wherein the first blocking layer filling in the substrate, and forming a metal layer on the first blocking layer; and fourthly, patterning the metal layer and the first blocking layer. The first blocking layer can be used as a sealing structure on the conductor layer to prevent the conductor layer from being eroded during subsequent processing procedures.
Description
Technical field
The invention relates to a kind of structure and manufacturing approach thereof of integrated circuit, and particularly relevant for a kind of structure and manufacturing approach thereof of intraconnections.
Background technology
Along with the lasting progress of semiconductor fabrication, the element live width is able to continue to dwindle.The dwindling of live width then help high speed, multi-functional, high element integrated level, low power consumption and cheaply the great scale integrated circuit chip be able to a large amount of manufacturings.
Because the microminiaturization of semiconductor element and the increase of integrated level make limited chip surface can't hold the intraconnections (interconnection) of increase day by day.In order to solve this problem, multi-metal intra-connection structure just is suggested, and becomes the mode that ic manufacturing technology has to adopt.The general employed multi-metal intra-connection structure of integrated circuit is made up of plain conductor and interlayer hole or contact hole.Internal connection-wire structure is configured among the multilayer dielectric layer, by the plain conductor or the semiconductor element that are formed on each layer plane of tungsten plug connection in interlayer hole opening or the contact window.
With an interlayer hole tungsten plug is example, and Figure 1A to Figure 1B is the profile that illustrates traditional a kind of metal interconnecting structure.With reference to Figure 1A, the dielectric layer 140 that has been formed with plain conductor 120 in the substrate 100 and has covered plain conductor 120.Afterwards, in dielectric layer 140, form opening, and in opening, form tungsten plug 150 through patterning method.Then, deposition resistance barrier material layer and metal material layer on dielectric layer 140, and on metal material layer, form patterning photoresist layer 170.With patterning photoresist layer 170 is mask, and etching metal material layer and resistance barrier material layer are to form plain conductor 160 and barrier layer 162.
Afterwards, please with reference to Figure 1B, (ashing) removes patterning photoresist layer 170 with the oxygen plasma ashing.Generally speaking, after carrying out etch process, can carry out manufacturing process for cleaning,, avoid successive process is caused harmful effect to remove the particulate or the impurity of remained on surface.But the problem of tungsten corrosion during the top that causes pattern and misalignment tungsten plug 150 (shown in Figure 1A), will take place in aligning (mis-alignment) or other reason if micro-photographing process makes a mistake in follow-up manufacturing process for cleaning.In detail, because plain conductor 160 can't cover tungsten plug 150 with barrier layer 162 fully, the tungsten plug 150 that is exposed out can react with the solvent that is used for manufacturing process for cleaning, causes tungsten plug 150 losses and forms hole 158, shown in Figure 1B.Because the tungsten plug 150 that is corroded reduces with the contact area of upper/lower layer metallic lead 120,160, make the resistance in loop increase, can cause the circuit element dysfunction.Person very, whole tungsten plug 150 is all washed in a pan empty and is formed and open circuit, and causes circuit element to lose efficacy.
Except micro-photographing process makes a mistake to causing the tungsten plug corrosion on time; When the live width of element was dwindled, conductor layer can't be aimed at the tungsten plug of its below sometimes fully, in the hope of dwindling design area; Tungsten plug corrosion this moment is with unavoidable, and the necessity that addresses the above problem also just promotes greatly.
Summary of the invention
The present invention provides a kind of manufacturing approach of intraconnections, can avoid conductor layer to be corroded.
The present invention provides a kind of internal connection-wire structure in addition, can effectively protect the connector that is positioned at the below, barrier layer.
The present invention proposes a kind of manufacturing approach of intraconnections.Substrate is provided earlier, in substrate, forms first dielectric layer again with opening.Then, in opening, form conductor layer, and make the apical side height of conductor layer be lower than the apical side height of first dielectric layer.Afterwards, on first dielectric layer and conductor layer, form first barrier layer, wherein opening is filled up on first barrier layer, on first barrier layer, forms metal level again.Then, the patterned metal layer and first barrier layer.
In an embodiment of the present invention, on be set forth in the opening method that forms conductor layer and comprise prior to forming the conductor material layer that fills up opening on first dielectric layer, then remove the conductor material layer beyond the opening, remove the conductor material layer of part in the opening afterwards again.
In an embodiment of the present invention, the above-mentioned method that removes conductor material layer comprises cmp.
In an embodiment of the present invention, the method on above-mentioned formation first barrier layer comprises deposition-etching-sedimentation.
In an embodiment of the present invention, plain conductor or semiconductor element have been formed with in the above-mentioned substrate.
In another embodiment of the present invention, above-mentioned opening exposes plain conductor or semiconductor element.
In an embodiment of the present invention, the manufacturing approach of intraconnections also is included in after this metal level of patterning and this first barrier layer, in substrate, forms second dielectric layer, and in second dielectric layer, forms connector.
In an embodiment of the present invention, the manufacturing approach of intraconnections also is included in and forms before the conductor layer, forms second barrier layer in the surface of opening.
In an embodiment of the present invention, the apical side height disparity range of the end face of above-mentioned conductor layer and dielectric layer is between 20 nanometer to 60 nanometers.
In an embodiment of the present invention, the material of above-mentioned conductor layer comprises tungsten.
In an embodiment of the present invention, the material on above-mentioned first barrier layer comprises titanium and titanium nitride.
The present invention proposes a kind of internal connection-wire structure in addition, and it comprises dielectric layer, conductor layer, first barrier layer and metal level.Dielectric layer is disposed in the substrate, and this dielectric layer has opening.Conductor layer is arranged in the opening of dielectric layer, and the apical side height of conductor layer is lower than the apical side height of dielectric layer.First barrier layer is disposed on dielectric layer and the conductor layer, and wherein opening is filled up on first barrier layer.And metal level is disposed on first barrier layer.
In an embodiment of the present invention, dispose plain conductor or semiconductor element in the above-mentioned substrate.
In an embodiment of the present invention, above-mentioned opening exposes plain conductor or semiconductor element.
In an embodiment of the present invention, the apical side height disparity range of the end face of above-mentioned conductor layer and dielectric layer is between 20 nanometer to 60 nanometers.
In an embodiment of the present invention, above-mentioned internal connection-wire structure also comprises second barrier layer, is disposed between dielectric layer and the conductor layer.
In an embodiment of the present invention, the material of above-mentioned conductor layer comprises tungsten.
In an embodiment of the present invention, the material on above-mentioned first barrier layer comprises titanium and titanium nitride.
Internal connection-wire structure of the present invention and manufacturing approach thereof reach the effect of protection conductor layer through making first barrier layer as the design of Sealing Structure on the conductor layer, therefore can avoid conductor layer in successive process, to be corroded.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts preferred embodiment, and conjunction with figs., elaborates as follows.
Description of drawings
Figure 1A to 1B is the sketch map of traditional a kind of internal connection-wire structure.
Fig. 2 is the sketch map according to a kind of internal connection-wire structure of one embodiment of the invention.
Fig. 3 is the schematic flow sheet according to the manufacturing approach of a kind of intraconnections of one embodiment of the invention.
Fig. 4 A to 4E is the generalized section according to the manufacturing approach of a kind of intraconnections of one embodiment of the invention.
Embodiment
Following examples are to be that example is explained internal connection-wire structure of the present invention with the interlayer hole connector, but not as limit, and the present invention can also be applied to various intraconnections.Fig. 2 is the generalized section of the internal connection-wire structure of one embodiment of the invention.As shown in Figure 2, this internal connection-wire structure comprises substrate 200, plain conductor 220, dielectric layer 240, conductor layer 250, barrier layer 256, barrier layer 262, plain conductor 260, dielectric layer 280 and conductor layer 290.
And dielectric layer 240 has opening 242, and opening 242 for example is the top that is disposed at plain conductor 220.Surface configuration at opening 242 has barrier layer 256.The material on barrier layer 256 for example is titanium and titanium nitride.Conductor layer 250 is arranged in the opening 242 of dielectric layer 240.In addition, the apical side height of conductor layer 250 is lower than the apical side height of dielectric layer 240.The material of conductor layer 250 for example is a tungsten.
What specify is, the conductor layer 250 in the present embodiment is an interlayer hole connector, in order to connect the plain conductor 220 and the plain conductor 260 of last layer more.Conductor layer 250 for example is the opening 242 that fills up jointly in the dielectric layer 240 with the part barrier layer 262 of conductor layer 250 tops.Because the barrier layer 262 that is configured in conductor layer 250 tops has thicker thickness, so barrier layer 262 can be used as the hermetically-sealed construction of interlayer hole connector, and prevents that effectively conductor layer 250 from corroding loss in manufacturing process for cleaning.
In another embodiment, the opening 242 of dielectric layer 240 also can be the top (not being illustrated among the figure) that is disposed at semiconductor element.That is to say that the conductor layer 250 that is formed in the opening 242 is as the contact hole connector, and electrically connect the semiconductor element on substrate 200 surfaces and the plain conductor 260 on upper strata.
Internal connection-wire structure of the present invention more than has been described, next the manufacturing approach of this internal connection-wire structure will be described.Fig. 3 is the schematic flow sheet of the intraconnections manufacturing approach of one embodiment of the invention.And the generalized section of the intraconnections manufacturing approach of Fig. 4 A to Fig. 4 E one embodiment of the invention.
At first, with reference to Fig. 3 step 302 and Fig. 4 A, substrate 400 is provided.Substrate 400 for example is the semiconductor-based end, like N type silicon base, P type silicon base, three or five families semiconductor-based end etc.For example the semiconductor element (not illustrating) that has been formed with conduction region (not illustrating) or has generally known in the substrate 400.In one embodiment, the surface of substrate 400 has been formed with plain conductor 420 (shown in Fig. 4 A).
Afterwards, with reference to Fig. 3 step 304 and Fig. 4 A, on substrate 400 surfaces, form dielectric layer 440, and dielectric layer 440 covers plain conductor 420.The material of dielectric layer 440 for example silica (SiO), silicon nitride (SiN), silicon oxynitride (SiON), phosphorosilicate glass (PSG), boron-phosphorosilicate glass (BPSG), non-impurity-doped silex glass (USG), fluorine doped silicon glass (FSG) or dielectric constant is lower than 4 low-k (low-k) dielectric material.The production method of dielectric layer 440 for example be aumospheric pressure cvd (atmospheric CVD), low-pressure chemical vapor deposition (low pressure CVD), PCVD (plasma-enhanced CVD, PECVD) or high density plasma chemical vapor deposition method (high density plasma CVD) etc.Then, in dielectric layer 440, form opening 452 with patterning method, shown in Fig. 4 A.452 of openings for example are to expose plain conductor 420, with as the interlayer hole opening.
What specify is, in another embodiment, the opening 452 in the dielectric layer 440 also can be to be formed at the top of semiconductor element and to expose the semiconductor element (not being illustrated among the figure) in the substrate 400, with the usefulness as contact window.
Please with reference to Fig. 4 B; In one embodiment; Optionally on opening 452 surfaces, form barrier layer 456, so that comparatively excellent contact interface of a conductivity, physical attachment property to be provided, and dielectric medium or the semiconductor of the conductor metal that prevents follow-up formation around diffusing into.The material on this barrier layer 456 comprises titanium, titanizing nitrogen or titanium-tungsten, and manufacturing approach then comprises for example direct current plasma sputter (DC plasma sputtering deposition), nitrogenize (nitridation) and reactive sputter methods such as (reactive sputtering deposition).
Afterwards, in substrate 400, form one deck conductor material layer.Conductor material layer for example is to cover dielectric layer 440 and fill up opening 452.The material of this conductor material layer for example is a tungsten; The method that forms the tungsten conductor material layer then for example is chemical vapour deposition (CVD); Wherein more comprise and be used alternatingly different chemical gaseous phase depositing process; For example Si reduction (silicon reduction), hydrogen reduction (hydrogen reduction) or silicomethane reduction (Silane reduction) fills up really opening 452 to obtain preferable gap (gap filling) ability of filling, and avoids producing hole (void).The conductor material layer of just having accomplished at the thickness range on the dielectric layer 440 between 300 nanometer to 750 nanometers.
Then, remove the conductor material layer of position, and further remove the conductor material layer of a part of position in above-mentioned opening 452 again, and form conductor layer 450 and the depressed part 454 (shown in Fig. 4 B) that is positioned at conductor layer 450 tops on dielectric layer 440 surfaces.By the formed conductor layer 450 of remaining conductor material layer, its apical side height can be lower than the apical side height of dielectric layer 440, is the step 306 among Fig. 3.The degree of depth 466 of depressed part 454 is approximately in the scope between the 20nm to 60nm.
The above-mentioned method that removes conductor material layer for example cmp (chemical mechanical polishing, CMP) or eat-back method (etch back).In one embodiment, remove the conductor material layer that upper strata blanket shape covers (blanket) with cmp earlier, feasible remaining conductor material layer apical side height and dielectric layer 440 end faces height such as grade or the approaching height such as grade that is positioned at opening 452.Then carry out overmastication (over-polish), optionally remove conductor material layer and stay dielectric medium, to form depressed part 454 and conductor layer 450.And above-mentioned another kind removes the method for conductor material layer is the method for eat-backing.The method of eat-backing is with the mode of dry ecthing (dry etching), does not use patterning method, and direct etching removes the material of substrate surface.The method of eat-backing at first from top to bottom removes conductor material layer so that expose dielectric layer 440 surfaces, and then carrying out over etching (over-etch) again removes the segment conductor material layer in the opening 452, to form depressed part 454.Need the control operation condition when carrying out the over etching step, stay dielectric medium as far as possible with selective removal tungsten conductor material.The operating time of over etching step or other operating parameter can be regulated and control the degree of depth 466 of depressed part 454.
Then, with reference to Fig. 3 step 308 and Fig. 4 C, in substrate 400, form barrier layer 462.Barrier layer 462 for example is to cover dielectric layer 440 and conductor layer 450, that is the depressed part 454 of conductor layer 450 tops can be inserted in barrier layer 462.The thickness 468 of barrier layer 462 on first dielectric layer 440 is approximately in the scope between the 30nm to 100nm.Barrier layer 462 can be in order to improving dielectric medium or tungsten conductive surface adhesive force or the conductivity to other materials, and prevent dielectric medium or the semiconductor of conductor metal around diffusing into.The material on above-mentioned barrier layer 462 for example is titanium, titanium nitride or titanium-tungsten.The method that forms barrier layer 462 then for example is physical vaporous deposition or chemical vapour deposition technique.In one embodiment; The composite bed that barrier layer 462 is made up of titanium layer and titanium nitride layer; Its manufacturing approach is that elder generation uses the direct current plasma sputter to form the titanium layer of bottom, makes the surface formation titanium nitride layer of titanium layer or forms it with reactive sputter in the surperficial directly titanium nitride layer of titanium layer with nitrogenize again.In the process that forms barrier layer 462, (deposition-etchback-deposition dep-etch-dep) promotes the gradient coating performance that resistance hinders material can also optionally to use deposition-etching-sedimentation.That is to say; Use argon ion sputtering etching and resistance barrier material to deposit the mode of interactive operation; With overhang (overhang) that forms in the elimination deposition process, and have (step coverage) ability of ladder covering preferably, and barrier layer 462 is filled in the depressed part 454 really; And keep and have an even surface, and do not need extra planarization.
Afterwards, with reference to Fig. 3 step 310 and Fig. 4 D, on barrier layer 462, form metal level (not illustrating).The material of metal level for example is aluminium, copper, aluminium copper or Al-Si-Cu alloy etc.The manufacture method of above-mentioned metal level for example be chemical vapour deposition (CVD) or physical vapour deposition (PVD) (physical vapor deposition, PVD) etc.Wherein, physical vapour deposition (PVD) then for example is vapor deposition (evaporation) or sputter (sputtering).
Then,, metal level and barrier layer 462 are together carried out patterning, and form plain conductor 460 and barrier layer 462a with reference to Fig. 3 step 312 and Fig. 4 D.This patterning process for example forms patterning photoresist layer 470 on metal level, be that mask carries out etch process and removes part metals layer and barrier layer 462 with patterning photoresist layer 470 then.In addition, before forming patterning photoresist layer 470, optionally form the barc layer, be beneficial to control the carrying out of micro-photographing process in layer on surface of metal.
In one embodiment, the aligning if the patterning process makes a mistake can cause the configuration of plain conductor 460 not to be covered in fully on the conductor layer 450, with reference to Fig. 4 D.Because etch process can be controlled etching and stop at dielectric layer 440 surfaces,, make conductor layer 450 can not be exposed out, and reach the effect of sealing (seal) conductor layer 450 so the part barrier layer 462a of position on conductor layer 450 still is able to keep.
Please, behind patterning process, remove the patterning photoresist layer 470 on plain conductor 460 with reference to Fig. 4 E.The method that removes patterning photoresist layer 470 for example is to adopt oxygen plasma ashing processing procedure.Then, carry out manufacturing process for cleaning, to remove the particulate or the impurity of remained on surface.The employed solvent of manufacturing process for cleaning can be acid or alkaline, has visual its demand of common knowledge the knowledgeable and adjusts in this technical field.When carrying out manufacturing process for cleaning; Because the barrier layer 462a of conductor layer 450 tops has thicker thickness; Conductor layer 450 is not exposed out, and the material of barrier layer 462a can't react with the solvent that cleans usefulness, so the problem that can avoid conductor layer 450 to be corroded.
And in one embodiment, with reference to Fig. 4 E, form after the plain conductor 460, more can in substrate 400, form dielectric layer 480.Then, in dielectric layer 480, form interlayer hole opening (not illustrating) with patterning method again.The interlayer hole opening for example is to expose plain conductor 460.In above-mentioned patterned etch process, need the good etching selectivity of control and be unlikely to destroy or part that eating thrown barrier layer 462a is exposed.What deserves to be mentioned is; In the process of carrying out patterning; The situation of aiming at and make that the interlayer hole opening is not to be formed entirely on the plain conductor 460 even make a mistake; Because conductor layer 450 tops are formed with the thicker barrier layer 462a of thickness, so the interlayer hole opening can't expose conductor layer 450.After the removing photoresistance processing, then carry out the wet-cleaned processing procedure again, this moment, employed cleaning solvent also can not contact conductor layer 450, and can avoid corrosion by this protection conductor layer 450.Afterwards, in the interlayer hole opening of dielectric layer 480, form conductor layer 490, with as connector.The material of conductor layer 490 for example is a tungsten.
In addition, be to be that example describes in the above-described embodiments with the metal plug that forms in the internal connection-wire structure, right the present invention is not limited to this.Structure of the present invention and method can also be applied in opening, to insert conductor layer and on conductor layer, form any processing procedure on barrier layer, know those skilled in the art when knowing its application and variation according to previous embodiment, so repeat no more in this.
In sum, internal connection-wire structure of the present invention and manufacturing approach thereof as the design of Sealing Structure on the conductor layer, reach the effect of protection conductor layer through the barrier layer.This internal connection-wire structure and manufacturing approach thereof can make conductor material can in the cleaning after metal etch or the interlayer etching, not be corroded, and avoid microelectronic element property abnormality or inefficacy.
In addition, intraconnections manufacturing approach of the present invention only need be omited the inching conventional process, can accomplish the internal connection-wire structure that is designed, and the processing procedure change is easy, and need not import additional apparatus.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is when being as the criterion with what claim defined.
Claims (18)
1. the manufacturing approach of an intraconnections comprises:
One substrate is provided;
In this substrate, form one first dielectric layer with an opening;
In this opening, form a conductor layer, the apical side height of this conductor layer is lower than the apical side height of this first dielectric layer;
On this first dielectric layer and this conductor layer, form one first barrier layer, wherein this opening is filled up on this first barrier layer;
On this first barrier layer, form a metal level; And
This metal level of patterning and this first barrier layer.
2. the manufacturing approach of intraconnections as claimed in claim 1 is characterized in that, the method that in this opening, forms this conductor layer comprises:
On this first dielectric layer, form a conductor material layer, and this conductor material layer fills up this opening;
Remove this conductor material layer beyond this opening; And
Remove this conductor material layer of part in this opening.
3. the manufacturing approach of intraconnections as claimed in claim 2 is characterized in that, the method that removes this conductor material layer comprises cmp.
4. the manufacturing approach of intraconnections as claimed in claim 1 is characterized in that, the method that forms this first barrier layer comprises deposition-etching-sedimentation.
5. the manufacturing approach of intraconnections as claimed in claim 1 is characterized in that, has been formed with a plain conductor or semiconductor element in this substrate.
6. the manufacturing approach of intraconnections as claimed in claim 5 is characterized in that, this opening exposes this plain conductor or this semiconductor element.
7. the manufacturing approach of intraconnections as claimed in claim 1 is characterized in that, after this metal level of patterning and this first barrier layer, also comprises:
In this substrate, form one second dielectric layer; And
In this second dielectric layer, form a connector.
8. the manufacturing approach of intraconnections as claimed in claim 1 is characterized in that, also is included in to form before this conductor layer, forms one second barrier layer in the surface of this opening.
9. the manufacturing approach of intraconnections as claimed in claim 1 is characterized in that, the apical side height disparity range of the end face of this conductor layer and this dielectric layer is between 20 nanometer to 60 nanometers.
10. the manufacturing approach of intraconnections as claimed in claim 1 is characterized in that, the material of this conductor layer comprises tungsten.
11. the manufacturing approach of intraconnections as claimed in claim 1 is characterized in that, the material on this first barrier layer comprises titanium and titanium nitride.
12. an internal connection-wire structure comprises:
One dielectric layer is disposed in the substrate, and this dielectric layer has an opening;
One conductor layer is disposed in this opening, and the apical side height of this conductor layer is lower than the apical side height of this dielectric layer;
One first barrier layer is disposed on this dielectric layer and this conductor layer, and wherein this opening is filled up on this first barrier layer; And
One metal level is disposed on this first barrier layer.
13. internal connection-wire structure as claimed in claim 12 is characterized in that, disposes a plain conductor or semiconductor element in this substrate.
14. internal connection-wire structure as claimed in claim 13 is characterized in that, this opening exposes this plain conductor or this semiconductor element.
15. internal connection-wire structure as claimed in claim 12 is characterized in that, the apical side height disparity range of the end face of this conductor layer and this dielectric layer is between 20 nanometer to 60 nanometers.
16. internal connection-wire structure as claimed in claim 12 is characterized in that, also comprises one second barrier layer, is disposed between this dielectric layer and this conductor layer.
17. internal connection-wire structure as claimed in claim 12 is characterized in that, the material of this conductor layer comprises tungsten.
18. internal connection-wire structure as claimed in claim 12 is characterized in that, the material on this first barrier layer comprises titanium and titanium nitride.
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| CN2008100421024A CN101661897B (en) | 2008-08-27 | 2008-08-27 | Interconnector structure and manufacturing method thereof |
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| CN105609431B (en) * | 2014-10-28 | 2018-07-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| TWI701768B (en) * | 2019-08-28 | 2020-08-11 | 力晶積成電子製造股份有限公司 | Method of manufacturing interconnect structure |
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| US6235579B1 (en) * | 1999-10-18 | 2001-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for manufacturing stacked capacitor |
| CN1374690A (en) * | 2001-03-13 | 2002-10-16 | 世界先进积体电路股份有限公司 | Manufacture of double mosaic wire copper wire inside low layer |
| US20040127023A1 (en) * | 2002-12-30 | 2004-07-01 | Chun In Kyu | Method for forming a contact using a dual damascene process in semiconductor fabrication |
| CN1679161A (en) * | 2002-09-04 | 2005-10-05 | 皇家飞利浦电子股份有限公司 | Method for fabrication of in-laid metal interconnects |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6235579B1 (en) * | 1999-10-18 | 2001-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for manufacturing stacked capacitor |
| CN1374690A (en) * | 2001-03-13 | 2002-10-16 | 世界先进积体电路股份有限公司 | Manufacture of double mosaic wire copper wire inside low layer |
| CN1679161A (en) * | 2002-09-04 | 2005-10-05 | 皇家飞利浦电子股份有限公司 | Method for fabrication of in-laid metal interconnects |
| US20040127023A1 (en) * | 2002-12-30 | 2004-07-01 | Chun In Kyu | Method for forming a contact using a dual damascene process in semiconductor fabrication |
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Address after: 215123 333 Xinghua street, Suzhou Industrial Park, Jiangsu Patentee after: Warship chip manufacturing (Suzhou) Limited by Share Ltd Address before: 215025 Xinghua street, Suzhou Industrial Park, Suzhou, Jiangsu 333 Patentee before: Hejian Technology (Suzhou) Co., Ltd. |