CN1395299A - 半导体元件的硅化物膜的形成方法 - Google Patents
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Abstract
本发明提供半导体元件的硅化物膜的形成方法。本发明由以下步骤构成：在半导体衬底上部形成多晶硅层组成的栅电极；以及在其侧壁上形成间隔层，在栅电极的两侧衬底内注入杂质而形成源/漏区域后，在构成物的整个面上以整体淀积来淀积Ti层的一部分，在用Ar或N2气进行等离子体处理使产生内部缺陷，在淀积其余厚度的Ti层和TiN层后，实施热处理，在栅电极及源/漏区域上部形成Ti硅化物膜，从而即使栅电极的线宽度减小，本发明也可以获得稳定且电阻小的C54相的Ti硅化物膜。
Description
技术领域
本发明涉及半导体元件的制造方法，更详细地说，涉及在高集成半导体元件中形成均匀的电阻小的硅化物膜的半导体元件的制造方法。
背景技术
一般地，在半导体元件的制造工序中，为了减小半导体元件表面的表面电阻而进行硅化物工序。例如，为了减少MOS型晶体管的RC延迟时间，在晶体管的栅电极、源/漏区域的表面上追加硅化物膜。
应用于半导体元件的硅化物有具有代表性的钨硅化物(WSi2)、钛硅化物(TiSi2)、及钴硅化物(CoSi2)等。其中，钛硅化物(以下称为Ti硅化物)在高集成化产生的信号处理的速度改善方面被频繁地使用在结(junction)部位等。
下面参照附图说明现有技术的半导体元件的硅化物膜的制造方法。
图1至图3是依次示出现有技术的半导体元件的硅化物膜的制造方法的工序顺序图。
如图1所示，现有技术的半导体元件的硅化物膜的制造方法在硅衬底10上形成场氧化膜12来区分元件的有源区和非有源区。
然后，在硅衬底10的有源区中依次淀积栅氧化膜13和掺杂多晶硅层，对它进行构图来形成栅电极14。
接着，在衬底的源/漏区域中离子注入低浓度的杂质而形成LDD(LightlyDoped Drain：轻掺杂漏区)区域16后，在栅电极14的侧面用硅氧化膜(SiO2)或氮化硅膜(Si3N4)形成间隔层(spacer，18)。
然后，在形成了间隔层18的结果物中离子注入高浓度的杂质而形成源/漏区域20。
然后，如图2所示，在所述结果物的整个面上淀积作为金属的Ti层22和TiN层24后，实施作为热处理工序的RTP(Rapid Thermal Process：快速热处理)。
这样，如图3所示，通过所述RTP，栅电极14的上部和源/漏区域20的硅与Ti层22及TiN层24进行硅化物反应，在各自的表面上形成Ti硅化物膜(TiSix，26)。
接着，通过除去未发生硅化物反应的区域的Ti层22和TiN层24，使栅电极14和源/漏区域20的各Ti硅化物膜26a、26b不相互连结。
如上那样，现有技术通过栅电极14的上部的Ti硅化物膜26a和源/漏区域20表面的Ti硅化物膜26b，可以降低各自的表面电阻。由此，在与栅电极14、源/漏区域20接触的布线的制造工序时可降低接触电阻。
但是，根据半导体元件的高集成化的设计规则，在减少栅电极的线宽度的情况下，难以进行均匀的硅化物膜的制造。这是因为在不稳定的硅化物形态的C49相的相转移形成时，稳定的硅化物形态的C54相因栅电极线宽度的缩小而在C49中几乎没有C54的核生成的席位，在一个核生成的席位中粗大的C54相不均匀，形成不连续的Ti硅化物膜。
因此，现有技术的硅化物制造方法在元件的高集成化产生的设计限制下，栅电极的线宽度急剧地减少而形成不均匀的硅化物膜，所以在栅电极和源/漏区域中产生硅化物电阻的增加和漏泄电流，造成局部元件的不良。
发明内容
因此，本发明为了解决上述现有技术中的问题而研究出的发明，其目的在于提供一种半导体元件的硅化物膜的形成方法，该方法在后续热处理的工序时可以确保均匀的硅化物膜。
为了实现上述目的，本发明的半导体元件的硅化物膜的形成方法的特征在于包括：在半导体衬底的表面上淀积下部金属层后实施等离子体处理的步骤；以及在所述等离子体处理过的下部金属层上淀积上部金属层后实施热处理工序，在所述半导体衬底的表面上形成硅化物膜的步骤。
此外，本发明的半导体元件的硅化物膜的形成方法的特征在于包括：在半导体衬底的上部形成没有多晶硅层的栅电极的步骤；在所述栅电极的侧壁上形成用绝缘物质构成的间隔层的步骤；在所述栅电极的两侧的衬底内形成注入了杂质的源/漏区域的步骤；在所述构成物的整个面上淀积下部金属层后用Ar或N2气实施等离子体处理的步骤；以及在下部金属层的上部淀积上部金属层，实施热处理，除去不与硅反应的金属层，在栅电极及源/漏的上面形成硅化物膜的步骤。
以上的本发明的目的、其他特征及长处从参照以下对本发明的优选实施例的说明中将变得明确。
附图说明
图1是顺序示出现有技术的半导体元件的硅化物膜的制造方法的工序剖面图。
图2同样是顺序示出现有技术的半导体元件的硅化物膜的制造方法的工序剖面图。
图3同样是顺序示出现有技术的半导体元件的硅化物膜的制造方法的工序剖面图。
图4是顺序示出本发明的半导体元件的硅化物膜的制造方法的工序剖面图。
图5同样是顺序示出本发明的半导体元件的硅化物膜的制造方法的工序剖面图。
图6同样是顺序示出本发明的半导体元件的硅化物膜的制造方法的工序剖面图。
图7同样是顺序示出本发明的半导体元件的硅化物膜的制造方法的工序剖面图。
图8同样是顺序示出本发明的半导体元件的硅化物膜的制造方法的工序剖面图。
具体实施方式
以下，参照附图详细说明本发明的半导体元件的硅化物膜的形成方法的优选实施例。
图4至图8是顺序示出本发明的半导体元件的硅化物膜的形成方法的工序剖面图。
如图4所示，本发明的硅化物膜的形成方法，首先在硅衬底100上形成场氧化膜102而区分为元件的有源区和非有源区。
然后，在衬底100的有源区形成栅氧化膜103后，淀积掺杂多晶硅层，对它进行构图而形成栅电极104。
接着，在衬底的源/漏区域中离子注入低浓度的杂质，形成LDD区域106后，在栅电极104的侧面用硅氧化膜(SiO2)或氮化硅膜(Si2N4)形成间隔层108。
然后，在形成了间隔层108的产物中离子注入高浓度的杂质来形成源/漏区域110。
接着，如图5所示，在所述构成物的整个面上淀积作为下部金属层的Ti层112。此时，下部Ti层112的厚度必需淀积，为整体Ti层的一部分的50～200。
然后，在RF反应室中连续地放入Ar或N2气后，在等离子体状态下激励气体，注入到下部Ti层112。此时，Ar或N2气以10sccm～40sccm流动，反应室的温度维持在300℃～400℃，使Ar或N2成分扩散到下部Ti层112。这样等离子体处理过的下部Ti层112，因这些气体成分的侵入而产生内部缺陷。
通过这样的缺陷，在以后的硅化物工序时使稳定并且电阻小的C54相更多地核生成，可以获得均匀的硅化物膜。
接着，如图6所示，在下部Ti层112的上部再次淀积作为上部金属层114的Ti。此时，上部Ti层114必需整体淀积，Ti层的其余部分具有100～300的厚度。
然后，如图7所示，在上部Ti层114的上部淀积TiN层116后，实施RTP工序来产生硅化物反应。
接着，如图8所示，通过所述RTP，栅电极104的上部、源/漏区域100的硅、下/上部Ti层112、114及TiN层116进行硅化物反应，在各自的表面上形成Ti硅化物膜(TiSix，118)。
然后，通过除去未发生硅化物反应的区域的下/上部Ti层112、114及TiN层116，使栅电极104和源/漏区域110的各Ti硅化物膜118a、118b不相互连结。
更详细地说，在650℃～750℃下进行1次RTP来形成Ti硅化物膜(TiSix，118)。此时，通过在等离子体处理时有内部缺陷的下部Ti层112，可容易地形成初期不稳定的C49相而减小晶粒的尺寸。对这样的晶粒小的C49相的Ti硅化物膜118以750℃～850℃并再次用高温实施2次RTP。于是，在C49相多的晶粒边界使稳定且电阻小的C54相进行核生成，可均匀连续地形成C54相的Ti硅化物膜118。
发明的效果
如上所述，根据本发明的半导体元件的硅化物膜的形成方法，分2次淀积硅化物的Ti层，但通过在RF等离子体状态下激励Ar或N2气并注入到最初淀积过的Ti层，在后续的热处理工序时可以确保均匀的硅化物膜。
因此，在高集成的半导体元件中，即使栅电极的线宽度小，但本发明通过将稳定且电阻小的C54相的Ti硅化物膜均匀连续地在栅电极和源/漏区域中形成，可以提高半导体元件的电气特性及收率。
以上通过实施例详细说明了本发明，但本发明不限定于实施例，只要是具有本发明所属领域的普通知识的人员，在不脱离本发明的思想和精神的范围内，当然可以修正或变更本发明。
Claims (14)
1.一种半导体元件的硅化物膜的形成方法，其特征在于包括：
在半导体衬底的表面上淀积下部金属层后实施等离子体处理的步骤；以及
在所述等离子体处理过的下部金属层上淀积上部金属层后实施热处理工序，在所述半导体衬底的表面上形成硅化物膜的步骤。
2.如权利要求1所述的半导体元件的硅化物膜的形成方法，其特征在于，所述下部和上部金属层是Ti。
3.如权利要求1所述的半导体元件的硅化物膜的形成方法，其特征在于，所述下部金属层有50～200的厚度。
4.如权利要求1所述的半导体元件的硅化物膜的形成方法，其特征在于，所述上部金属层有100～300的厚度。
5.如权利要求1所述的半导体元件的硅化物膜的形成方法，其特征在于，所述等离子体处理是在向反应室中流动10～40sccm的Ar或N2气，使反应室的温度维持在300℃～400℃的状态下进行。
6.一种半导体元件的硅化物膜的形成方法，其特征在于，所述热处理由1次热处理和2次热处理构成。
7.如权利要求6所述的半导体元件的硅化物膜的形成方法，其特征在于，所述1次热处理温度为650℃～750℃，2次热处理温度为750℃～850℃。
8.如权利要求1所述的半导体元件的硅化物膜的形成方法，其特征在于，还包括在所述半导体衬底上形成源/漏区域和栅电极的步骤。
9.一种半导体元件的硅化物膜的形成方法，其特征在于包括：
在半导体衬底上形成栅电极的步骤；
在所述栅电极的侧壁上形成间隔层的步骤；
在所述栅电极的两侧的衬底内形成源/漏区域的步骤；
在所述构成物的整个面上淀积下部金属层后实施等离子体处理的步骤；以及
在所述等离子体处理过的下部金属层的上部淀积上部金属层，实施1次热处理和2次热处理工序，在所述栅电极及源/漏的上面形成硅化物膜的步骤。
10.如权利要求9所述的半导体元件的硅化物膜的形成方法，其特征在于，所述下部和上部金属层是Ti。
11.如权利要求9所述的半导体元件的硅化物膜的形成方法，其特征在于，所述下部金属层有50～200的厚度。
12.如权利要求9所述的半导体元件的硅化物膜的形成方法，其特征在于，所述上部金属层有100～300的厚度。
13.如权利要求9所述的半导体元件的硅化物膜的形成方法，其特征在于，所述等离子体处理是向反应室中流动10～40sccm的Ar或N2气，使反应室的温度维持在300℃～400℃的状态下进行。
14.如权利要求9所述的半导体元件的硅化物膜的形成方法，其特征在于，所述1次热处理温度为650℃～750℃，2次热处理温度为750℃～850℃。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR37355/01 | 2001-06-28 | ||
| KR10-2001-0037355A KR100395776B1 (ko) | 2001-06-28 | 2001-06-28 | 반도체 소자의 실리사이드막 제조 방법 |
| KR37355/2001 | 2001-06-28 |
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| Publication Number | Publication Date |
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| CN1395299A true CN1395299A (zh) | 2003-02-05 |
| CN1249794C CN1249794C (zh) | 2006-04-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB021272476A Expired - Fee Related CN1249794C (zh) | 2001-06-28 | 2002-06-28 | 半导体元件的硅化物膜的形成方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6800553B2 (zh) |
| JP (1) | JP3873008B2 (zh) |
| KR (1) | KR100395776B1 (zh) |
| CN (1) | CN1249794C (zh) |
| TW (1) | TW548747B (zh) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7923778B2 (en) | 2004-04-23 | 2011-04-12 | Semiconductor Energy Laboratory Co., Ltd. | Thin film integrated circuit and method for manufacturing the same, CPU, memory, electronic card and electronic device |
| CN103412423A (zh) * | 2013-08-27 | 2013-11-27 | 江西合力泰科技股份有限公司 | 一种低温印刷钛化硅的工艺 |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100982420B1 (ko) * | 2003-09-30 | 2010-09-15 | 삼성전자주식회사 | 실리사이드 박막을 갖는 반도체 소자 및 그 제조 방법 |
| KR100628225B1 (ko) | 2004-12-29 | 2006-09-26 | 동부일렉트로닉스 주식회사 | 반도체 소자의 제조방법 |
| JP2009049207A (ja) * | 2007-08-20 | 2009-03-05 | Spansion Llc | 半導体装置の製造方法 |
| US9174847B2 (en) | 2008-05-01 | 2015-11-03 | Honda Motor Co., Ltd. | Synthesis of high quality carbon single-walled nanotubes |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60193380A (ja) * | 1984-03-15 | 1985-10-01 | Nec Corp | 半導体装置の製造方法 |
| KR0164072B1 (ko) * | 1995-11-13 | 1999-02-01 | 김주용 | 반도체 소자의 얕은 접합 형성방법 |
| KR100224785B1 (ko) * | 1996-12-31 | 1999-10-15 | 김영환 | 반도체 소자의 트랜지스터 형성방법 |
| KR100231904B1 (ko) * | 1997-05-21 | 1999-12-01 | 윤종용 | Ti 실리사이드 제조방법 |
| KR100276388B1 (ko) | 1997-10-30 | 2001-01-15 | 윤종용 | 코발트/니오븀 이중 금속층 구조를 이용한 실리사이드 형성 방법 |
| US6110821A (en) * | 1998-01-27 | 2000-08-29 | Applied Materials, Inc. | Method for forming titanium silicide in situ |
| US6287966B1 (en) | 1999-05-03 | 2001-09-11 | Taiwan Semiconductor Manufacturing Company | Low sheet resistance of titanium salicide process |
| JP2001319893A (ja) * | 2000-05-11 | 2001-11-16 | Nec Corp | 半導体装置の製造方法 |
| US6727165B1 (en) * | 2001-09-28 | 2004-04-27 | Lsi Logic Corporation | Fabrication of metal contacts for deep-submicron technologies |
-
2001
- 2001-06-28 KR KR10-2001-0037355A patent/KR100395776B1/ko not_active IP Right Cessation
-
2002
- 2002-06-26 US US10/180,760 patent/US6800553B2/en not_active Expired - Lifetime
- 2002-06-27 JP JP2002187601A patent/JP3873008B2/ja not_active Expired - Fee Related
- 2002-06-28 TW TW091114456A patent/TW548747B/zh not_active IP Right Cessation
- 2002-06-28 CN CNB021272476A patent/CN1249794C/zh not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7923778B2 (en) | 2004-04-23 | 2011-04-12 | Semiconductor Energy Laboratory Co., Ltd. | Thin film integrated circuit and method for manufacturing the same, CPU, memory, electronic card and electronic device |
| CN103412423A (zh) * | 2013-08-27 | 2013-11-27 | 江西合力泰科技股份有限公司 | 一种低温印刷钛化硅的工艺 |
| CN103412423B (zh) * | 2013-08-27 | 2016-05-11 | 江西合力泰科技有限公司 | 一种低温印刷钛化硅的工艺 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1249794C (zh) | 2006-04-05 |
| US6800553B2 (en) | 2004-10-05 |
| US20030003731A1 (en) | 2003-01-02 |
| KR20030001038A (ko) | 2003-01-06 |
| KR100395776B1 (ko) | 2003-08-21 |
| JP2003051459A (ja) | 2003-02-21 |
| TW548747B (en) | 2003-08-21 |
| JP3873008B2 (ja) | 2007-01-24 |
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