CN1393933A - 化合物半导体装置 - Google Patents

化合物半导体装置 Download PDF

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Publication number
CN1393933A
CN1393933A CN02124890A CN02124890A CN1393933A CN 1393933 A CN1393933 A CN 1393933A CN 02124890 A CN02124890 A CN 02124890A CN 02124890 A CN02124890 A CN 02124890A CN 1393933 A CN1393933 A CN 1393933A
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electrode
grid
contact electrode
channel region
chip
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CN1260826C (zh
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浅野哲郎
上川正博
平田耕一
榊原干人
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Abstract

一种化合物半导体装置，用于高频器件的GaAsFET，为了缩小芯片尺寸、降低成本，将各接点电极沿芯片角配置为L型。为了更加缩小芯片尺寸、和提高高频特性，将各接点电极配置在芯片各角，FET在中央相对于芯片边呈45度倾斜配置。以此，芯片尺寸能更加缩小，可以实现比超高频的硅半导体的FET更便宜的GaAs FET。

Description

化合物半导体装置
技术领域
本发明涉及一种用于高频设备的化合物半导体装置，特别是涉及一种使芯片尺寸小型化，提高了高频特性的化合物半导体装置。
背景技术
随着世界性的手机市场的扩大及面向数字卫星广播接收机需求的高涨，高频设备的需求急剧扩张。作为其元件，由于使用高频波，采用镓、砷(GaAs)的场效应晶体管(以下称为FET)的情况增多，随之推进了将所述开关电路自身集成化的单片微波集成电路(MMIC)和本机振荡用FET的开发。
图5表示一例用于本机振荡的GaAsFET。
如图5(A)所示，GaAsFET由沟道区域12、源极用接点电极42、漏极用接点电极43及栅极用接点电极44。
构道区域12是，在非掺杂GaAs基板上层积形成非掺杂缓冲外延生长层、N外延生长层，在表面上配置肖特基接触的栅极，栅极的两侧配置与GaAs表面欧姆接触的源极、漏极。该FET根据栅极的电位，在正下方的沟道区域内形成耗尽层，进而控制源极和漏极之间的漏极电流。
在该图中以点划线包围的长方形的区域是形成于基板的沟道区域12。从右侧延伸的梳齿状的5根第三层接点金属层30是源极，其下有以第一层电阻金属层10形成的源极。另外从左侧延伸的梳齿状的4根第三层接点金属层30是漏极，其下有以第一层电阻金属层10形成的漏极。该两电极配置为将梳齿互相咬合的形状，其间以第二层栅格金属层20形成的栅极17，在沟道区域12上配置为8根梳齿形状。
源极接点电极42、漏极接点电极43及栅极接点电极44是第三层配线，是进行接点形成的接点金属层(Ti/Pt/Au)30。第二层配线是在FET的栅极形成时同时形成的栅格金属层(Ti/Al)20，在源极接点电极42及漏极接点电极43正下方也作为缓冲材料设置。另外，该栅格金属层20可以延伸，在栅极接点电极44正下方也作为缓冲材料设置。源极及漏极是与基板形成电阻接触的第一层电阻金属层(AuGe/Ni/Au)，与接点金属层30重叠。
栅极接点电极44及漏极接点电极43为防止高频信号互相泄漏而衰减，相互间隔，一个个设置形成被源极接点电极42截断的形状。即，将各个接点电极在半导体芯片上配置为L形，沿沟道区域12的两个边配置。源极接点电极42配置在半导体芯片的角部。
各接点电极上分别如虚线圆所示，固定着联接导线60(参照图5(B))。联接导线在源极接点电极42固定2根，在漏极及栅极接点电极43、44分别固定1根。各接点电极的大小，只要是有能固定60μm球径的联接导线所必需的最小程度的大小即可。源极接点电极42，为减小电阻及电感分量，固定着2根联接导线，但是由于设置在角部，联接导线压接时能确保充分的面积。
在图6表示图5的C-C线(图6(A))、D-D线(图6(B))、E-E线(图6(C))的断面图。
图6(A)表示漏极接点电极43的断面图。由于GaAs基板既硬且脆，作为缓冲材料在基板上设置栅格金属层20。将设置在其上的氮化膜25的一部分开口，设置以实线表示的第三层接点金属层(Ti/Pt/Au)30。而且在接点金属层30上热压联接导线。另外，源极接点电极42部分也是同样的结构。
在图6(B)表示栅极接点电极44断面图。将形成FET的栅极时同时形成的栅格金属层20延伸，其上设置第三层接点金属层(Ti/Pt/Au)30，形成栅极接点电极44。其上热压联接导线。
图6(C)表示交叉部的断面图。在接点金属层30中，栅极(栅格金属层20)及源极(接点金属层30)在沟道区域12外通过氮化膜交叉，与栅极接点电极44及源极接点电极42接触。该交叉部的面积约400μm2。
在本机振荡用FET、开关IC中，由于接点面积大，所以，芯片尺寸由接点数量决定的部分就非常大，这是实情。例如本发明的本机振荡用FET的情况，如果是接点中心-接点中心间距离为80μm，接点尺寸为60μm见方，接点端部-分块条(ストリ一ト)区域端部间距为10μm，分块条宽为50μm的标准，那么，芯片尺寸成为0.27×0.27mm2。这时就形成FET本身配置在接点与接点的间隙的感觉，接点数量、接点配置方案如此直接地决定芯片尺寸。
由图5可知，栅极及漏极接点电极44、43各自为1个即可，为防止各自的信号泄漏利用源极接点电极42截断，在芯片内，配置在远隔的对角线上。只要有充分的固定联接导线60的面积就可以了，所以，源极及栅极在沟道区域以外进行交叉，芯片尺寸可大幅度缩小。
在图7中表示的是，图5所示的FET的部分扩大的平面图及断面图。
图7(A)是平面图，被点划线包围的长方形区域，是形成于基板11上的沟道区域12。从右侧延伸的梳齿状的5根第三层接点金属层30是源极13，其下有以第一层电阻金属层10形成的源极14。另外从左侧延伸的梳齿状的4根第三层接点金属层30是漏极15，其下有以第一层电阻金属层10形成的漏极16。该两电极配置为将梳齿互相咬合的形状，其间以第二层栅格金属层20形成的栅极17，在沟道区域12上配置为梳齿形状。这里，该FET的栅格宽度Wg，是梳齿状栅极17的栅格宽度的总和，这时为400μm
图7(B)是表示FET的断面结构。在基板11，设置着由n型外延生长层决定的沟道区域12。为将沟道区域12与其他区域分离，设置离子注入硼等的绝缘层70，在沟道区域12利用栅格金属层20设置栅极17。作为FET，实际工作部分是该栅极17正下方的沟道区域12。在栅极17连接的沟道区域1 2两侧，设置以第一层电阻金属层10形成的漏极16及源极14。而且在其之上如前所述，设置以第三层接点金属层30形成的漏极15及源极13，进行各元件配线。
在图5所示的FET中，利用接点电极的精心配置，实现芯片尺寸的大幅缩小。但是，为了芯片进一步缩小，各接点电极之间的距离缩小到极限，联接导线的中心间距离变为80μm。而且，由于各接点电极距离近，邻接的联接导线之间的距离变近，所以，存在高频信号泄漏或者组装容易产生缺陷的问题。
另外，源极接点电极42由联接导线60引出，与接地端子GND连接，把与输入端子连接的栅极接点电极44和与输出端子连接的漏极接点电极43分离。但是，以设置栅极、漏极接点电极44、43的芯片对角线为中心，只是在一侧设置源极用的联接导线60(参照图5(B))，由源极决定的栅极及漏极的分离不能说充分。这样，栅极及漏极的分离不充分也与高频信号泄漏有关，成为不能提高高频特性的重要因素。
现在，硅半导体芯片的性能提高很惊人，在高频带利用的可能性不断提高。例如本机振荡电路，使用fT(截止频率)在25GHz以上的硅半导体晶体管，通过对应用电路下功夫，可以产生与使用GaAsFET的本机振荡电路相近的性能。目前，硅芯片在高频带的利用难，使用高价格的化合物半导体芯片，硅半导体的芯片性能好，只要有利用的可能性，则当然芯片价格高的化合物半导体芯片在价格竞争中会失败。实际上，所述的硅半导体晶体管与目前的本机振荡用GaAsFET比较，是便宜的。因此，缩小芯片尺寸、抑制成本是必然的，芯片尺寸缩小是不可避免的。另外，同时还要求高频特性的进一步改善。
发明内容
本发明是鉴于上述各种问题开发的，提供一种化合物半导体装置，其具有设置在化合物半导体基板表面的沟道区域、和与所述沟道区域表面连接的源极、漏极及栅极，设有分别与所述源极、漏极及栅极连接的源极接点电极、漏极接点电极及栅极接点电极，将各接点电极配置在芯片角，所述沟道区域的栅极、源极及漏极，沿芯片的大致对角线倾斜配置，通过对进行芯片内的FET及接点电极的配置下功夫，实现芯片尺寸缩小和提高高频特性。
附图说明
图1是用于说明本发明的平面图；
图2是用于说明本发明的(A)平面图、(B)断面图；
图3是用于说明本发明的(A)平面图、(B)断面图；
图4是用于说明本发明的平面图；
图5是用于说明目前技术的平面图；
图6是用于说明目前技术的断面图；
图7是用于说明目前技术的(A)平面图、(B)断面图。
具体实施方式
以下参照图1到图4说明本发明的实施例。
图1(A)表示一例作为本发明第一实施例的GaAsFET。
GaAsFET由沟道区域12、源极接点电极2、漏极接点电极3及栅极接点电极4构成。
沟道区域12是如下配置的，在非掺杂的GaAs基板上，进行非掺杂缓冲外延生长层、N型外延生长层的积层，在表面配置肖特基接触栅极，在栅极的两边配置与GaAs表面欧姆接触的源极、漏极。该FET利用栅极电位在正下方的沟道区域内形成耗尽层，进而控制源极、漏极间的漏极电流。
在该图中，被点划线包围的长方形区域，是形成于基板的沟道区域12。从左上侧伸展的梳齿状的第三层接点金属层30是源极，之下是第一层电阻金属层10形成的源极。另外，从右下侧延伸的梳齿状的第三层接点金属层30是漏极，之下是第一层电阻金属层10形成的漏极。该两电极配置为互相咬合的梳齿状，其间以第二层栅格金属层20形成的栅极17，在沟道区域12上配置为梳齿形状。
源极接点电极2、漏极接点电极3及栅极接点电极4是第三层的配线，是形成接点的接点金属层(Ti/Pt/Au)30。第二层的配线是，在FET的栅极形成时同时形成的栅格金属层(Ti/Al)20，也在源极接点电极2及漏极接点电极3正下方作为缓冲材料设置。另外，该栅格金属层20延伸，在栅极接点电极4正下方也作为缓冲材料设置。源极及漏极是与基板欧姆接触的第一层电阻金属层(AuGe/Ni/Au)，与接点金属层30重叠。
栅极接点电极4及漏极接点电极3，为防止高频信号互相泄漏而衰减，相互间隔一个个设置，形成被两个源极接点电极2截断的形状。即，将源极接点电极2配置在芯片对角线上的两个角上，栅极及漏极接点电极4、3分别配置在芯片的其余角。
如虚线圆圈所示，各接点电极分别固定一根联接导线60。各接点电极的大小，只要有能固定60μm球径的联接导线所必需的最小程度大小即可。联接导线60，固定在设置于对角线上的两个源极接点电极2上，形成这样的结沟，将设置在芯片对角线的漏极接点电极3和栅极接点电极4从芯片两侧截断(参照图1(B))。即，利用固定在源极接点电极2的联接导线，使与输入端子连接的栅极接点电极4、及与输出端子连接的漏极接点电极3之间的屏蔽性变好，作为高频特性的散射参数的S参数(S12)变小。因此，可以实现高频增益大的FET。
另外，联接导线从各角放射状地引出，邻接的导线接点的中心距离能大。由于邻接的联接导线之间的距离能较大，所以其间的高频信号泄漏能变小，因此有助于FET的高频增益的提高。
图1的接点部及交叉部的断面图与图6表示的一样，所以省略其说明。
图2是表示图1表示的FET的局部放大的平面图及断面图。
图2(A)是平面图，被点划线包围的长方形区域，是形成于基板11的沟道区域12。从左侧伸展的梳齿状的第三层接点金属层30是源极13，之下是第一层电阻金属层10形成的源极14。另外从右侧延伸的梳齿状的第三层接点金属层30是漏极15，之下是第一层电阻金属层10形成的漏极16。该两电极配置为互相咬合的梳齿状，其间，以第二层的栅格金属层20形成的栅极17，梳齿状地配置在沟道区域12上。这里，该FET的栅格宽度Wg，是梳齿状栅极17的栅格宽度的总和，这时为400μm。
图2(B)所示是FET的断面结构。且这时的断面结构是概略，以后详述，但是根据形成栅极的方向，不限于此。
在基板11上设置有基于n型外延生长层的沟道区域12。为使沟道区域与其他区域分离，离子注入硼等设置绝缘层70，在沟道区域12上利用栅格金属层20设置有栅极17。作为FET实际工作部分是该栅极17正下方的沟道区域12。在栅极17相接的沟道区域12两侧，设置以第一层的电阻金属层10形成的漏极16及源极14。而且在其之上，如前所述设置第三层的接点金属层30形成的漏极15及源极13，进行各元件配线等。
由图1可知，栅极及漏极接点电极4、3设置在芯片对角线上的各1个角上，为防止各自的信号泄漏，利用设置在另外对角线角上的源极接点电极2截断。各接点电极只要有固定联接导线60所需的充分的面积就可以，配置在芯片的各角上各接点电极形成剪掉芯片中心侧角部的形状。而且使FET的栅极、源极及漏极的梳齿相对芯片对角线，也就是芯片的边，呈45度倾斜配置，因此可以将中心部作为FET的沟道区域而有效活用。
因此，如果将目前的接点配置为L型的FET，直接采用倾斜45度的方案，那么栅格宽度为400μm时的0.27×0.27mm的芯片尺寸，成为0.25×0.25mm2。
另外，在沟道区域12以外，向源极接点电极2及栅极接点电极4延长的电极部分，通过氮化膜交叉，具有寄生容量。也就是说，即使是相同栅格宽度，也是交叉面积少的好，为些，就要有效地增加梳齿的长度，减少栅极的个数。各接点电极配置在角，形成将接点电极的芯片中心侧的角切掉的形状，利用将FET与芯片的边相对呈45度倾斜，芯片中心部分的面积就可以有效活用，所以不改变栅格总宽度(例如400μm)，就可将目前的8个栅极做成6个。以此，可减小基于交叉部的寄生容量，进一步提高高频特性。
具体地说，在目前L型接点配置的FET中，交叉部的面积为400μm2，但是，在本发明实施例中，通过使栅格宽为6个，交叉部的面积可以缩小到285μm2，寄生容量可以降低。另外，由该布置方案形成的芯片尺寸为0.26×0.26mm2，与目前L型接点配置的FET相比，芯片尺寸小，能实现高频特性良好的FET。
另外，将邻接的导线接点中心间距扩展到上述的0.25×0.25mm2时的110μm，0.26×0.26mm2时的120μm，所以组装容易，邻接的联接导线之间距离能增大。因此，联接导线之间高频信号泄漏减小，构成高频增益大的FET。
而且，通过将源极接点电极2配置在芯片对角线的角上，形成用其联接导线60，以对角线上的栅极接点电极4及漏极接点电极3为中心从芯片两侧截断的结构。即栅极-漏极之间的屏蔽性变好，作为高频特性的散射参数的S参数(S12)变小。因此也有助于高频增益变提高。
图3是本发明的第二实施例，表示一例GaAsFET。
该FET的布置方案图与图1表示的一样，省略其说明，其大的不同点在于形成栅极的方向。在图1表示的第一实施例的FET中，栅极无论形成在哪一个方向都可以，但是作为第二实施例的图3(A)表示的FET，GaAs半导体基板将(100)面作为表面，栅极实际上形成于基板的(0 1 1)方向(参照图4)。这里所谓(0 1 1)是结晶方向，是图3(A)或图4箭头表示的方向。因此，栅极的A-A线的断面形状变成图3(B)表示的样子。
与栅极17接触的沟道区域12，其表面尽可能不露出的，这样相位噪音特性变好。如果为在该(0 1 1)方向形成栅极17而进行槽蚀刻，那么，由于能蚀刻为沟道区域12表面露出少的形状，所以能实现本机振荡用等要求低相位噪音特性的FET。
另外，如图4所示，将栅极在(0 1 1)方向形成，如本发明，通过采用将FET相对于芯片边呈45度倾斜的布置方案，在薄片上将芯片分块时的分块工作区域，形成与(0 1 1)方向呈45度倾斜的方向。如果在该方向分块，那么，就有能大幅减小崩碎的优点。
这里以(0 1 1)方向进行了说明，但是，即使在将(0 1 1)方向旋转180度的(011)方向也能得到同样的效果。
因此，目前考虑崩碎，由于能将设置为50μm的切块工作区域宽度缩小到40μm，所以芯片尺寸还能更小。
因此，如果采用目前的将接点呈L型配置的FET直接倾斜45度的布置方案，那么，在栅格宽度为400μm时，芯片尺寸由0.27×0.27mm2变为0.24×0.24mm2。
另外，如前所述，在沟道领域12以外，延伸在源极接点电极2及栅极接点电极4的电极部分，通过氮化膜交叉，所以具有寄生容量。也就是说，即使是相同栅格宽度，也是交叉部的面积少的好，为此，就要有效地增加梳齿的长度，减少栅极的个数。各接点电极配置在角部，形成将各接点电极的芯片中心侧的角切掉的形状，利用将FET相对芯片的边呈45度倾斜，芯片中心部分的面积就可以有效活用，所以不改变栅格总宽度(例如400μm)，就可将目前的8个栅极做成6个。以此，可以减小基于交叉部的寄生容量，提高高频特性。该布置方案的芯片尺寸成为0.25×0.25mm2，比目前L型接点电极配置的FET芯片尺寸小，能实现高频特性良好的FET。
另外，将邻接的导线接点的中心距离扩展到上述的0.24×0.24mm2时为110μm，0.25×0.25mm2时为120μm，所以组装容易，邻接的联接导线之间距离能增大。因此，联接导线之间高频信号泄漏可减小，构成高频增益大的FET。
而且，与第一实施例一样，利用将源极接点电极2配置在芯片对角线上的角部，形成以其联接导线从芯片两侧截断栅极接点电极4和漏极接点电极3的结构。即，栅极-源极之间的屏蔽性变好，作为高频特性的散射参数的S参数(S12)变小。这也很有助于高频增益的提高。
本发明的特征在于，将两个源极接点电极2配置在芯片对角线上的角部，漏极接点电极3及栅极接点电极4分别配置在芯片的其他角部，而且在芯片中心部相对于芯片的边呈45度倾斜地配置FET。
因此，可以实现芯片内的空间可以有效地活用、可以缩小芯片尺寸、而且高频特性良好的化合物半导体装置。
如以上详述，根据本发明，可以得到以下种种效果。
第一，由于可以进行中心部分的空间有效活用的布置，所以，当采用将目前L型接点配置的FET直接倾斜的布置时，就可缩小到0.25×0.25mm2。
第二，由于空间可以活用，所以，以提高高频特性为目标，即使以同一栅格宽度，将栅格数量从8个减少到6个，芯片尺寸也可控制在0.26×0.26mm2内，与目前的L型接点配置的FET相比，芯片尺寸能够变小。
第三，可增大邻接的导线接点中心距离。在0.25mm正方时，距离能到110μm，0.26mm正方时，距离能到120μm，所以即使芯片尺寸小，邻接的联接导线之间的距离也能变大。以此，不但能减少组装时的不良，而且能减小邻接的联接导线之间的高频信号泄漏，结果是，能实现高频增益大的FET。
第四，能以对角线上的漏极接点电极3及栅极接点电极4为中心，将连接在源极接点电极2的联接导线60在芯片两侧引出，所以，利用连接到GND电位的源极，可以将与输入端子连接的栅极和与输出端子连接的漏极，从芯片两侧截断。就是说，使栅极-漏极之间的屏蔽性提高，故作为高频特性的散射参数的S参数(S12)变小。因此也能提高FET的高频增益。
第五，如果将FET的栅极在薄片的(0 1 1)方向或(011)方向形成，那么，为使栅极部分从沟道区域的露出减少可进行槽蚀刻，因此可以实现本机振荡用途等要求的低相位噪音特性的FET。
第六，通过将FET的栅极在薄片的(0 1 1)方向或(011)方向形成，切块时的崩损也能大幅减少，所以，能把切块工作区域宽度从50μm缩小到40μm，可进一步缩小芯片尺寸。例如，在将L型接点电极配置的FET直接倾斜的布置方案中，形成0.24×0.24mm2的尺寸，以进一步提高特性为目标，栅格总宽相同，如果栅格个数由8个变为6个，那么，就形成0.25×0.25mm2。
这样，如果芯片尺寸可以缩小，那么，FET的价格也就大幅降低。例如，在目前的0.27mm正方的芯片尺寸下，薄片可获得相当于5.2万个的芯片数量，但根据本发明的实施例，0.26mm正方的，可获得的芯片数量为5.6万个，0.25mm正方的，可获得的芯片数量为6万个，0.24mm正方的，可获得的芯片数量为6.5万个，大幅度增加。使用fT在25GHz程度的超高频硅半导体晶体管的本机振荡电路，通过对应用电路下功夫，可产生出与使用GaAsFET的本机振荡电路相近的性能。目前，GaAsFET与超高频硅晶体管相比，价格方面处于不利地位。但是，在本发明的GaAsFET中，由于能降低成本，所以与该超高频硅晶体管比较，能以大幅下调的价格提供。

Claims (7)

1、一种化合物半导体装置，具有设置在化合物半导体基板表面的沟道区域和、连接在所述沟道区域表面的源极、漏极及栅极；设置了与所述源极、漏极及栅极分别连接的源极用接点电极、漏极用接点电极及栅极用接点电极，其特征在于，
将各接点电极配置在芯片的角部，将所述沟道区域的栅极、源极及漏极沿芯片的大致对角线倾斜配置。
2、一种化合物半导体装置，具有设置在化合物半导体基板表面的沟道区域和、连接在所述沟道区域表面的源极、漏极及栅极；设置了与所述源极、漏极及栅极分别连接的源极用接点电极、漏极用接点电极及栅极用接点电极，其特征在于，
将所述源极用接点电极配置在芯片对角线上两个角部，将栅极及漏极用接点电极分别配置在芯片剩余的角部，使所述沟道区域的栅极、源极及漏极相对于芯片的边，呈30度到60度角倾斜配置。
3、如权利要求1或2所述的化合物半导体装置，其特征在于，所述化合物半导体基板，将(100)面作为表面，所述栅极实际上在所述基板的(0 1 1)方向或(011)方向形成。
4、如权利要求1或2所述的化合物半导体装置，其特征在于，所述源极及所述栅极在所述沟道区域外通过绝缘膜交叉，连接在所述源极用接点电极及栅极用接点电极上。
5、如权利要求1或2所述的化合物半导体装置，其特征在于，在所述各接点电极上，分别各固定一根联接导线。
6、如权利要求1或2所述的化合物半导体装置，其特征在于，作为所述化合物半导体基板，采用GaAs基板，在其表面形成所述沟道区域。
7、如权利要求1或2所述的化合物半导体装置，其特征在于，所述栅极在沟道区域形成肖特基结，所述源极与漏极在沟道区域形电阻结。
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