CN1387644A - 并行处理器体系结构的sdram控制器 - Google Patents
并行处理器体系结构的sdram控制器 Download PDFInfo
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Abstract
说明一种并行、基于硬件的多线程处理器。该处理器包括一协调各系统功能的通用处理器和支持多硬件线程的多个微引擎。该处理器还包括具有第1存储控制器和第2存储控制器的存储控制系统,前者存储控制器根据存储器指针是指向偶数存储组还是指向奇数存储组对存储器指针进行分类,后者存储器根据存储器指针是读指针还是写指针对存储器指针进行优化。
Description
背景技术
本发明涉及一种存储器的控制器,尤其是并行处理器用这种控制器。
并行处理是计算处理中并发事件信息处理的有效形式。与串行处理相反,并行处理要求计算机中同时执行许多程序。在并行处理的情况下,并行操作涉及同时做一件以上的事情。与在某一站串行执行全部任务的串行范例或在专门站执行任务的流水式机器有所不同,并行处理配备多个站,每个站能执行全部任务。也就是说,通常全部站或多个站对问题的相同或共同要素进行同时且独立的工作。有些问题适合采用并行处理解决。
并行处理任务中所用的存储系统可能是无效率的。
发明概述
根据本发明的一个方面,一种随机存取存储器的存储控制器包含保持来自多个微控制单元的存储器指针的地址和命令队列。存储控制器还包含保持来自计算机总线的存储器指针的第1读/写队列和保持来自核心处理器的存储器指针的第2读/写队列。该存储控制器还包含具有仲裁器的控制逻辑,该仲裁器检测每一队列的满员程度和待处理存储器指针的状态,以便从其中一个队列选择一存储器指针。
根据本发明的又一方面,该控制器具有对链接位作出响应的控制逻辑,该链接位在设定时允许对邻接存储器指针专门处理。该链接位还控制仲裁器,使仲裁器选择先前请求总线的功能单元。链接位的肯定将会控制仲裁器,使其当经过优化的存储位也设定时保持来自当前队列的存储器指针。
本发明的一个或多个方面可提供以下一个或多个优点。
控制器当经优化存储位设定时使用存储器指针分类。存储器指针分类基于可使某一存储组对另一存储组隐藏预充电的存储组指针。具体来说,若存储器系统组织成奇数存储组和偶数存储组,而存储控制器工作于奇数存储组,存储控制器便可启动对偶数存储组的预充电。若存储器指针在奇数和偶数存储组间交替,就能预充电。
此外,还可用其他优化。举例来说,可采用归并优化、开放页面优化、链接以及刷新机制,在归并优化场合,可归并的操作在存储器存取前归并,而开放页面优化场合则通过检查地址使存储器的开放页面不再开放。
此控制器的另一特征在于,当队列中存放一存储器指针时,除可设定的经优化存储位以外,该控制器还用A链接位@。该链接位当设定时便允许对邻接存储器指针专门处理。链接位的肯定将会控制仲裁器,使仲裁器选择先前请求存储器总线的功能单元。
附图简要说明
图1是采用基于硬件的多线程处理器的通信系统的框图。
图2是图1中基于硬件的多线程处理器的具体框图。
图3是图1和图2中基于硬件的多线程处理器所用的微引擎功能单元的框图。
图3A是图3中微引擎流水线的框图。
图3B是表示环境切换指令格式的示意图。
图3C是表示通用寄存器地址安排的框图。
图4是基于硬件的多线程处理器中所用的强化带宽操作用存储控制器的框图。
图4A是表示图4中SDRAM控制器的仲裁策略的流程图。
图4B是说明对SDRAM控制器进行优化的好处的时序图。
图5是基于硬件的多线程处理器中所用的等待时间有限的操作用存储控制器的框图。
图5A是表示对SRAM控制器进行优化的好处的时序图。
图6是图1中处理器的通信总线接口的框图。
说明
体系结构
参照图1,通信系统10包括一并行、基于硬件的多线程处理器12。该基于硬件的多线程处理器12与诸如PCI总线14这种总线、存储器系统16和第二总线18连接。系统10对可分解为并行子任务或功能的任务尤其有用。具体来说,硬件多线程处理器12对那些面向带宽的任务而非面向等待时间的任务有用。硬件多线程处理器12具有多重微引擎22,分别配备可对一任务同时作用和独立工作的多重硬件控制的线程。
硬件多线程处理器12还包括一中央控制器20,该控制器有助于对硬件多线程处理器12的其他资源加载微码控制,并执行其他通用计算机类型功能,诸如处理协议、异常以及微引擎在边界状态等条件下传出数据分组进行更为细节处理场合对分组处理的额外支持。一实施例中,处理器20是一基于StrongArmT(Arm是英国Arm有限公司的商标)的体系结构。通用微处理器20具有一操作系统。通过该操作系统,处理器20可调用功能在微引擎22a~22f上操作。处理器20可利用任何得到支持的操作系统,最好用实时操作系统。对按Strong Arm结构实现的核心处理器来说,可用诸如微软NT实时、VXWorks和μCUS这种操作系统和可从互联网得到的免费件操作系统。
硬件多线程处理器12还包含多个功能微引擎22a~22f。这些功能微引擎(微引擎)22a~22f分别在硬件及其关联状态方面保持多个程序计数器。实际上,各微引擎22a~22f中可同时使相应的多组线程工作,而任何时候仅一个真正操作。
一实施例中,存在6个微引擎22a~22f,如图所示,每一微引擎22a~22f能处理4个硬件线程。6个微引擎22a~22f以包括存储器系统16以及总线接口24和28在内的共用资源进行工作。存储器系统16包含同步动态随机存取存储器(SDRAM)的控制器26a和静态随机存取存储器(SRAM)的控制器26b。SDRAM存储器16a和SDRAM控制器26a通常用于处理大量数据,例如处理来自网络数据分组的网络有效负载。SRAM控制器26b和SRAM存储器16b在网络实施例当中实现较小等待时间、迅速存取任务,例如存取查找表、核心处理器20的存储器等。
6个微引擎22a~22f根据数据特性存取SDRAM16a或SRAM16b。因此,对SRAM存入并读取短等待时间且小带宽的数据,而对SDRAM则存入并读取等待时间不重要的大带宽数据。微引擎22a~22f可对SDRAM控制器26a或SRAM控制器26b执行存储器指针指令。
可通过SRAM或SDRAM的存储器存取说明硬件多线程的优点。举例来说,一线程0所请求的微引擎对SRAM的存取会使SRAM控制器26b启动对SRAM存储器16b的存取。SRAM控制器控制对SRAM总线的仲裁,对SRAM16进行存取,从SRAM16b读取数据,并使数据返回至提出请求的微引擎22a-22b。SRAM存取期间,若微引擎(例如22a)仅具有一个可运作的线程,该微引擎会休眠直到从SRAM返回数据。通过采用每一微引擎22a~22f内的硬件环境对换,该硬件环境对换能使具有独特程序计数器的其他环境在该相同微引擎中执行。因此,第一线程(例如线程0)等待所读出数据返回的同时,另一线程例如线程1可起作用。执行期间,线程1可存取SDRAM存储器16a。线程1在SDRAM单元上运作,线程0在SRAM单元上运作的同时,新线程例如线程2可在微引擎22a中现场运作。线程2可运作一些时间直到该线程需要存取存储器或执行某些其他长等待时间操作,诸如对总线接口进行存取。因此,处理器12可同时使总线运作、SRAM运作和SDRAM运作均得到完成,或由一个微引擎22a在其上运作,全部完成或正在工作的总线操作、SRAM操作和SDRAM操作,并且使另一个线程可用于处理数据通路中更多的工作。
硬件环境对换还使任务完成同步。举例来说,2个线程会同时命中相同的共用资源例如SRAM。诸如FBUS(F总线)接口28、SRAM控制器26a和SDRAM26b等每一个独立功能单元当其完成其中一个微引擎线程环境所请求的任务时,便回报一通知完成运作的标志。微引擎收到该标志,便能判断开通哪一线程。
利用硬件多线程处理器的一个例子是用作网络处理器。作为网络处理器,硬件多线程处理器12作为与诸如媒体存取控制器(例如10/100BaseT8进制MAC13a或千兆位以太网13b)这种网络装置的接口。通常作为一网络处理器,硬件多线程处理器12可作为与任何类型通信设备的接口或收发大量数据的接口。在联网应用中起作用的通信系统10可从设备13a和13b接收多个网络数据分组,以并行方式处理这些数据分组。可采用硬件多线程处理器12独立处理各网络数据分组。
处理器12的另一应用例是一附录处理器用打印引擎或作为存储子系统(即RAID磁盘存储器)的处理器。再一应用是作为配对引擎。举例来说,在证券业中,电子交易的出现要求用电子配对引擎来搓合买方和卖方的报单。可在系统10上完成上述和其他并行任务。
处理器12包括一将该处理器与第2总线18连接的总线接口28。一实施例中,总线接口28将处理器12与所谓的FBUS18(FIFO总线)连接。FBUS接口28负责控制处理器12和形成该处理器与FBUS18的接口。FBUS18是64位宽的FIFO总线,用于形成与媒体存取控制器(MAC)设备的接口。
处理器12包括一第二接口(例如PCI总线接口24),该接口将驻留PCI总线14上的其他系统组成部分与处理器12连接。PCI总线接口24提供一至存储器16(例如SDRAM存储器16a)的高速数据通路24a。通过该通路,数据可从SDRAM16a通过直接存储器存取(DMA)的传送经PCI总线14转移。硬件多线程处理器12支持图像传送。硬件多线程处理器12能用多个DMA通道,因而若DMA传送的一个目标忙,另一DMA通道便可接管PCI总线对另一目标传送信息,以维持处理器12高效。此外,PCI总线接口还支持目标和主机操作。目标操作是总线14上的从属装置通过对该操作起从属作用的读和写存取SDRAM场合的操作。主机操作中,处理器核心20直接对PCI接口24收、发数据。
每一功能单元连接1条或多条内部总线。下文将说明,内部总线是32位的双总线(即1条总线用于读,另1条用于写)。硬件多线程处理器12结构上还做成处理器12中内部总线带宽之和大于处理器12所接外部总线的带宽。处理器12包含内部核心处理器总线,例如ASB总线(高级系统总线:Advancedsystem Bus),该总线将处理器核心接到存储控制器26a、26b和ASB译码器30,后文将说明。ASB总线是配合Strong Arm处理器核心用的所谓AMBA总线的子集。处理器12还包含将微引擎单元接到SRAM控制器26b、ASB变换器30和FBUS接口28的专用总线34。存储器总线38将存储控制器26a、26b接到总线接口24、28和包含用于引导操作等的快速擦写ROM16c的存储器系统16。
参照图2,每一微引擎22a~22f包含仲裁器,检查标志以判定可提供的工作线程。来自任一微引擎22a~22f的任何线程都可访问SDRAM控制器26a、SRAM控制器26b或FBUS接口28。存储控制器26a和26b分别包含多个队列,以存放待处理的存储器指针请求。这些队列保持存储器指针的次序或者安排存储器指针来优化存储器带宽。举例来说,若线程0相对线程1独立或者无关,线程1和0便没有理由无法不按顺序完成其存储器指针指向SRAM单元。微引擎22a~22f对存储控制器26a和26b发布存储器指针请求。微引擎22a~22f以足够的存储器指针操作充满存储器子系统26a和26b,使得该存储器子系统26a和26b成为处理器12运作的瓶颈。
若存储器子系统16充满本质上独立的存储器请求,处理器12便可进行存储器指针分类。该存储器指针分类改善能达到的存储器带宽。如下文所述,存储器指针分类减少存取SRAM时所出现的空载时间或空泡。通过存储器指针指向SRAM,在读写之间对信号线电流方向的切换,产生等待SRAM16b与SRAM控制器26b连接的导体上的电流稳定的空泡或空载时间。
也就是说,在总线上驱动电流的驱动器需要在状态变化前稳定。因此,读后接着写的重复周期会使峰值带宽下降。存储器指针分类允许组织指针指向存储器,使得长串的读出后面接着长串的写入。这可用于使流水线的空载时间最少,以有效达到接近最大可用带宽。指针分类有助于保持并行硬件环境线程。对于SDRAM,指针分类使一存储组对另一存储组可隐藏预充电。具体而言,若存储器系统166组织成奇数存储组和偶数存储组,而处理器在奇数存储组上工作,存储控制器便可在偶数存储组启动预充电。若存储器指针在奇数和偶数存储组之间交替变化,便可预充电。通过安排存储器指针的顺序交替访问相对存储组,处理器12改善SDRAM的带宽。此外,还可采用其他优化。举例来说,可采用可归并的运作在存储器存取前归并场合的归并优化、通过检查地址不重新打开存储器开放页面场合的开放页面优化、将在下面说明的链接以及刷新机制。
FBUS接口28支持MAC装置所支持的各端口用的收和发标志,还支持表明业务何时得到保证的中断标志。FBUS接口28还包含对来自FBUS18的输入数据组首部进行处理的控制器28a。控制器28a提取该分组的首部,并且在SRAM中进行可微编程源/宿/协议散列查找(用于地址平滑)。如果散列未成功分辨,将分组首部送到处理器核心20进行附加处理。FBUS接口28支持下列内部数据事务:
FBUS单元 (共用总线SRAM) 至/来自微引擎
FBUS单元 (经专用总线) 从SDRAM单元写入
FBUS单元 (经MBUS) 读出至SDRAM
FBUS18是标准业界总线,其中包含例如64位宽的数据总线、地址边带控制和读/写控制。FBUS接口28能用一系列输入输出FIFO29a~29b输入大量数据。微引擎22a~22f从FIFO29a~29b取得数据,命令SDRAM控制器26a将来自己从总线18上的装置得到数据的接收FIFO的数据移入FBUS接口28。该数据可通过存储控制器26a,经直接存储器存取送到SDRAM存储器16a。同样,微引擎能将从SDRAM26a至接口28的数据经FBUS接口28移出到FBUS18。
在微引擎之间分配数据功能。经由命令请求连接SRAM26a、SDRAM26b和FBUS28。命令请求可以是存储器请求或FBUS请求。例如,命令请求能将数据从位于微引擎22a的寄存器移到共用资源,例如移到SDRAM位置、SRAM位置、快速擦写存储器或某MAC地址。这些命令送出到每一功能单元和共用资源。然而,共用资源不需要保持数据的局部缓存。反之,共用资源存取位于微引擎内部的分布数据。这使微引擎22a~22f可局部存取数据,而不是对总线上存取的仲裁,冒争用总线的风险。利用此特征,等待数据内部到达微引擎22a~22f的阻塞周期为0。
连接这些资源(例如存储控制器26a和26b)的例如ASB总线30、SRAM总线34和SDRAM总线38等数据总线具有足够的带宽,使得无内部阻塞。因此,为了避免阻塞,处理器12具有每一功能单元配备内部总线最大带宽至少2倍的带宽要求。例如,SDRAM可以83MHz运作于64位宽总线。SRAM数据总线可具有读写分开的总线,例如可以是运作于166MHz的32位宽读出总线和运作于166MHz的32位宽写入总线。也就是说,运作于166Mhz的64位实际上是SDRAM带宽的2倍。
核心处理器20也可存取共用资源。核心处理器20经总线32直接与SDRAM控制器26a、总线接口24和SRAM控制器26b通信。然而,为了访问微引擎22a~22f和任一微引擎22a~22f的传送寄存器,核心处理器24经ASB变换器30在总线34上存取微引擎22a~22f。ASB变换器30可在实体上驻留于FBUS接口28,但逻辑上不同。ASB变换器30进行FBUS微引擎传送寄存器位置与核心处理器地址(即ASB总线)之间的地址变换,以便核心处理器20能访问属于微引擎22a~22c的寄存器。
虽然如下文所述微引擎22可用寄存器组交换数据,但还提供便笺存储器27,使微引擎能将数据写到该存储器,供其他微引擎读取。便笺式存储器27连接总线34。
处理器核心20包含在5级流水线实现的RISC核心50,该流水线进行在单个周期内对1个操作数或2个操作数的单周期移位,提供乘法支持和32位滚筒型移位支持。此RISC核心50具有标准Strong ArmT体系结构,但由于性能上的原因,用5级流水线实现。处理器核心20还包含16K字节指令快速缓存器52、8K字节数据快速缓存器54和预读取流缓存器56。核心处理器20执行与存储器写入和指令读取并行的算术运算。核心处理器20经ARM规定的ASB总线与其他功能单元形成接口。ASB总线是32位双向总线32。
微引擎
参照图3,示出微引擎22a~22f中一示范例,例如微引擎22f。微引擎包含控制存储器70,在一实施例中该存储器包含这里达1024字(每字32位)的RAM。该RAM存储一微程序。该微程序可由核心处理器20加载。微引擎22f还包含控制器逻辑72。该控制器逻辑包含指令译码器73和程序计数器(PC)单元72a~72d。按硬件维持4个微程序计数器72a~72d。微引擎2f还包含环境事件切换逻辑74。该环境事件逻辑74从例如SRAM26a、SDRAM26b或处理器核心20、控制及状态寄存器等共用资源的每一个接收消息(例如:序号#事件响应SEQ_#_EVENT_RESPONSE、FBI事件响应FBI_EVENT_RESPONSE、SRAM事件响应SRAM_EVENT_RESPONSE、SDRAM事件响应SDRAM_EVENT_RESPONSE和ASB事件响应ASB_EVENT_RESPONSE)。这些消息提供有关请求的功能是否完成的信息。根据线程请求的功能是否完成和信号传送是否完成,线程需要等待该完成信号,如果线程能工作,便将该线程放到可用线程列表(未示出)。微引擎22a可具有最多例如4个可用线程。除执行线程局部所有的事件信号外,微引擎22还用全局的信令状态。借助该信令状态,执行线程可对全部微引擎22广播信号状态。接收请求可行信号后,微引擎中的全部任何线程可按这些信令状态分支。可用这些信令状态判定资源的可用性或资源提供服务是否适当。
环境事件逻辑74具有对4个线程的仲裁。一实施例中,仲裁是一循环机制。可用包括优先级排队或加权合理排队在内的其他技术。微引擎22f还包括一执行框(EBOX)数据通路76,其中包含算术逻辑单元76a和通用寄存器组76b。算术逻辑单元76a执行算术和逻辑功能以及移位功能。寄存器组76b具有数量较多的通用寄存器。图3B中将说明,此实施例中,第1组(组A)具有64个通用寄存器,第2组(组B)也具有64个。这些通用寄存器形成窗口(后文将说明),以便其可相对寻址和绝对寻址。
微引擎22f还包含写传送寄存器堆栈78和读传送堆栈80。这些寄存器也形成窗口,以便其可相对寻址和绝对寻址。资源的写入数据位于写传送寄存器堆栈78。读寄存器堆栈80则用于从共用资源返回的数据。分别来自例如SRAM控制器26a、SDRAM控制器26b或核心处理器20之类共用资源的事件信号,与数据的到达串行或并行提供给环境事件仲裁器74,提醒线程数据可用或数据已发送。传送寄存器组78和80都通过数据通路连接执行框(EBOX)76。一实施例中,读传送寄存器具有64个寄存器,写传送寄存器也有64个。
如图3A所示,微引擎数据通路维持5级微流水线82。该流水线包含查找微指令字82a、形成寄存器文件地址82b、从寄存器文件读操作数82c、ALU或移位或比较运算82d和结果写回寄存器82e。通过提供回写数据旁路至ALU/移位器单元,假定按寄存器文件而非RAM实现寄存器,微引擎可执行寄存器文件同时读写,完全隐藏写操作。
SDRAM接口26a在读数据上对提出请求的微引擎送回一表明是否在读请求上出现奇偶差错的信号。微引擎采用任何送回的数据时,微引擎的微码负责校验SDRAM读奇偶标志。校验该标志时,如果设定该标志,分支动作将其消除。仅在启用SDRAM供校验时发送奇偶标志,SDRAM受奇偶性防护。微引擎和PCI单元是通知奇偶差错的唯一请求者。因此,如果处理器核心20或FIFO要求奇偶性保护,微引擎就按请求帮助。微引擎22a~22f支持条件分支。分支判决结果是先前微控制指令设定条件码时,出现条件分支执行时间(不包含转移)最坏的情况。表1示出该等待时间如下:
|1|2|3|4|5|6|7|8|
------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n2|XX|b1|b2|b3|b4|
寄存器地址生成 | |n1|cb|XX|XX|b1|b2|b3|
寄存器文件查找 | | |n1|cb|XX|XX|b1|b2|
ALU/shifter/cc | | | |n1|cb|XX|XX|b1|
写回 | | |m2| |n1|cb|XX|XX|
其中,
nx是预分支微字(n1设定为cc)
cb是条件转移
bx是后分支微字
xx是异常微字
如表1所示,直到周期4才设定条件码n1,能进行分支判决,这在本例中使用周期5上查找分支路径。微引擎由于必须在分支路径用操作b1填充流水线前吸收流水线中操作n2和n3(紧接分支后的2个微字),带来2个周期的分支等待时间损失。如果不进行分支,就不吸收微字,按常规继续执行。微引擎有若干机制用于减少或消除有效分支等待时间。
微引擎支持延迟分支。延迟分支是微引擎允许在分支后实施分支前出现1个或2个微字的情况(即分支作用在时间上“延迟”)。因此,如果能找到有用的工作填补分支微字后所浪费的周期,就能隐去分支等待时间。下面示出延迟1周期的分支,其中允许在cb后、b1前执行n2:
|1|2|3|4|5|6|7|8|
------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n2|XX|b1|b2|b3|b4|
寄存器地址生成 | |n1|cb|n2|XX|b1|b2|b3|
寄存器文件查找 | | |n1|cb|n2|XX|b1|b2|
ALU/shifter/cc | | | |n1|cb|n2|XX|b1|
写回 | | | | |n1|cb|n2|XX|
下面示出2周期的延迟分支,其中n2和n3都允许在分支到b1出现前完成。注意,仅分支前在微字设定条件码时,允许2周期分支延迟。
|1|2|3|4|5|6|7|8|9|
------------------+----+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n2|n3|b1|b2|b3|b4|b5|
寄存器地址生成 | |n1|cb|n2|n3|b1|b2|b3|b4|
寄存器文件查找 | | |n1|cb|n2|n3|b1|b2|b3|
ALU/shifter/cc | | | |n1|cb|n2|n3|b1|b2|
写回 | | | | |n1|cb|n2|n3|b1|
微引擎也支持条件码估值。如果分支前判决分支的条件码设定2个或多个微字,则由于能早1周期进行分支判决,能消除1周期的等待时间如下:
|1|2|3|4|5|6|7|8|
------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|n2|cb|XX|b1|b2|b3|b4|
寄存器地址生成 | |n1|n2|cb|XX|b1|b2|b3|
寄存器文件查找 | | |n1|n2|cb|XX|b1|b2|
ALU/shifter/cc | | | |n1|n2|cb|XX|b1|
写回 | | | | |n1|n2|cb|XX|
此例中,n1设定条件码,n2不设定条件码。因此,可在周期4而不是周期5进行分支判决,以消除1周期的分支等待时间。下面的例子中,将1周期延迟与条件码提早设定加以组合,以完全隐去分支等待时间:
|1|2|3|4|5|6|7|8|
------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|n2|cb|n3|b1|b2|b3|b4|
寄存器地址生成 | |n1|n2|cb|n3|b1|b2|b3|
寄存器文件查找 | | |n1|n2|cb|n3|b1|b2|
ALU/shifter/cc | | | |n1|n2|cb|n3|b1|
写回 | | | | |n1|n2|cb|n3|
其中,在1周期延迟分支前的2周期设定条件码cc。
在不能提前设定条件码的情况下(即条件码设定在分支前的微字中时),微引擎支持试图减少1周期留下的暴露分支等待时间的分支猜测。通过“猜测”分支路径或串行路径,微定序器在确切知道执行何路径前预先取得猜测路径1。猜测如果正确,就消除1周期分支等待时间如下:
|1|2|3|4|5|6|7|8|
------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n1|b1|b2|b3|b4|b5|
寄存器地址生成 | |n1|cb|XX|b1|b2|b3|b4|
寄存器文件查找 | | |n1|cb|XX|b1|b2|b3|
ALU/shifter/cc | | | |n1|cb|XX|b1|b2|
写回 | | | | |n1|cb|XX|b1|
其中猜测进行分支而且也进行分支。如果微码猜测进行的分支不正确,微引擎仍然浪费1周期:
|1|2|3|4|5|6|7|8|
------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n1|XX|n2|n3|n4|n5|
寄存器地址生成 | |n1|cb|n1|XX|n2|n3|n4|
寄存器文件查找 | | |n1|cb|n1|XX|n2|n3|
ALU/shifter/cc | | | |n1|cb|n1|XX|n2|
写回 | | | | |n1|cb|n1|XX|
其中猜测进行分支但不进行分支。
然而,微码猜测不进行分支时,有差异地分配等待时间损失。
对猜测不进行分支而且也不进行分支而言,不存在浪费周期,如下所示:
|1|2|3|4|5|6|7|8|
------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n1|n2|n3|n4|n5|n6|
寄存器地址生成 | |n1|cb|n1|n2|n3|n4|n5|
寄存器文件查找 | | |n1|cb|n1|n2|n1|b4|
ALU/shifter/cc | | | |n1|cb|n1|n2|n3|
写回 | | | | |n1|cb|n1|n2|
然而,对猜测不进行分支但进行分支而言,存在2个浪费周期如下:
|1|2|3|4|5|6|7|8|
------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n1|XX|b1|b2|b3|b4|
寄存器地址生成 | |n1|cb|XX|XX|b1|b2|b3|
寄存器文件查找 | | |n1|cb|XX|XX|b1|b2|
ALU/shifter/cc | | | |n1|cb|XX|XX|b1|
写回 | | | | |n1|cb|XX|XX|
微引擎可组合分支猜测和1周期分支延迟,以进一步改善结果。对猜测进行分支加上1周期延迟分支而且也进行分支而言,其结果为:
|1|2|3|4|5|6|7|8|
------------------+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n2|b1|b2|b3|b4|b5|
寄存器地址生成 | |n1|cb|n2|b1|b2|b3|b4|
寄存器文件查找 | | |n1|cb|n2|b1|b2|b3|
ALU/shifter/cc | | | |n1|cb|n2|b1|b2|
写回 | | | | |n1|cb|n2|b1|
上述情况下,通过执行n2和正确猜测分支方向,隐去2周期分支等待时间。如果微码猜测不正确,仍暴露1周期等待时间如下:
|1|2|3|4|5|6|7|8|9|
------------------+----+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n2|XX|n3|n4|n5|n6|n7|
寄存器地址生成 | |n1|cb|n2|XX|n3|n4|n5|n6|
寄存器文件查找 | | |n1|cb|n2|XX|n3|n4|n5|
ALU/shifter/cc | | | |n1|cb|n2|XX|n3|n4|
写回 | | | | |n1|cb|n2|XX|n3|
其中,猜测进行分支加上1周期延迟分支但不进行分支。
如果微码正确猜测不进行分支,流水线按常规不受干扰的情况顺序进行。微码错误猜测不进行分支,微引擎又暴露1周期非生产性执行如下:
|1|2|3|4|5|6|7|8|9|
------------------+----+----+----+----+----+----+----+----+----+
微存储查找 |n1|cb|n2|XX|b1|b2|b3|b4|b5|
寄存器地址生成 | |n1|cb|n2|XX|b1|b2|b3|b4|
寄存器文件查找 | | |n1|cb|n2|XX|b1|b2|b3|
ALU/shifter/cc | | | |n1|cb|n2|XX|b1|b2|
写回 | | | | |n1|cb|n2|XX|b1|
其中,猜测不进行分支但进行分支,而且
nx是预分支微字(n1设定为cc)
cb是条件转移
bx是后分支微字
xx是异常微字
在转移指令的情况下,由于直到ALU级中存在转移的周期结束才知道分支地址,造成3个额外周期的等待时间如下:
|1|2|3|4|5|6|7|8|9|
------------------+----+----+----+----+----+----+----+----+----+
微存储查找 |n1|jp|XX|XX|XX|j1|j2|j3|j4|
寄存器地址生成 | |n1|jp|XX|XX|XX|j1|j2|j3|
寄存器文件查找 | | |n1|jp|XX|XX|XX|j1|j2|
ALU/shifter/cc | | | |n1|jp|XX|XX|XX|j1|
写回 | | | | |n1|jp|XX|XX|XX|
环境切换
参照图3B,其中示出环境切换指令的格式。环境切换是促使选择不同环境(及其相关联PC)的特殊分支形式。环境切换也引入一些分支等待时间。考虑以下的环境切换:
|1|2|3|4|5|6|7|8|9|
------------------+----+----+----+----+----+----+----+----+----+
微存储查找 |o1|ca|br|n1|n2|n3|n4|n5|n6|
寄存器地址生成 | |o1|ca|XX|n1|n2|n3|n4|n5|
寄存器文件查找 | | |o1|ca|XX|n1|n2|n3|n4|
ALU/shifter/cc | | | |o1|ca|XX|n1|n2|n3|
写回 | | | | |o1|ca|XX|n1|n2|
其中,
ox是旧环境流
br是旧环境中分支微字
ca是环境再仲裁(致使环境切换)
nx是新环境流
XX是异常微字
环境切换中,致使“br”微字异常,以避免保留正确旧环境PC会造成的控制和定时复杂性。
按照分支前在微字上设定的ALU条件码操作的条件分支可选择0、1或2周期分支延迟模式。所有其他分支(包括环境再仲裁)可选择0或1周期分支延迟模式。可设计体系结构使环境仲裁微字在前置分支的分支延迟窗内、转移或使该微字为非法任选项。也就是说,某些实施例中,由于如上所述原因,其会造成保存旧环境PC过度复杂,流水线中分支转换时不允许发生环境切换。还可设计体系结构,使在前置分支的分支延迟窗内的分支、转换或者环境仲裁微字非法,以免分支行为复杂且不可预测。
每一微引擎22a~22f支持4个环境的多线程执行。其原因之一是使1个线程可正好在另一线程发布存储器指针后开始执行,并且必须等待直到该指针完成后才进行更多工作。由于存储器等待时间显著,此性能对维持微引擎硬件有效执行至关重要。换句话说,若仅支持一个线程执行,微引擎就会闲置大量周期,等待指针返回,从而使总的计算吞吐量减少。多线程执行通过跨越多个线程执行有用的独立工作,使微引擎可隐去存储器等待时间。提供2种同步机制,以便使线程可发布SRAM或SDRAM指针,并且在完成该访问时,接着与下一个时间点同步。
一种机制是立即同步。立即同步中,微引擎发布指针,并且立即换出该环境。相应的指针完成时便发信号通知该环境。一旦发信号,便换回环境,以便当出现环境对换事件且轮到其运作时执行。因此,从单一环境指令流的角度看,微字在发出存储器指针后要到指针完成才得以执行。
第2种机制是延迟同步。延迟同步中,微引擎发布指针后,继续执行一些其他与指针无关的有用工作。过些时间,变成需要线程执行流与所发布指针的完成同步后再进一步工作。这时,执行同步微字,换出当前线程,并且在过一些时间完成指针时将其换回,或者由于已经完成指针而继续执行当前线程。用以下2种不同信令方案实现延迟同步。
若存储器指针与传送寄存器关联,在设定或消除相应传送寄存器有效位时便产生触发线程的信号。举例来说,设定寄存器A有效位时,便发出在传送寄存器A中存数据这种SRAM读出的信号。若存储器指针与传送FIFO或接收FIFO关联,而不是与传送寄存器关联,在SDRAM控制器26a中完成访问时产生信号。微引擎调度器中仅保持每一环境一种信号状态,因而此方案中只能存在一个待处理信号。
至少有2种可设计微控制器微程序的一般操作范例。一种是优化总体的微控制器计算吞吐量和总体的存储器带宽,其代价是花费一个线程执行等待时间。当系统具有对非相关数据分组执行每一微引擎多线程的多重微引擎时,此范例会有意义。
第2种范例是以总体的微引擎计算吞吐量和总体存储器带宽的代价来优化微引擎执行等待时间。此范例涉及以实时约束执行线程,该约束支配按某规定时间必须绝对完成的某工作。这种约束要求给单一线程执行的优化比诸如存储器带宽或总体计算吞吐量之类其他考虑高的优先级。实时线程隐含仅执行一个线程的单一微引擎。目标是使单一实施线程尽快执行,而多线程的执行妨碍此性能,所以不处理多线程。
在发布存储器指针和环境切换方面,这2种范例的编码方式显著不同。在实时情况下,目标是尽快发布尽量多的存储器指针,以便使这些指针所带来的存储器等待时间最短。已尽量提早发布尽量多的指针,目标是微引擎与指针尽可能并行执行尽量多的计算。与实时优化时相对应的计算流是:
o)发布存储器指针1
o)发布存储器指针2
o)发布存储器指针3
o)进行与存储器指针1、2、3无关的工作
o)与存储器指针1的完成同步
o)进行取决于存储器指针1且与存储器指针2和3无关的工作
o)根据前面的工作发布新存储器指针
o)与存储器指针2的完成同步
o)进行取决于存储器指针1和2且与存储器指针3无关的工作
o)根据前面的工作发布新存储器指针
o)与存储器指针3的完成同步
o)进行取决于全部3个指针完成的工作
o)根据前面的工作发布新存储器指针
反之,对吞吐量和带宽的优化则采取不同方法。对微引擎计算吞吐量和总体存储器带宽而言,不考虑单线程执行等待时间。为了实现这点,目标是对每一线程在微程序上均匀分隔存储器指针。这将给SRAM和SDRAM的控制器提供均匀的存储器指针流,并且使总可获得一线程的概率最大,以隐去换出另一线程时带来的存储器等待时间。
寄存器文件地址类型
参照图3C,所存在的2个寄存器地址空间是局部可存取寄存器和全部微引擎均可存取的全局可存取寄存器。通用寄存器(GRP)做成2个分开组(A组和B组),其地址逐字交错,使得A组寄存器具有LSB=0,B组寄存器具有LSB=1。每组可进行本组内2个不同字的同时读写。
整个组A和组B上,寄存器集合76b也组织成每一线程具有可相对寻址的32个寄存器的4个窗76b0~76b3。因此,线程0在77a(寄存器0)找到其寄存器0,线程1在77b(寄存器32)找到其寄存器0,线程2在77c(寄存器64)找到其寄存器0,线程3在77d(寄存器96)找到其寄存器0。支持相对寻址,以便多线程能准确使用相同的控制存储器和位置,但访问不同的宁寄存器窗,并执行不同功能。寄存器窗寻址和寄存器组寻址的使用,仅在以微引擎22f中以双端口RAMS提供必要的读带宽。
这些开窗的寄存器不需要保存环境切换之间的数据,从而消除环境对换文件或堆栈的常规推入和推出。这里环境切换对从一环境到另一环境的变化具有0周期的开销。相对寄存器寻址将寄存器组划分成跨越通用寄存器集合地址宽度的窗。相对寻址允许访问相对于窗起始点的任何窗。此体系结构内也支持绝对寻址,其中,通过提供寄存器的准确地址,任何线程可访问任一绝对寄存器。
通用寄存器48的寻址可出现2种方式,取决于微字格式。这2种方式是绝对方式和相对方式。绝对方式中,在7位源段(a6~a0或b6~b0)直接指定寄存器地址的寻址:
7 6 5 4 3 2 1 0
+…+…+…+…+…+…+…+…+
A GPR: |a6|0|a5|a4|a3|a2|a1|a0| a6=0
B GPR: |b6|1|b5|b4|b3|b2|b1|b0| b6=0
SRAM/ASB:|a6|a5|a4|0|a3|a2|a1|a0| a6=1,a5=0,a4=0
SDRAM: |a6|a5|a4|0|a3|a2|a1|a0| a6=1,a5=0,a4=1
在8位宿段(d7~d0)直接指定寄存器地址:
7 6 5 4 3 2 1 0
+…+…+…+…+…+…+…+…+
A GPR: |d7|d6|d5|d4|d3|d2|d1|d0| d7=0,d6=0
B GPR: |d7|d6|d5|d4|d3|d2|d1|d0| d7=0,d6=1
SRAM/ASB:|d7|d6|d5|d4|d3|d2|d1|d0| d7=1,d6=0,d5=0
SDRAM: |d7|d6|d5|d4|d3|d2|d1|d0| d7=1,d6=0,d5=1
若<a6:a5>=1,1,<b6:b5>=1,1或<d7:d6>=1,1,低端位便变换成环境相对地址字段(下文说明)。当A、B绝对字段指定非相对A或B源地址时,仅能对SRAM/ASB和SDRAM地址空间的低端半部分寻址。实际上,读绝对方式的SRAM/SDRAM具有有效地址空间。但由于该限制不适用宿段,写SRAM/SDRAM可用全地址空间。
相对方式中,在按5位源段(a4~a0或b4~b0)规定的环境空间内偏置指定地址的寻址:
7 6 5 4 3 2 1 0
+…+…+…+…+…+…+…+…+
A GPR: |a4|0|环境|a2|a1|a0| a4=0
B GPR: |b7|1|环境|b2|b1|b0| b4=0
SRAM/ASB:|ab4|0|ab3|环境|b1|ab0| ab4=1,ab3=0
SDRAM: |ab4|0|ab3|环境|b1|ab0| ab4=1,ab3=1
或者在按6位宿段(d5~d0)规定的环境空间内偏置指定地址的寻址:
7 6 5 4 3 2 1 0
+…+…+…+…+…+…+…+…+
A GPR: |d5|d4|环境d2|d1|d0| d5=0,d4=0
B GPR: |d5|d4|环境|d2|d1|d0| d5=0,d4=1
SRAM/ASB:|d5|d4|d3|环境|d1|d0| d5=1,d4=0,d3=0
SDRAM: |d5|d4|d3|环境|d1|d0| d5=1,d4=0,d3=1
如果<d5:d4>=1,1,则宿地址找不到有效寄存器,因而不回写宿操作数。
从微引擎和存储控制器可全局存取以下寄存器:
散列单元寄存器
便笺和共用寄存器
接收FIF0和接收状态FIFO
发送FIFO
发送控制FIFO
不中断驱动微引擎。执行每一微流直到完成为止,根据处理器12中其他装置用信号通知的状态选择一新流。
参照图4,SDRAM存储控制器26a包含存储器指针队列90,其中存储器指针请求从各微引擎22a~22f到达。存储控制器26a包括一仲裁器91,该仲裁器选择下一微引擎指针请求至任何功能单元。设一个微引擎提出访问请求,该请求会来到SDRAM控制器26a内部的地址和命令队列90。若该访问请求具有称为A经优化存储位@的位集合,便将进入的指针请求分类为偶数组队列90a或奇数组队列90b。若存储器指针请求没有存储器优化位集合,系统设定就转入一排序队列90c。SDRAM控制器26是一FBUS接口28、核心处理器20和PCI接口24所共用的资源。SDRAM控制器26还维持一用于执行读出-修改-写入自动操作的状态机。SDRAM控制器26还对SDRAM的数据请求进行字节对准。
命令队列90c保持来自微引擎的指针请求的排序。根据一系列奇数和偶数组指针,可要求信号仅在指向偶数组和奇数组两者的存储器指针序列完成时返回信号。若微引擎22f将存储器指针分类成奇数组指针和偶数组指针,并且存储器指针在奇数组前漏出其中一个组(例如偶数组),但在最后的偶数指针上信号肯定,便可想象存储控制器26a可返回信号通知微引擎已完成存储器请求,即使奇数组指针不提供服务也这样。这种现象可造成一相干问题。通过提供排序队列90c使微引擎可让多个待处理存储器指针中仅最后的存储器指针通知完成,从而可避免上述情况。
SDRAM控制器26a还包含高优先级队列90d。高优先级队列90d中,来自一个微引擎的输入存储器指针直接进入高优先级队列,并且以高于其他队列中其他存储器指针的优先级进行工作。偶数组队列90a、奇数组队列90b、命令队列90c和高优先级队列90d,所有这些队列都在一个RAM结构中实现。该结构逻辑上分成4个不同的窗,各窗分别具有其本身首部和尾部指针。由于填入和漏出操作仅是单一输入和单一输出,可将它们置于同一RAM结构以提高RAM结构密度。
SDRAM控制器26a还包括核心总线接口逻辑即ASB总线92。ASB总线接口逻辑92形成核心处理器20与SDRAM控制器26a的接口。ASB总线是一包含32位数据通路和28位地址通路的总线。通过MEM ASB数据设备98(例如缓存器)对存储器存取数据。MEM ASB数据设备98是一写数据队列。若有从核心处理器20经ASB接口92进入的数据,该数据可存入MEM ASB设备98,接着通过SDRAM接口110从MEM ASB设备98移至SDRAM存储器16a。虽然未示出,但可对读出提供相同的队列结构。SDRAM控制器26a还包括一引擎97从微引擎和PCI总线拉进数据。
附加队列包括保持若干请求的PCI地址队列94和ASB读/写队列96。存储器请求经复用器106送至SDRAM接口110。复用器106由SDRAM仲裁器91控制,该仲裁器检测各队列满员程度和请求状态,并根据优先级业务控制寄存器100存放的可编程值,从所检测的情况判定优先级。
一旦对复用器106的控制选择一存储器指针请求,就将此存储器指针请求送至一译码器108对其进行译码,并生成一地址。该经过解码的地址送至SDRAM接口110,将其分解成行地址和列地址选通信号来存取SDRAM16a,并通过将数据送至总线112的数据线16a读出或写入数据。一实施例中,总线112实际上是2条分开的总线,而不是单一总线。该分开的总线会包含连接分布式微引擎22a~22f的读出总线和连接分布式微引擎22a~22f的写入总线。
SDRAM控制器26a其特征在于,在队列90中存储存储器指针时,除可设定该经优化存储位外,还有A链接位@。该链接位当其设定时允许对邻接存储器指针专门处理。如上文所述,仲裁器12控制选择哪一微引擎在命令总线上将存储器指针请求提供给队列90(图4)。对链接位的肯定将控制仲裁器使之选择先前请求该总线的功能单元,这是因为对链接位的设定表明微引擎发出一链接请求。
设定链接位时,会按队列90接收邻接存储器指针。由于邻接存储器指针是来自单一线程的多存储器指针,这些邻接指针通常按排序队列90c存储。为了提供同步,存储控制器26a仅需要在完成时在链接存储器指针未端给出信号。但经优化存储器链接中,(例如经优化存储位和链接位设定时)存储器指针便会进入不同组,并且在其他组充分露出前有可能对发布信号A完成@的其中一个存储组完成,这样就破坏相干性。因此,控制器110用链接位保持来自当前队列的存储器指针。
参照图4A,示出SDRAM控制器26a中仲裁策略的流程表示。仲裁策略优待链接微引擎存储器请求。处理过程115通过链接微引擎存储器指针请求的检查115a开始进行。过程115停留于链接请求,直到使链接位清零。过程对后面接着PCI总线请求115c、高优先级队列业务115d、相对组请求115e、排序队列请求115f和相同组请求115g的ASB总线请求115b进行检查。对链接请求提供完整的业务,而对业务115b~115d则按循环顺序提供。仅当业务115a~115d完全漏出时,该过程才进行业务115e~115g的处理。当先前SDRAM存储器请求对链接位设定时,设定所链接的微引擎存储器指针请求。当设定链接位时,仲裁引擎便再次仅对相同队列服务,直到链接位清零。ASB处于等待状态时对Strong Arm核心带来严重性能损失,故ASB优先级高于PCI。因为PCI的等待时间要求,PCI优先级高于微引擎。但就其他总线而言,该仲裁优先级可能不同。
如图4B所示,示出的是不具有有效存储器优化和具有有效存储器优化的典型存储器定时。可以知道,对有效存储器优化的利用使总线应用程度最大,从而隐去实际SDRAM装置内固有的等待时间。本例中,非优化存取可用14周期,而优化存取则可用7周期。
参照图5,其中示出SRAM的存储控制器26b。该存储控制器26b包括一地址及命令队列120。存储控制器26a(图4)具有一基于奇数和偶数分组的存储器优化队列,存储控制器26b则根据存储器操作类型(即读出或写入)优化。地址及命令队列120包括一高优先级队列120a、一作为SRAM执行的主导存储器指针功能的读队列120b、以及一通常包括要非优化的全部SRAM读写的排序队列120c。尽管未图示,地址及命令队列120也可包括一写队列。
SRAM控制器26b还包括核心总线接口逻辑即ASB总线122。ASB总线接口逻辑122形成核心处理器20与SRAM控制器26b的接口。ASB总线是一包括32位数据通路和28位地址通路的总线。通过MEM ASB数据设备128(例如缓存器)对存储器存取数据。MEM ASB数据设备128是一写数据队列。若有从核心处理器20通过ASB接口122的进入数据,该数据可存入MEM ASB设备128,接着通过SRAM接口140从MEM ASB设备128移至SRAM存储器16b。虽未图示,但可提供相同的队列结构用于读出。SRAM控制器26b还包括一引擎127从微引擎和PCI总线拉进数据。
存储器请求经复用器126送至SDRAM接口140。复用器126由SDRAM仲裁器131控制,该仲裁器检测各队列满员程度和请求状态,并根据优先级业务控制寄存器130存放的可编程值,从所检测的情况判定优先级。一旦对复用器126的控制选择一存储器指针请求,就将此存储器指针请求送至一译码器138对其进行译码,并生成一地址。SRAM单元保持对经存储器映射的离片SRAM和扩展ROM的控制。SRAM控制器26b可对例如16M字节寻址,而例如用于SRAM16b的8M字节映射保留用于专用功能,其中包括通过快速擦写ROM16的引导空间;MAC器件13a、13b用的控制台端口存取访问;以及对关联(RMON)计数器的存取。SRAM用于局部查找表和队列管理功能。
SRAM控制器26b支持下列事务:
微引擎请求 (经专用总线) 至/自SRAM
核心处理器 (经ASB总线) 至/自SRAM。
SRAM控制器26b进行存储器指针分类以使SRAM接口140至存储器16b的流水线中延迟(空泡)最少。SRAM控制器26b根据读功能进行存储器指针分类。一个空泡可以是1周期或者2周期,取决于所用存储器件的类型。
SRAM控制器26b包括一锁定查找器件142,是一8输入项地址内容可寻址存储器用于对读出锁定的查找。每一位置包括一由后续读出-锁定请求检查的有效位。地址及命令队列120还包括一读出锁定失效队列120d。该队列120d用于保持因存储器一部分存在锁定而失效的读存储器指针请求。也就是说,其中一个微引擎所发布的存储器请求所具有的读出锁定请求在地址及控制队列120中处理。该存储器请求将对排序队列120c或读队列120b运作,并将其识别为读出锁定请求。控制器26b将存取锁定查找器件142以判断该存储位置是否已经锁定。若此存储位置根据任何先前的读出锁定请求而被锁定,该存储锁定请求将失效,并将存入读出锁定失效队列120d。若解锁或者142表示该地址未锁定,SRAM接口140就将用该存储器指针的地址对存储器16b进行常规的SRAM地址读/写请求。命令控制器及地址发生器138也会将该锁定输入锁定查找器件142,以便后续读出锁定请求将发现该存储位置被锁定。锁定需要结束后通过对程序中微控制指令的运作来使存储位置解锁。通过对CAM中有效位清零将该位置解锁。解锁后,读出锁定失效队列120d变成最高优先级队列,给丢失的全部排队的读出锁定一次机会发出一存储器锁定请求。
如图5A所示,示出的是没有有效存储器优化和具有有效存储器优化的静态随机存取存储器的典型时序。可以知道,分组读写改善消除死周期的周期时间。
参照图6,示出的是微引擎22和FBUS接口逻辑(FBI)之间的通信。网络应用中的FBUS接口28可对来自FBUS18的来向数据分组进行首部处理。FBUS接口28所进行的一项关键功能是对数据分组首部的提取和对SRAM中可微编程源/宿/协议散列查找。若该散列不能成功分辨,数据分组首部就提升至核心处理器28用于更为高级的处理。
FBI 28包含发送FIFO 182、接收FIFO 183、散列单元188以及FBI控制及状态寄存器189。这4个单元通过对微引擎中与传送寄存器78、80连接的SRAM总线28的时间复用存取与微引擎22通信。也就是说,全部对微引擎的收发通信都通过传送寄存器78、80。FBUS接口28包括一用于在SRAM不用SRAM数据总线(部分总线38)的时间周期期间将数据推入传送寄存器的推状态机200以及一用于从相应微引擎中的传送寄存器当中读取数据的拉状态机202。
散列单元包括一对FIFO 18a、188b。该散列单元判定FBI 28收到一FBI散列请求。散列单元188从进行调用的微引擎22当中取得散列键。读取该键并散列后,将索引号送回进行调用的微引擎22。在单个FBI散列请求下,进行多达3次散列。总线34和38均为单向:SDRAM推/拉数据总线以及S总线推/拉数据总线。上述总线每一条需要对适当微引擎22的传送寄存器提供读/写控制的控制信号。
传送寄存器通常要求保护其环境控制以保证读出的正确性。具体来说,若线程1用写传送寄存器对SDRAM 16a提供数据,线程1必须等到SDRAM控制器16a返回的信号表明该寄存器已提升并可重新使用才重写此寄存器。每次写均不需要表明已经完成该功能的目的地所返回的信号,其原因在于若该线程用多个请求对该目的地的相同命令队列写入,该命令队列内确保完成命令,因而仅最后的命令需要将信号传回该线程。但若该线程采用多个命令队列(排序和读出),这些命令请求就必需分解成独立的环境任务,以便通过环境对换保持排序。本节开头提出的特例涉及对FBUS状态信息采用FBI至传送寄存器的非请求型推(PUSH)的某类操作。为了保护传送寄存器的读/写判定,FBI当设定这些专用FBI推操作时提供一专用的推保护信号。
采用FBI非请求型推方法的任何微引擎22必须在存取传送寄存器同意的FBUS接口/微引擎前测试该保护标志。若该标志并非肯定,该微引擎便可存取传送寄存器。若该标志肯定,则存取寄存器前环境应等待N周期。根据所推的传送寄存器个数加上前端保护窗,确定先验的此计数。基本思想是,微引擎必须测试此标志,然后以连续周期快速将希望从所读传送寄存器读出的数据移到GPR,因而推引擎不与微引擎读出冲突。
其他实施例
应理解,虽然结合详细说明描述了本发明,但上述描述用于说明,并非限定本发明范围,该范围由所附权利要求的范围限定。其他方而、优点和修改均在以下权利要求书范围内。
Claims (18)
1.一种随机存取存储器用控制器,其特征在于,包括:
一保持来自多个微控制功能单元的存储器指针的地址和命令队列;
一保持来自计算机总线的存储器指针的第1读/写队列;
一保持来自核心处理器的存储器指针的第2读/写队列;
一包含仲裁器的控制逻辑,该仲裁器检测每一队列的满员程度和待处理存储器指针的状态,以便从其中一个队列选择一存储器指针。
2.如权利要求1所述的控制器,其特征在于,控制逻辑进一步根据优先级业务控制寄存器中存储的可编程值选择其中一个队列以提供下一存储器指针。
3.如权利要求1所述的控制器,其特征在于,地址和命令队列包括:
保持来自高优先级任务的存储器指针的高优先级队列。
4.如权利要求1所述的控制器,其特征在于,地址和命令队列包括:
偶数组队列;
奇数组队列;
其中,微引擎将存储器指针分类为奇数组指针和偶数组指针。
5.如权利要求1所述的控制器,其特征在于,地址和命令队列包括:
一排序队列,而且
控制器检查经过优化的存储器指针位,若设定该位,便将进入的指针请求分类为偶数组队列或奇数组队列。
6.如权利要求5所述的控制器,其特征在于,地址和命令队列包括:
一排序队列,而且
若存储器指针请求未设定存储器优化位,便将该存储器指针存入该排序队列。
7.如权利要求1所述的控制器,其特征在于,地址和命令队列在单一存储器结构中实施,并且包括:
一保存存储器指针的排序队列;
一保存存储器指针的偶数组队列:
一保存存储器指针的奇数组队列;
一保存存储器指针的高优先级队列,而且
该存储器结构分区为4个不同队列区,每区具有其本身的首部及尾部指针。
8.如权利要求7所述的控制器,其特征在于,地址和命令队列进一步包括:
一插入队列控制逻辑和移出队列仲裁逻辑,对队列当中存储器指针的插入和移出进行控制。
9.如权利要求1所述的控制器,其特征在于,进一步包括:
一命令控制器和地址生成器,响应来自从其中一个所述队列当中选定的存储器指针的地址,生成地址和命令以控制存储器接口。
10.如权利要求9所述的控制器,其特征在于,进一步包括:
一存储器接口,响应所生成的地址和命令以产生存储器控制信号。
11.如权利要求1所述的控制器,其特征在于,该控制逻辑响应一链接位,该链接位设定时,允许对邻接的存储器指针进行专门处理。
12.如权利要求1所述的控制器,其特征在于,链接位的肯定将控制仲裁器,使该仲裁器因表明微引擎发出过链接请求的链接位设定而选择先前请求该总线的功能单元。
13.如权利要求1所述的控制器,其特征在于,控制逻辑响应一经过优化的存储位和链接位,而且链接位的肯定当经过优化的存储位也设定时,控制仲裁器以保存来自当前队列的存储器指针。
14.如权利要求1所述的控制器,其特征在于,仲裁器具有一对所链接的微引擎提供存储器指针的仲裁策略。
15.如权利要求14所述的控制器,其特征在于,仲裁器具有一为链接请求提供服务直到链接位清零为止的仲裁策略。
16.如权利要求1所述的控制器,其特征在于,仲裁器具有一通过对所链接的微引擎检查存储器指针请求来起动的仲裁策略。
17.如权利要求16所述的控制器,其特征在于,该仲裁策略使所链接的存储器请求能够得到完全的服务。
18.如权利要求16所述的控制器,其特征在于,当链接位设定时,仲裁引擎便对该同一队列再次提供服务,直到该链接位清零为止。
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CN100367257C (zh) | 2008-02-06 |
HK1049899A1 (en) | 2003-05-30 |
HK1049899B (zh) | 2008-12-24 |
US7424579B2 (en) | 2008-09-09 |
ATE262197T1 (de) | 2004-04-15 |
EP1214661B1 (en) | 2004-03-17 |
US20090024804A1 (en) | 2009-01-22 |
US20060069882A1 (en) | 2006-03-30 |
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