CN1300831C - 硅片imd cmp后成膜方法 - Google Patents

硅片imd cmp后成膜方法 Download PDF

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Publication number
CN1300831C
CN1300831C CNB2003101226844A CN200310122684A CN1300831C CN 1300831 C CN1300831 C CN 1300831C CN B2003101226844 A CNB2003101226844 A CN B2003101226844A CN 200310122684 A CN200310122684 A CN 200310122684A CN 1300831 C CN1300831 C CN 1300831C
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cmp
film
silicon wafer
pco
imd
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CN1632928A (zh
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殷建斐
张震宇
蔡晨
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Abstract

本发明公开了硅片IMD CMP后成膜方法，旨在提供一种缩短硅片成产周期，使硅片金属配线间的绝缘层氧化膜平坦化，从而提高集成电路产品质量的方法。其技术方案的要点是：根据硅片IMD CMP后残膜的厚度，自动选择相应的PCO成膜条件；其中，所述自动选择相应的PCO成膜条件是根据CMP残膜厚度与之后PCO不同成膜条件相对应的表格来完成的。

Description

硅片IMD CMP后成膜方法
技术领域
本发明涉及一种半导体制造工艺方法，尤其是涉及一种硅片IMD CMP后成膜方法。
背景技术
随着半导体制造技术的不断提高，出现了多层布线技术，它使得器件大小及线宽不断缩小，大大提高了半导体器件的集成度。但多层布线的出现，导致了硅片表面出现了较大的段差，凹凸不平，造成了金属配线不良及后序光刻对焦上的困难。为了解决这一问题，引入了CMP(化学机械平面化)工艺。它是通过化学反应和机械研磨抛光的作用，使硅片表面的凹凸不平趋于平坦化，而IMD CMP(金属层间介质层化学机械平面化)工艺，就是利用该方法，使硅片上的金属配线间的绝缘层氧化膜变得平坦，提高了集成电路产品的质量。在IMD CMP工艺中，由于CMP设备的研磨速率变动较大，而且在CMP之前成长IMD的设备存在作业腔间差，造成了CMP工程后残膜经常会超出规格，而传统工艺在CMP工程后采用固定的PCO(成长氧化膜)成长条件，使得必须通过返工将残膜的厚度修正到规格范围内，才能保证之后的VIA(接触孔)刻蚀厚度的稳定性。这样不但延长了产品的生产周期，同时也增加了CMP设备和PCO设备的负荷率。
发明内容
本发明的目的在于针对现有技术的上述不足，提出一种缩短硅片生产周期，使硅片金属配线间的绝缘层氧化膜平坦化，从而提高集成电路产品质量的成膜方法。
本发明的上述目的是通过下述技术方案实现的：根据硅片IMP CMP后残膜的厚度，自动选择相应的PCO成膜条件。其中，所述的自动选择相应的PCO成膜条件是根据CMP残膜厚度与之后PCO不同成膜条件相对应的表格完成的。
和现有技术相比，本发明具有以下有益效果：
1、由于自动选择相应的PCO成膜条件，使得产品生产周期变短；
2、保证经PCO成膜后的氧化膜厚度基本处于同一水平，使得VIA刻蚀相对稳定，提高了产品质量。
具体实施方式
下面结合实施例对本发明作进一步描述。
在硅片IMD CMP后，根据CMP后残膜厚度，自动选择相应的PCO(成长氧化膜)成膜条件。即CMP之后残膜厚度若较厚，则选择成膜量较少的PCO条件；若CMP之后残膜厚度偏薄，则选择相应的成膜量较多的PCO(成长氧化膜)条件。从而辩证经PCO成膜后的氧化膜基本处于同一水平，使得VIA(接触孔)刻蚀相对稳定。
具体而言，在硅片IMD CMP后，对PCO成膜条件进行细分，分别与某一特定范围内的CMP残膜厚度相对应，制成一张表格。如下表：
  CMP残膜厚度   PCO成膜条件
  3000-3499   A(成长量为5000)
  3500-3999   B(成长量为4500)
  4000-4499   C(成长量为4000)
  4500-4999   D(成长量为3500)
  5000-5499   E(成长量为3000)
例如：产品规格为PCO成长后氧化膜厚度中心值为8000。当一产品经CMP后残膜厚度为4100，则由APC(高级进程控制)系统，根据表格自动选择条件为C的成长量为4000的PCO成长条件。
在制作产品工艺流程中，将CMP研磨后的膜厚测定工序设置为原工程，将之后的氧化膜成长工序设置为目标工程。即在膜厚测定数据未得到时，该氧化膜成长工序的作业条件为未知；当膜厚测定正常结束后，根据膜厚值，从事先设定的对应表格中选择相应的成长条件，并修改该工序的作业条件，从而实现根据不同残膜厚度成长不同的氧化膜，保证成长后的膜厚值在同一水平。

Claims (1)

1、一种设置硅片IMD CMP后成膜方法，其特征在于，根据硅片IMD CMP后残膜的厚度，自动选择相应的PCO成膜条件；其中，所述自动选择相应的PCO成膜条件是根据CMP残膜厚度与之后PCO不同成膜条件相对应的表格来完成的。
CNB2003101226844A 2003-12-24 2003-12-24 硅片imd cmp后成膜方法 Expired - Fee Related CN1300831C (zh)

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CN1300831C true CN1300831C (zh) 2007-02-14

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1210364A (zh) * 1997-06-27 1999-03-10 西门子公司 用bpsg回流去除cmp划痕的方法和用其制成的集成电路芯片
CN1248059A (zh) * 1998-09-17 2000-03-22 世大积体电路股份有限公司 平坦的金属层间介电层或内层介电层的制造方法
US6057603A (en) * 1998-07-30 2000-05-02 Advanced Micro Devices, Inc. Fabrication of integrated circuit inter-level dielectrics using a stop-on-metal dielectric polish process
US6291339B1 (en) * 1999-01-04 2001-09-18 Advanced Micro Devices, Inc. Bilayer interlayer dielectric having a substantially uniform composite interlayer dielectric constant over pattern features of varying density and method of making the same
US6451687B1 (en) * 2000-11-24 2002-09-17 Chartered Semiconductor Manufacturing Ltd. Intermetal dielectric layer for integrated circuits
US6569729B1 (en) * 2002-07-19 2003-05-27 Taiwan Semiconductor Manufacturing Company Method of fabricating three dimensional CMOSFET devices for an embedded DRAM application

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1210364A (zh) * 1997-06-27 1999-03-10 西门子公司 用bpsg回流去除cmp划痕的方法和用其制成的集成电路芯片
US6057603A (en) * 1998-07-30 2000-05-02 Advanced Micro Devices, Inc. Fabrication of integrated circuit inter-level dielectrics using a stop-on-metal dielectric polish process
CN1248059A (zh) * 1998-09-17 2000-03-22 世大积体电路股份有限公司 平坦的金属层间介电层或内层介电层的制造方法
US6291339B1 (en) * 1999-01-04 2001-09-18 Advanced Micro Devices, Inc. Bilayer interlayer dielectric having a substantially uniform composite interlayer dielectric constant over pattern features of varying density and method of making the same
US6451687B1 (en) * 2000-11-24 2002-09-17 Chartered Semiconductor Manufacturing Ltd. Intermetal dielectric layer for integrated circuits
US6569729B1 (en) * 2002-07-19 2003-05-27 Taiwan Semiconductor Manufacturing Company Method of fabricating three dimensional CMOSFET devices for an embedded DRAM application

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