CN1295876C - 磁逻辑元件 - Google Patents

磁逻辑元件 Download PDF

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CN1295876C
CN1295876C CNB008156808A CN00815680A CN1295876C CN 1295876 C CN1295876 C CN 1295876C CN B008156808 A CNB008156808 A CN B008156808A CN 00815680 A CN00815680 A CN 00815680A CN 1295876 C CN1295876 C CN 1295876C
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logic device
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CN1390388A (zh
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拉塞尔·考苯
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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/02Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
    • G11C19/08Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
    • G11C19/0808Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure using magnetic domain propagation
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y25/00Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/16Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices
    • H03K19/168Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices using thin-film devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/195Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/81Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00Nanotechnology
    • Y10S977/902Specified use of nanostructure
    • Y10S977/932Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/94Specified use of nanostructure for electronic or optoelectronic application in a logic circuit

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  • Nanotechnology (AREA)
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  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
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  • Design And Manufacture Of Integrated Circuits (AREA)
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Abstract

一种由磁性材料的至少一个点链形成的逻辑装置。每个点具有200nm或更小的宽度,并且被分隔开一足够小的距离,以确保相邻点的磁相互作用。

Description

磁逻辑元件
技术领域
本发明涉及通过实现磁量子点特性而得到的逻辑电路。
背景技术
在过去四十年中,诸如微处理器的硅电子器件的集成密度一直遵循稳定的指数增长。尽管硅集成度仍然具有很大的未来增长潜力,最终将会到来集成密度不可能进一步增长的时刻。因而需要提供另一种可供选择的数字逻辑。想象中,人们可能会转向分子电子学,其中使用单个分子或原子作为逻辑门并相互连接。不过,在该领域中有大量的技术和学术困难需要克服,以致它不可能直接取代硅电子学。近来,人们已经将更多的注意力放在电子量子点和单电子晶体管上,作为在传统的硅器件以外用于继续增加集成密度的选择。一种称为量子细胞自动机(aquantum cellular automaton-QCA)的量子点的尤为吸引人的结构,已经表现出执行逻辑运算的能力。遗憾的是,目前这些器件仅工作在非常低的温度下。
发明概述
根据本发明,提供一种由磁材料的至少一个点链形成的逻辑装置,每个点具有200nm或更小的宽度,并被分隔开一足够小的距离,以确保相邻点的磁相互作用。该点可以为100nm或更小,或者为80nm或更小。
该点可以具有圆形、椭圆形或它们的组合。
该点可以由软磁材料如铁镍合金(Ni80Fe20)或CoFe形成。
该点可以形成在由诸如Si材料制成的基板上。
该逻辑装置还可以包括用于向点链提供一或多个受控磁场的装置。该用于提供磁源的装置可以包括用于控制该磁源的装置,使得该磁场可以作为控制时钟运作。在该装置中可以设置多个链,以提供“或”门,“与”门,“非”门或它们的组合,或者其它许多逻辑门中的任一个。通过进一步包括一或多个产生磁-电效应的元件,该装置可以提供一或多个电输出。
本发明提供采用磁量子点的QCA。该设计在高达铁磁金属的居里温度(~1000K)时能够良好的工作,并且可以用大到200nm或者小如10nm的点来实现。因而,本发明提供的磁量子细胞自动机(MQCA),能够填补传统的硅器件与分子电子学之间的空白。200nm的点使面集成密度(每个芯片的有效晶体管的数量)比当今的CMOS增加了400倍;10nm的点使表面集成密度增加了160000倍。而且,与当前的CMOS工艺相比,用于MQCA器件的制造工艺相当简单。因而,根据本发明的MQCA能够完全改变IC制造的经济状况,允许不能够筹集到用于CMOS制造的资金(约20亿美圆)的较小的公司进入市场。此外,MQCA作为全磁器件,随时准备着面对刚出现的磁随机存取存储器(MRAM)技术,将来MRAM将代替所有的半导体计算机存储器。
附图说明
现在,将参照附图描述本发明的一个实施例,其中:
图1为根据本发明结合多种原理的逻辑装置的示意图;
图2为示意图,表示根据本发明的逻辑元件中的孤立子缺陷;
图3表示根据本发明的逻辑互连接如何相互交叉而无不利的相互干扰;
图4A,4B和4C为示意图,表示如何将本发明的例子构造成提供阻抗匹配;以及
图5表示根据本发明,如何通过改变链分裂处附近点的厚度获得信号扇出(fan-out)。
具体实施方式
在描述本发明之前,提供一些背景技术是有用的。
近来,纳米大小的磁粒子(纳米磁体)已经成为科学和技术研究的主题。这些人造的0尺寸结构特别另人感兴趣,因为除了提供在其中研究磁性基本问题的极好的实验以外,对于诸如用于计算机的超高密度硬盘媒体和非易失存储器的未来技术应用而言,它们是非常有前途的选择。
纳米磁体的众多用途产生于称为Brown基本理论的原理,该理论指出,因为静磁能与量子机械交换能之间的竞争,磁畴结构会被整个压缩成一个非常小(~10-8m)的磁粒子,导致纳米磁体相当于单个巨型螺旋。近来,已经实验证实,该理论在平面圆形铁磁盘中是正确的。从而,有可能通过实验实现几千波尔磁子的孤立的平面偶极矩。通过选择纳米磁体的几何形状,可以另外选择优选的面内方向(各向异性)。即使在100nm远的距离处,从该巨型螺旋发出的磁场也能够达到几十奥斯特。将其与kT/m,可表示为室温下1Oe附近的磁场的热涨落能量(对于75nm直径,10nm厚的铁镍合金盘而言)进行比较。从而可以使纳米磁体在比热下限(thermal floor)更高的能级上静磁相互作用,即使在室温和更高温度下也是如此。
(i)逻辑状态
图1表示根据本发明的MQCA示意图。将各向同性铁磁材料的圆形单畴盘设置成足够小的间距,以使最邻近的盘共享强静磁相互作用。典型的尺寸为80nm直径,15nm厚的盘设置成115nm间隔。在这种情形中,可以将每个盘表示为一巨型平面螺旋。盘的圆形形状确保孤立的螺旋具有各向同性能量表面。不过,偶极子耦合是各向异性的,从而两个相邻螺旋最好沿着它们的中心连线指向。因而,图1中所示的点链是双稳态的:一个链中所有的螺旋能够沿该链指向,不过不与该链横切。该链使用工作在+1和-1而不是1和0的布尔代数的变量表示逻辑状态。在水平链的情形中,我们定义指向左边的螺旋处于状态-1,指向右边的螺旋为状态+1。在竖链的情形中,我们定义向下指向页面的螺旋处于状态-1,向上指向页面的螺旋处于状态+1。
(ii)孤立子传输
现在假定我们将链中一半螺旋设置为状态+1,另一半为状态-1,如图2示意地所示。这两个状态在链的中心处相遇,形成缺陷(defect)。为了简化,我们已经在图2中以点状画出该缺陷,即从状态-1到+1的转变突然发生。实际上,该缺陷具有这样一种结构,即将在几个点的空间上发生状态转变。现在假设施加一个小场,沿链长度的方向取向。这将具有施加给处于+1状态的螺旋的能量超过处于-1状态的螺旋的效果。远离该缺陷的处于状态-1的螺旋,由于它们最近邻螺旋的相互作用场保持不变,从而不改变方向。不过,缺陷处的-1螺旋受到零的净相互作用,这是因为来自其+1相邻螺旋的相互作用场被来自其-1相邻螺旋的相互作用场抵消。从而,它可以自由地反向对准该场,导致缺陷向右移动一个单元。这反过来增加了与该场对准的单元数量,从而降低了系统的能量。然后,可以将同样的讨论应用于新的-1缺陷螺旋,从而缺陷再次移动,并且持续进行移动,直到缺陷到达了链的端部,在此处缺陷消失。此缺陷实际上是一个孤立子,即被限定在一定的区域并能够通过施加的场而移动。孤立子载有拓扑荷:我们称图2中所示的孤立子为正的,因为它沿着施加场的正方向运动。处于从逻辑状态-1到+1转变的中间的孤立子,当向右移动时将载有负电荷,并将向所施加场的正方向的反方向运动(即,在图2中向左)。
因此,在这种MQCA设计中,通过弱振荡施加场驱动的磁孤立子,信号在其中传输。当所施加的场为正时,正的孤立子向右运动,负的孤立子向左运动。从而,这些拓扑带电的孤立子完全类似于半导体IC中所使用的电子和空穴。然而,不是在电场的作用下沿铝或铜导线流动,孤立子在一或多个磁场的作用下,沿耦合的磁量子点的网络传播。可以完全地向整个芯片施加磁场,同时作为每个点的电源(任何移动孤立子的能量都来自于所施加的场)并作为低时滞时钟。例如,将在该装置的平面中,从向上,到向左,到向下,到向右旋转的矢量磁时钟场,可以用于控制逻辑网络的同步操作,并用于在拐角附近和通过门路由信号。
(iii)数据输入
可以从椭圆的纳米磁体将数据放入链中,如图1的盒A中高亮显示所示。此椭圆形引入了形状各向异性,极大地增加了它的矫顽性。从而,仅能够通过强外部施加场(或者完全来自施加场,或者部分来自于载流轨道,如图1中点E所示)进行切换,并且不受来自圆形纳米磁体的相互作用场的影响。从而,孤立子不会在载有椭圆单元的链的端部消失;不过,它能够在链的自由端消失。这种非对称性保证在一个施加场周期以后,链中的每个单元将被设置成椭圆单元的逻辑状态,并将保持稳定不变。因此,椭圆单元起到输入管脚的作用,并将它们的逻辑状态向下传送到任何相连的链。或者,可以通过铁磁点接触施加高强度螺旋极化的电流脉冲而翻转点的磁状态。
(iv)逻辑门
通过将3个点链一起传送(pipe)可以构成逻辑门,如图1的盒B中所示。在这种情形中,来自左边的2个链为输入,离开右边的一个链为输出。节点受到来自链的相互作用场的矢量和,从而完成求和功能。用这种方法,通过施加偏置磁场,可以实现逻辑“与”或“或”功能。通过图1的盒D中所示的点设置,可以实现“非”功能。此处所描述的并且实际上贯穿整个方案中的逻辑门的一个重要特征在于逻辑信号可以反馈,以便进行锁定。从而,可以实现完全同步状态的机器。
(v)复杂网络
此设计不限于目前所讨论的线性链。如果在与x和y方向成45°处施加完全施加的磁场,那么能够沿x和y方向构成链,并在拐角处转向,如图1的盒C中所示。QCA和MQCA相对传统CMOS的一个主要优点在于链能够彼此交叉,如图3所示。在这种情形中,孤立子将无防碍地相互穿过。这样的结果是能够将大的、复杂的网络,如中央处理单元全部建立在单一平面上,不需要多层处理和路由(vias)。因而与CMOS相比,减小了制造成本(资本投入和每个单元的成本)。或者,可以使用相互作用点的多个平面获得三维逻辑硬件。通过使平面相隔一大于点直径的距离,可以使多个平面不相互作用(简单地用于增加单个芯片的复杂度)。相反,通过将平面相隔一小于点直径的距离,信号能够在平面之间通过。因而,可以很容易地实现信号在平面之间的“路由”。通过这种3维结构,可以很容易地增加装置的复杂度。
(vi)数据输出
利用磁电效应,如隧道磁电阻(Tunnel Magneto Resistance-TMR),在芯片的最后的输出部位(例如图1中点“F”),可以将逻辑信号从磁形式转变成电形式。
(vii)阻抗匹配
高频电路在每个接点处必须阻抗匹配,以避免反射。在MQCA中也存在类似的概念,不过不仅在高频下要求阻抗匹配。图4(a)说明了这种情形。假设链中两个点之间的间距比通常大,则导致在该点处发生较弱的耦合。这可能发生于拐角处或门设计中。现在假设孤立子从左向右传播。当孤立子到达弱耦合点时,由于点B受到点A的场并不足够强以补偿点B受到点C的场,所以孤立子的运动将受到阻碍。孤立子不能通过这个点传播,除非施加更大的驱动场,而施加更大的驱动场可能是不合乎需要的。通过使点B成轻微的椭圆形,孤立子向点B施加弱的各向异性。还可以向点A施加另一个相反符号的各向异性。图4(b)表示最终的结构。在这种情形中,从A到B的弱耦合被点B的各向异性场补偿。该结构的另一个吸引人的特征在于它是单方向的。从右向左传播的孤立子将受到增强的阻碍作用。从而,这种弱链接的接合点是孤立子二极管,可以用于控制MQCA系统中信号的路由。也可以通过点厚度改变耦合强度。图4c表示使用点厚度的突变来获得单方向性的孤立子二极管的另一种形式。每个点中的数字给出了用纳米表示的点厚度。
逻辑门扇出到多种其他门的输入是任何有用的逻辑系统的一个重要特征。相反,MQCA使用图1中盒B的结构能够获得扇出。在接近接合点的单元中可以引起小的各向异性,以实现阻抗匹配。这种各向异性的二极管效应可防止信号向回流入门的输出端。或者,可以通过逐渐改变链分裂附近的点厚度而获得扇出,如图5所示。每个点中的数字给出了以纳米为单位的点厚度。

Claims (10)

1.一种由磁性材料的至少一个点链形成的逻辑装置,每个点的宽度在10nm到200nm之间,并被分隔开一足够小的距离,以确保相邻点的磁相互作用。
2.根据权利要求1所述的逻辑装置,其中该点为100nm或更小。
3.根据权利要求1所述的逻辑装置,其中该点为80nm或更小。
4.根据权利要求3所述的逻辑装置,其中该点具有椭圆形状。
5.根据权利要求1到4所述的逻辑装置,其中该点由软磁材料形成。
6.根据前面任何一个权利要求所述的逻辑装置,其中该点形成在由硅制成的基板上。
7.根据前面任何一个权利要求所述的逻辑装置,进一步包括用于向点链提供受控磁场的装置。
8.根据权利要求7所述的逻辑装置,其中该用于提供磁场的装置包括用于控制该受控磁场装置的装置,使得该磁场可作为控制时钟运作。
9.根据权利要求8所述的逻辑装置,其中提供和设置多个链,以提供“或”门,“与”门,“非”门或其组合。
10.根据权利要求9所述的逻辑装置,其被设置来进一步包括一或多个产生磁电效应的元件,以提供电输出。
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