CN1286282C

CN1286282C - Method for processing transparent element in boundary scan interconnection test

Info

Publication number: CN1286282C
Application number: CNB021241570A
Authority: CN
Inventors: 游志强; 李颖悟
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2002-07-12
Filing date: 2002-07-12
Publication date: 2006-11-22
Anticipated expiration: 2022-07-12
Also published as: CN1467936A

Abstract

The present invention relates to a method for processing a transparent element in boundary scan interconnection tests, which is characterized in that the method comprises the following steps: a characteristic file of the transparent element is formed; the characteristic file is loaded into a test system; a net list is loaded into the test system; the test system searches the net list and finds the transparent elements according to the characteristic information of the transparent element; networks isolated by the transparent element are combined. The present invention mainly provides the method for automatically solving the problems of circuits, exclusion and driving chips of the interconnection tests. The present invention automatically acquires the information of direct connecting logic devices of a tested single board, such as resistors, exclusion, drivers, etc., by the compilation to net list files and device listing files of the tested single board, and consequently increases the network number capable of being tested of the boundary scan interconnection test and improves the fault coverage of the interconnection test of the single board.

Description

In a kind of boundary scan interconnecting test to the processing method of transparent element

Technical field

The present invention relates to the communications field, relate in particular in a kind of boundary scan interconnecting test processing method transparent element.

Technical background

Interconnecting test mainly be meant on the circuit board between the device interconnection line test, the faults such as open circuit, short circuit or dull type of main testing circuit plate level.Because in IEEE 1149.1 standards, interconnecting test instruction (EXTEST) is a mandatory instruction, and all BS devices are all supported interconnecting test.In the boundary scan interconnecting test, the resistance between boundary scanning device, exclusion and chip for driving are the key factors that influences fault coverage.

So-called transparent element is meant the element that has straight-through logical relation in the circuit board, mainly comprises resistance, exclusion and chip for driving etc.

On circuit board, we call a network to the number of pins that links together.Wherein have the fault of some networks to detect, but we are referred to as the survey grid network by the boundary scan interconnecting test, but but but wherein the survey grid network can be divided into directly survey grid network and survey grid network indirectly again.

Directly but the survey grid network is meant the network that comprises the BS pin that can import and an exportable BS pin on the circuit board at least.But network shown in Figure 1 is direct survey grid network.

But the survey grid network is meant the network that comprises a BS pin and a transparent element pin on the circuit board at least indirectly, but but it can be merged into directly survey grid network with other indirect survey grid network.Network among Fig. 2 and Fig. 3 all can be surveyed, but need regard network 1 and network 2 as a network, regard network 3 and network 4 as a network, ..., a kind of method of manual process is as follows: interface is provided, but by the indirect survey grid network information of being isolated by transparent element on user's typing circuit board, but but test macro is merged into directly survey grid network with indirect survey grid network again.

The advantage of this processing mode is flexibly, and shortcoming is complex operation, easily make mistakes, poor practicability.Manual input interface as shown in Figure 4.But but be associated with on the indirect survey grid network of another one by a pin with an indirect survey grid network, but such two indirect networks have just synthesized a direct survey grid network.

In the prior art, the boundary scan and test system VICTORY of TERADYNE company is a kind of application test macro more widely, and its treatment step is as follows:

At first need the manual compiling head that in the net table, adds.

Need to inspect the net table then, manual revise part of devices name in the net table, the device of all similar resistance is all renamed be R.Need simultaneously by hand exclusion device names all in the net table to be replaced by RP.

As seen, the processing method of VICTORY system has its superiority than manual process mode, can the batch processing transparent element.But this processing method that the VICTORY system provides but needs a special people to go to safeguard, and extensibility, portability are all not ideal enough.

Summary of the invention

The present invention is exactly at the shortcoming in the above-mentioned boundary scan interconnecting test technology, proposes the method for circuit, exclusion and chip for driving problem in a kind of automatic solution interconnecting test.

To the processing method of transparent components and parts, it is characterized in that may further comprise the steps in a kind of boundary scan interconnecting test:

Form the tag file of transparent element;

Tag file is loaded into test macro;

The net table is loaded into test macro;

Test macro is according to the characteristic information of transparent element, and the dragnet table finds transparent element;

To be merged by the network that transparent element is isolated;

Described transparent element tag file comprises the general feature file and the tag file of company level of transparent element;

The general feature file content of described transparent element comprises: element title, model and encapsulation;

Described tag file content of company level comprises: the tag file of describing the tag file of resistance, the tag file of describing exclusion and description chip for driving.

A general feature file can write down a kind of feature of transparent element, also can put down in writing the feature more than a kind of transparent element.

A tag file of company level can comprise a kind of feature of transparent element, also can comprise more than a kind of feature.

The present invention has mainly proposed the method for the problem of circuit, exclusion and chip for driving in a kind of automatic solution interconnecting test.That is: by compiling to tested single board net meter file, device list file, automatically obtain the information of the straight-through logical devices such as resistance, exclusion, 244 drivers and 245 drivers on the tested single board, but remove to increase the survey grid network number of boundary scan interconnecting test, improved the fault coverage of veneer interconnecting test.

Description of drawings

As shown in Figure 1, but be the direct schematic diagram of survey grid network;

As shown in Figure 2, but be because the schematic diagram of the indirect survey grid network that resistance exist to form;

As shown in Figure 3, but be because the schematic diagram of the indirect survey grid network that chip for driving exist to form;

As shown in Figure 4, be the interface schematic diagram of manual typing in the prior art;

As shown in Figure 5, be a flow chart of the present invention;

As shown in Figure 6, be an interface schematic diagram of the embodiment of the invention.

Embodiment

Below in conjunction with Figure of description the specific embodiment of the present invention is described.

PCB net table is the epitome of schematic diagram, and information all on the circuit board nearly all have description in the net table.A typical PCB net table comprises following content at least:

1, device list: the model of all components and parts, encapsulation and code name on the writing circuit plate

2, network list: the interconnected relationship on the writing circuit plate between all components and parts

Our a kind of typical net sheet format: Viewdraw Allergo net table (* .tel).Example is as follows:

$PACKAGES

′SOP48-20-250′！74LVTH16244；U8?U9?U10?U11

…

$FUNCTIONS

74LVTH16244！74ABT16244；F49?F129?F132?F134

…

$NETS

′$7N409′；R75：F60.2?U13：F49.1

′$7N410′；R76：F59.2?U13：F49.48

…

$END

$PACKAGES and $FUNCTIONS partial record the device list on the circuit board.

The $NETS partial record network list on the circuit.

We it can also be seen that from top net table example: the element of same kind has the naming rule of agreement: Rxxx to represent that resistance, Cxxx represent that electric capacity, RNxxx or RPxxx represent exclusion, Uxxx presentation function device etc. on the circuit board.

In view of this, if we increase the description to device package and model on the basis of VICTORY software processing method, device name and device package, model are combined,, be not difficult to find a practicality and general processing method again in conjunction with the present situation of different company's circuit design.Processing procedure of the present invention is such:

At first to form the tag file of transparent element;

In the present invention, the demand of this tag file is had two kinds, a kind of is the general feature file, title, model and the encapsulation of record transparent element, and this is a description feature commonly used in the field tests.In field tests, the element of same kind has the naming rule of agreement: Rxxx to represent that resistance, Cxxx represent that electric capacity, RNxxx or RPxxx represent exclusion, Uxxx presentation function device etc. on the circuit board.

General feature file of the present invention uses a kind of new file format, the feature of one or more transparent elements of file logging.

Tag file of company level of the present invention comprises the tag file of describing resistance, describes the tag file of exclusion and describes 244 tag files that drive.

Seeing two concrete tag files below, is note in { } wherein:

--xClass IC definition { the expression note is with "--" beginning }

BEGIN_NAME_DEFINE { expression keyword, NAME represents the title of element }

NAME=RN% { the equal sign back is user's input, and " % " represents asterisk wildcard }

DIRECTION＝NO

LEADS＝YCN16-4

[

(1，8)

(2，7)

(3，6)

(4，5)

]

LEADS＝YCN35-4

[

(1，8)

(2，7)

(3，6)

(4，5)

]

END_NAME_DEFINE

--?xClass?IC?definition

BEGIN_MODEL_DEFINE

MODEL＝％74ABT244％，％74HC244％，％74ACT16244％，

%74ACT244%, %74LVC244%, %74ABT162244%, %74ABT16244%, %74LVTH16244% { MODEL represents the model of element }

DIRECTION=YES { DIRECTION represents whether the component pin that defines has definite input/output relation }

LEADS=SOP20%{LEADS represents the encapsulation of element }

[

(2，18)

(4，16)

(6，14)

(8，12)

(11，9)

(13，7)

(15，5)

(17，3)

] pins corresponding relation of definition element a kind of encapsulation between [], describe and be with form to pin: (in-pin, out-pin), in-pin represents the pin number that can import, out-pin represents exportable pin number }

LEADS＝％SOP48％

[

(47，2)

(46，3)

(44，5)

(43，6)

(41，8)

(40，9)

(38，11)

(37，12)

(36，13)

(35，14)

(33，16)

(32，17)

(30，19)

(29，20)

(27，22)

(26，23)

]

END_MODEL_DEFINE

The tag file of the above generation is loaded into test macro;

The net table is loaded into test macro;

The net table is the text of indication circuit annexation, can both generate automatically in each single board design, and test macro can be analyzed automatically.

More than 3 steps, on the sequencing of time, do not have strict requirement, after can loading the net table earlier, generate and the loading tag file, can generate tag file earlier yet and reload the net table, load tag file at last, these all are the different expression forms of a technical scheme.

According to the characteristic information of transparent element, in the net table, search for then, find the network of being isolated by transparent element; The search of this transparent element is a comparatively simple step, and most of software is all supported this simple search, resembles the function of search that carries in the office softwares such as WORD, implements very convenient.

At last, will be merged, can finish processing method of the present invention by the network that transparent element is isolated.This merging also is one of function that present test macro had.

More than automatically perform software by one on these realitys of work and finish, promptly the more common testing system software of field tests at present as shown in Figure 6, is exactly concrete processing interface schematic diagram of the present invention.In this embodiment, comprised transparent elements such as resistance, exclusion and chip for driving, wherein chip for driving can be more colloquial 244,245 etc., and 74LVTH16244 is the unidirectional drive chip.

This shows that the present invention is simple, convenient, has very strong practicality, has solved more scabrous problem in the present test.Automatically generate because the net table is a cad tools, tag file is a system file, and the user only need click ' determining ' button after will netting table and tag file importing software module basically.Simultaneously, because the model of transparent element commonly used is basicly stable, period of change is longer, so general, the easy care of method of the present invention.And the user can freely increase new transparent devices, makes the present invention more flexible.

The checking of the present invention by in the laboratory can improve several times to the fault coverage of circuit board, and under the best situation, fault coverage has improved 10 times.

The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with the people of this technology in the disclosed technical scope of the present invention; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.

Claims

1, in a kind of boundary scan interconnecting test to the processing method of transparent components and parts, it is characterized in that this method may further comprise the steps:

The tag file of a, formation transparent element;

B, tag file is loaded into test macro;

C, the net table is loaded into test macro;

D, test macro are according to the characteristic information of transparent element, and the dragnet table finds transparent element;

E, the network that will be isolated by transparent element merge;

The tag file of described transparent element comprises: the general feature file of transparent element and tag file of company level;

2, the processing method to transparent element as claimed in claim 1 is characterized in that a general feature file can write down a kind of feature of transparent element, also can put down in writing the feature more than a kind of transparent element.

3, the processing method to transparent element as claimed in claim 1 is characterized in that a tag file of company level can comprise a kind of feature of transparent element, also can comprise more than a kind of feature.