CN1862267A - Method for checking circuit schematic diagram - Google Patents
Method for checking circuit schematic diagram Download PDFInfo
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- CN1862267A CN1862267A CN 200510103483 CN200510103483A CN1862267A CN 1862267 A CN1862267 A CN 1862267A CN 200510103483 CN200510103483 CN 200510103483 CN 200510103483 A CN200510103483 A CN 200510103483A CN 1862267 A CN1862267 A CN 1862267A
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Abstract
The present invention provides a method for checking circuit schematic diagram. Said method mainly includes the following steps: storing rules of various mode circuits into rule data base; using matching method of described mode circuit to match correspondent mode circuit in circuit schematic diagram to be checked and utilizing the rule of mode circuit stored into rule data base to check the circuit schematic diagram.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of method that circuit theory diagrams are examined.
Background technology
The drafting of circuit theory diagrams is important steps in the hardware design process in early stage, the industrial design of generally using EDA (automatic electronic) instrument to finish circuit theory diagrams at present.For guaranteeing the reliability of design, the design of circuit theory diagrams need be followed certain design specifications usually, owing to be subjected to the influence of circuit scale, circuit complexity and designer's ability and experience, unavoidably some mistakes can appear simultaneously in the design process of circuit theory diagrams.If these mistakes are extended to the design later stage even are extended to and realize and test phase, cause huge cost will for the whole performance history of hardware.Therefore, just should take certain measure in the design phase of circuit theory diagrams, such as, circuit theory diagrams to be examined automatically, the defective and the mistake that exist in being used for finding as soon as possible to design to guarantee designing quality, shorten the design cycle and save design cost.
The examination of circuit theory diagrams mainly comprises drawing normalized checking (can not overlap each other as drawing course device symbol), the inspection of device connection error (whether unsettled as device pin, as whether to have input and output conflict etc.), design logic bug check work such as (rule of thumb finishing).
A kind of checking method of circuit theory diagrams is in the prior art: adopt artificial check of drawings.Be that hardware designer is examined circuit theory diagrams according to the experience of oneself.This method mainly relies on the ability and the experience of hardware designer, can effectively utilize personal experience's accumulation of hardware designer.
The shortcoming of this method is: this method adopts artificial check of drawings, is a kind of review mode of non-automaticization, and in actual application, the result of use of this method will be subjected to the influence of ability, experience or even the duty of hardware designer.Therefore, the poor reliability of this method, efficient is low and cost is high, can't adapt to large-scale design effort.In addition, because the experience accumulation of hardware designer only limits to the individual, therefore, the popularization communication effect of this method is also relatively poor.
The checking method of another kind of circuit theory diagrams is in the prior art: use the embedded automatic check of drawings function of EDA (electric design automation) instrument to finish the examination of circuit theory diagrams.The normal at present eda tool that uses as Protel, ViewDraw, Concept etc., all has the schematic diagram audit function that is provided by eda tool provider.This method can be found the mistake in the schematic diagram quickly and easily in the drawing course of circuit theory diagrams.The principle schematic of this method as shown in Figure 1.
The shortcoming of this method is: owing to the audit function that eda tool is embedded is all more limited usually, therefore, this method can only be checked out some drawing gauge plasticity mistakes and some simple Devices physical connection mistakes.Can't check out the logical design mistake of some more complicated.Because the audit function of EDA is embedded in the instrument, can only support the examination of some fixed functions simultaneously, can't expand that also user's design experiences can't be preserved, accumulated and propagates, therefore, the promotion effect of this method is relatively poor according to user's demand.
The checking method of another kind of circuit theory diagrams is in the prior art: at some specific eda tools, design some schematic diagram censorwares the function of this specific eda tool is expanded.Censorware exists with the form of plug-in unit or stand alone software.Censorware obtains schematic diagram information by the schematic diagram data file that reads, analyzes the eda tool generation, or obtains schematic diagram information by the expansion interface that eda tool provides, and then according to the schematic diagram information of obtaining the correctness of schematic diagram is checked.This method can customize according to user's demand and experience, the examination rule of exploitation circuit theory diagrams, can implement some complicated logical design bug check to schematic diagram, has strengthened the examination ability of eda tool greatly.The principle schematic of this method as shown in Figure 2.
The shortcoming of this method is: the censorware in this method is to develop according to specific eda tool, this censorware must use the expansion interface of this specific eda tool, perhaps this censorware can only be discerned the document format data of this specific eda tool, therefore, this censorware can not be used for other eda tool; In the method, examination rule realizes by program code, and the user can only make further customization, interpolation or modification to this examination rule by coding code again, implements the comparison difficulty.Therefore, this method this be unfavorable for the accumulation and the propagation of the sharing of resource, experience.
The checking method of another kind of circuit theory diagrams is in the prior art: develop a general examination platform that is independent of eda tool.This method has adopted schematic diagram data file, regular actuator, examination rule technology disconnected from each other, the principle schematic of this method as shown in Figure 3, concrete processing procedure is as follows:
By the Data Format Transform instrument schematic diagram data file that different eda tools generates is converted to unified common data structure file.After TCL (command tools language) order encapsulation is used in the basic operation that a group of regular actuator is complete, the person that offers the Rulemaking, the Rulemaking person uses these TCL order structure examination rules, and will examine rule and be stored in the database.When beginning circuit theory diagrams are examined, audit crew is downloaded needed examination rule from database, and regular actuator is finished the censorship to schematic diagram according to the examination rule of downloading.In the method, the formulation of principle diagram design, examination rule and examination are carried out and are independently carried out respectively, and adopt database mode storage examination rule, therefore, this method has flexibly, be easy to expand, be beneficial to advantages such as the accumulation of sharing, be beneficial to experience of resource and propagation.
The shortcoming of this method is: in the method, the examination rule is described and typing by Tool Command Language, the execution of examination rule is controlled by regular command, therefore, the shortcoming of the maximum of this method is exactly not directly perceived, rule typing process is cumbersome, and when regular more complicated, that the rule description text will inevitably become is lengthy, easily make mistakes and readable bad.
Summary of the invention
In view of above-mentioned existing in prior technology problem, the purpose of this invention is to provide a kind of method that circuit theory diagrams are examined, thereby can realize circuit theory diagrams being examined automatically based on mode circuit.
The objective of the invention is to be achieved through the following technical solutions:
A kind of matching process of mode circuit comprises:
A, in the pending trial circuit theory diagrams feature device and the character network of search pattern circuit;
B, according to described feature device and the character network that finds, between pending trial circuit theory diagrams and mode circuit, mate.
Described steps A further comprises:
A1, in the pending trial circuit theory diagrams core devices of search pattern circuit, if find this core devices, execution in step A2 then; Otherwise the coupling flow process of mode circuit finishes;
A2, in the pending trial circuit theory diagrams, be the center, press feature device and the character network of breadth-first strategy by lining and outer search pattern circuit with the core devices.
Described steps A 2 specifically comprises:
A21, the core devices that finds in the described pending trial circuit theory diagrams is related with the core devices foundation in the mode circuit, also the device on these two all-networks that core devices connected and this all-network is mated, between the device that the match is successful, set up related;
Whether the feature device of A22, checking mode circuit all has corresponding related with all devices in the character network in the pending trial circuit theory diagrams with network, if, then in the pending trial circuit theory diagrams, search and obtain feature device and character network, otherwise, determine in the pending trial circuit theory diagrams, not find feature device and character network.
Described steps A 21 also comprises
Successively with the device on described two all-networks that core devices connected as new core devices, all-network that core devices connected that this is new and the device on this all-network mate, between the device that the match is successful, set up related, the all-network and the device that comprise on described two all-networks that core devices connected all mate, and have set up association.
Described steps A 21 specifically comprises:
In the matching process of described device,, then directly set up related with certain device in the described mode circuit this device if certain device in the mode circuit has only a device to match in the pending trial circuit theory diagrams; If there is one group of device to match, then from this group of device, selects a device and set up related with certain device in the described mode circuit.
Described steps A 21 specifically comprises:
According to the maximum search degree of depth of appointment, calculate the matching degree of corresponding device in each device in described one group of device and the mode circuit, therefrom select a device of matching degree maximum to set up related with the corresponding device in the mode circuit.
Described steps A 21 specifically comprises:
The matching degree of described device equals the matching degree sum of each pin of device divided by the number of pins of device.
Described steps A 21 specifically comprises:
If the current search depth registration is 0, the device count that the matching degree of pin equals to exist in the device that network that pin connects connects the device count of coupling to connect divided by the network that pin connected;
If the current search depth registration is greater than 1, then search depth is subtracted 1, the described device matching degree of recursive call algorithm, calculate the matching degree that has the device of coupling in the device that network that pin connected connects, the device count that the matching degree of pin equals to exist in the device that network that pin connects connects the matching degree sum of the device of coupling to connect divided by the network that pin connected.
Described step B specifically comprises:
B1, after confirming in the pending trial circuit theory diagrams, to find the feature device and character network of mode circuit, then confirm to exist in the pending trial circuit theory diagrams this mode circuit;
B2, corresponding device and network in all devices except that feature device and character network and network and the pending trial circuit theory diagrams in this mode circuit are mated one by one, between the device that the match is successful and network, set up related.
A kind of method that circuit theory diagrams are examined comprises:
C, the rule of various mode circuits is deposited in the rule database;
The matching process of D, the described mode circuit of use, the corresponding mode circuit of coupling in the pending trial circuit theory diagrams, and according to the described rule that deposits the mode circuit in the rule database in, the pending trial circuit theory diagrams are examined.
Described step C specifically comprises:
C1, set up the universal data format description document of mode circuit;
C2, the core of using the universal data format description document description scheme circuit rule of described mode circuit, other slave part of tool using command language description scheme circuit rule, and with in the general format data file and rule description script typing rule database that generate.
Described step C1 specifically comprises:
C11, in the electric design automation eda tool schematic diagram of drawing mode circuit;
C12, use crossover tool, the schematic diagram of the mode circuit that eda tool is generated is converted to a kind of and the irrelevant universal data format description document of eda tool.
Described step C2 specifically comprises:
The supplementary of tool using command language description scheme circuit rule, this supplementary comprises: the core devices information of the name information of mode circuit rule, mode circuit and feature device and character network information.
Described step C2 specifically comprises:
The tool using command language is given each device and the constrained attributes of network building-out in the mode circuit, the corresponding one section ool instruction language script of this constrained attributes.
Described step D specifically comprises:
D1, definite needs and pending trial circuit theory diagrams carry out the various mode circuits of matching treatment, download the mode circuit rule of these various mode circuits from described rule database;
The matching process of D2, the described mode circuit of use, in the pending trial circuit theory diagrams, mate described various mode circuit respectively, be recorded in the mistake in the pending trial circuit theory diagrams of finding in the matching process, and, the pending trial circuit theory diagrams examined according to the mode circuit rule of described download.
Described step D2 specifically comprises:
In the mode circuit rule of described download, the ool instruction language script of the constrained attributes correspondence of device that taking-up is complementary between pending trial circuit theory diagrams and mode circuit and network, carry out this ool instruction language script, finish attribute inspection this device and network according to execution result.
Described step D also comprises:
Draw the pending trial circuit theory diagrams in eda tool, the audit function of using eda tool to carry is carried out preliminary inquiry to the pending trial circuit theory diagrams, and is a kind of general format data file that is independent of eda tool with the file conversion of pending trial circuit theory diagrams.
As seen from the above technical solution provided by the invention, the present invention compares with prior art, has following advantage:
1, the mode circuit rule description is simple, directly uses the core of the general format data file description scheme circuit rule of mode circuit.
2, confirm and the step that is connected coupling by pattern location, pattern, between mode circuit and pending trial circuit theory diagrams, mate from coarse to finely, can reduce the expense in the mode circuit matching process effectively.
3,, can examine the pending trial circuit theory diagrams according to mode circuit effectively and quickly based on the describing method of mode circuit rule and the matching process of mode circuit.
Description of drawings
The principle schematic of Fig. 1 for using the embedded automatic check of drawings function of eda tool that circuit theory diagrams are examined;
The principle schematic of Fig. 2 for using censorware that circuit theory diagrams are examined;
The principle schematic of Fig. 3 for using general examination platform that circuit theory diagrams are examined;
Fig. 4 is the concrete processing flow chart of the matching process of mode circuit of the present invention;
Fig. 5 is the synoptic diagram of search depth and matching relationship;
Fig. 6 is the concrete processing flow chart of the describing method of mode circuit rule of the present invention;
Fig. 7 is the principle schematic of the method that circuit theory diagrams are examined of the present invention;
Fig. 8 is the concrete processing flow chart of the method that circuit theory diagrams are examined of the present invention.
Embodiment
The invention provides a kind of method that circuit theory diagrams are examined, core of the present invention is: the core of directly using the general format data file description scheme circuit rule of mode circuit, adopt the pattern that circuit theory-regular actuator-the examination rule is separated, circuit theory diagrams are examined automatically based on the mode circuit coupling.
In order to describe the present invention better, we simply introduce earlier mode circuit.
Mode circuit is a kind of common circuit segment that meets design specifications.In the design process of circuit diagram, often exist the circuit segment that some realize specific function, comprise in this circuit segment have between some devices be fixedly coupled, each device has the certain device of fixing attribute, the annexation of these certain device and attribute configuration come from practical experience and be verified is correct.This circuit segment is exactly a kind of mode circuit in the circuit diagram, or claims preferred circuit figure.
Describe the method for the invention in detail below in conjunction with accompanying drawing, the present invention has at first proposed a kind of matching process of mode circuit, and the concrete processing flow chart of this method comprises the steps: as shown in Figure 4
Step 4-1: determine pending trial circuit theory diagrams and corresponding mode circuit.
The coupling of mode circuit is exactly to seek the circuit segment of mating with mode circuit on the unexamined circuit theory diagrams, and sets up mode circuit and the corresponding device of unexamined circuit and getting in touch of annexation.
At first need to determine the unexamined circuit theory diagrams, need accordingly to determine the mode circuit of coupling then.This corresponding mode circuit is standard circuit segment with typical case's application under directly taking passages from the schematic diagram of design in the past or the circuit theory diagrams that repaint according to these standard circuit segments from some experience accumulation that designed in the past.
Step 4-2: the core devices of search pattern circuit in the pending trial circuit theory diagrams.
The core devices of mode circuit is a most representative device in the mode circuit, if occur this device in the pending trial circuit theory diagrams, then it exists the possibility of this mode circuit will be bigger.So, at the core devices of pending trial circuit theory diagrams search pattern circuit, if find, execution in step 4-3 then; Otherwise, execution in step 4-3.
Step 4-3: the core devices in pending trial circuit theory diagrams and the mode circuit is set up related, mated all-network that this device connects and the device on the network.
If in the pending trial circuit theory diagrams, find the core devices of mode circuit, in the pending trial circuit theory diagrams, be the center then with the core devices, press feature device and the character network of breadth-first strategy by lining and outer pattern search circuit.Feature device and character network are the signs of mode circuit, if in the pending trial circuit theory diagrams circuit segment of existence and character network and feature device matching, then think this strive for survival with the circuit of mode circuit coupling; If there is no, think that then this mode circuit does not exist in the pending trial circuit theory diagrams with the circuit segment of character network and feature device matching.The concrete search procedure of character network and feature device is as follows:
Core devices in the mode circuit is related with corresponding devices foundation in the pending trial circuit theory diagrams, promptly in pending trial circuit theory diagrams and mode circuit, add a relating attribute in the data structure of corresponding devices object and network object, the property value of this relating attribute is a pointer to object, with the corresponding object of the affiliated partner pointed mode circuit of pending trial circuit theory diagrams, simultaneously with the corresponding object of the affiliated partner pointed pending trial circuit theory diagrams of mode circuit.
Corresponding devices in the pending trial circuit theory diagrams is added single coupling device list.Single coupling device is meant certain device that certain network connects in the mode circuit, has only a device to match in the device that matching network connected in the pending trial circuit theory diagrams.If there are a plurality of devices to match, then be called many coupling devices.
From single coupling device list, take out first device, promptly take out corresponding devices in the described pending trial circuit theory diagrams, the coupling all-network that this device connected between mode circuit and pending trial circuit theory diagrams, and this all-network all set up association, simultaneously for wherein each network, all devices that matching network connected are also set up association, if single coupling device then adds device single device list of mating; Otherwise with in the circuit theory diagrams with mode circuit in the set of devices of device matching add many list of matches.
Step 4-4: in the pending trial circuit theory diagrams, do not have this mode circuit.
If in the pending trial circuit theory diagrams, do not find the core devices of mode circuit, think then in the pending trial circuit theory diagrams, not have this mode circuit that the coupling flow process of mode circuit finishes.
Step 4-5: all devices on the network are added single coupling device list or mate device list more, coupling single coupling device list or mate the all-network that device connected in the device list and the device on the network more.
From single coupling device list, take out all devices one by one successively, the all-network that related this device of coupling and foundation is connected between mode circuit and pending trial circuit theory diagrams, simultaneously, device on related this all-network of coupling and foundation, list coupling device is wherein added single coupling device list, with the many couplings of many couplings device adding device list wherein.
Taking out all devices one by one successively again from single coupling device list, carry out same coupling and set up related operation, is empty up to single coupling device list.
After single coupling device list is sky, specify a maximum search degree of depth, search depth is meant that at matching process be center freestone heart device device farthest is connected process with core devices intermediary device number with the core devices, this parameter is specified by the user when the examination beginning, be used for controlling the order of accuarcy of coupling, search depth is big more, and it is accurate more to mate, but the time that needs is long more, can weigh the relation of time and precision and select a suitable value.Such as, in the synoptic diagram of search depth shown in Figure 5 and matching relationship: c0 is a core devices, the coupling of the device in mode circuit and the pending trial circuit theory diagrams is associated as: C0 mates c0, C1 mates c1, and C2 mates c2, and C3 mates c3, C4 mates c4, and C5 mates c5.When search depth was appointed as 1, the coupling device that searches was: c1, c2, c3.When search depth was appointed as 2, the coupling device that searches was: c4, c5.
From many couplings device list, get first set of devices, according to the maximum search degree of depth of appointment, the matching degree of corresponding device in each device and the mode circuit in the calculating device group, the process of calculating device matching degree is as follows:
1, the matching degree of each pin of calculating device at first.
The pin matching degree is defined as the matching degree of the network that pin connects, and calculates according to the following procedure:
All devices that network connects in the match pattern circuit in the pending trial circuit theory diagrams.
If the current search depth registration is 0, then there is the device count of device count/network connection of coupling in the device that network matching degree=network connects;
If the current search depth registration greater than 1, then subtracts 1 with search depth, recursive call device matching degree algorithm, the matching degree of the device of existence coupling in the device that computational grid connects.The device count that has matching degree sum/network connection of the device of coupling in the device that network matching degree=network connects.
The network matching degree that aforementioned calculation is come out is the matching degree of pin.
2, calculating device matching degree.
Device matching degree=pin matching degree sum/number of pins.
After having calculated the device matching degree, therefrom select a device of matching degree maximum to set up related with the corresponding device in the mode circuit, and with in the single coupling of the device adding device list, from single coupling device list, take out this device again, carry out coupling recited above and set up related operation, then, from many couplings device list, get second set of devices, according to the maximum search degree of depth of appointment, carry out coupling recited above and set up related operation.Up to many couplings device list is empty, and the coupling process related with foundation finishes.
Step 4-6: judge whether have feature device and character network in the pending trial circuit theory diagrams.
Feature device and character network in the checking mode circuit, if the feature device all has corresponding related with all devices in the character network in the pending trial circuit theory diagrams with network, then show and have feature device and character network, execution in step 4-7 in the pending trial circuit theory diagrams; Otherwise, execution in step 4-4.
Step 4-7: corresponding device in device except that feature device and character network and network and the mode circuit in the pending trial circuit theory diagrams and network are mated one by one, set up related.
After in confirming the pending trial circuit theory diagrams, having feature device and character network, then confirm to exist in the pending trial circuit theory diagrams this mode circuit.So, corresponding device in device except that feature device and character network and network and the mode circuit in the pending trial circuit theory diagrams and network are mated one by one, set up related.
The detailed process of coupling is identical with the described matching process of step 4-5 with step 4-3.If corresponding device in device in the pending trial circuit theory diagrams except that feature device and character network and network and the mode circuit and network can not mate fully, then illustrate in the pending trial circuit theory diagrams to have design mistake.
The invention allows for a kind of describing method of mode circuit rule, the concrete treatment scheme of this method comprises the steps: as shown in Figure 6
Step 6-1, in eda tool the drawing mode circuit.
This method at first need be in eda tool the schematic diagram of drawing mode circuit.
Step 6-2, mode circuit is converted to a kind of universal data format description document.
Use certain crossover tool, the schematic diagram of the mode circuit that eda tool is generated is converted to a kind of and the irrelevant universal data format description document of eda tool.
Step 6-3, the core of using the universal data format description document description scheme circuit rule of mode circuit.
The universal data format description document of using above-mentioned conversion to generate, the core of description scheme circuit rule.
The supplementary of step 6-4, tool using command language description scheme circuit rule.
Behind the core of having described the mode circuit rule, the supplementary of tool using command language description scheme circuit rule.Comprising: the information such as core devices, feature device and character network of the title of mode circuit rule, mode circuit corresponding common format data file, mode circuit.
The attribute inspection of device and network in step 6-5, the tool using command language description scheme circuit.
For each device and the network in the mode circuit, the tool using command language is added a constrained attributes.The corresponding one section ool instruction language script of this constrained attributes, this ool instruction language script are used to describe the various attribute constraints to this device.
Based on the matching process of mode circuit recited above and the describing method of mode circuit rule, the present invention has proposed a kind of checking method of circuit theory diagrams at last, this method adopts the pattern that circuit theory one regular actuator-the examination rule is separated, its principle schematic as shown in Figure 7, the concrete treatment scheme of this method comprises the steps: as shown in Figure 8
Step 8-1, with mode circuit rule input database.
According to the describing method of mode circuit rule recited above, generate the general format data file and the rule description script of various mode circuits, in this general format data file and rule description script typing rule database.
Step 8-2, use eda tool carry out preliminary inquiry to the pending trial circuit theory diagrams.
Draw the pending trial circuit theory diagrams in eda tool, after completing, the examination instrument that uses eda tool to carry carries out preliminary inquiry to the pending trial circuit theory diagrams, the mistake of finding in the record examination, and save as file.Then, using the data-switching instrument is a kind of general format data file that is independent of eda tool with the file conversion of pending trial circuit theory diagrams.
Step 8-3, from database, download needed mode circuit rule.
According to the pending trial circuit theory diagrams of drawing, determine need carry out accordingly the mode circuit of matching treatment, then, from rule database, download the pairing mode circuit rule of this mode circuit.
Matching process match pattern circuit in the pending trial circuit theory diagrams of step 8-4, use mode circuit.
Carry out the mode circuit of matching treatment according to the needs of determining, use the matching process of mode circuit recited above, this mode circuit of coupling in the pending trial circuit theory diagrams of drawing.
If in matching process, in the pending trial circuit theory diagrams, do not find core devices, feature device and the character network of this mode circuit, then the examination at this mode circuit finishes.Execution in step 8-6.
If in matching process, in the pending trial circuit theory diagrams, found core devices, feature device and the character network of mode circuit, then determining has this mode circuit at the pending trial circuit theory diagrams.Use the matching process of mode circuit recited above, between pending trial circuit theory diagrams and mode circuit, mate, and set up association, execution in step 8-5.
The mistake of finding in step 8-5, the report matching process for each device and the network that have mated, is carried out the script of its constrained attributes correspondence.
Be recorded in the mistake in the pending trial circuit theory diagrams of finding in the matching process.For each device and network in the pending trial circuit theory diagrams that mated with mode circuit, take out describing method according to mode circuit rule recited above, the tool using command language is the constrained attributes of this each device and network building-out.Carry out the ool instruction language script of this constrained attributes correspondence, finish attribute inspection, and provide audit report this device and network.Examination at this mode circuit finishes.
Step 8-6, according to next mode circuit, to the pending trial circuit theory diagrams proceed the examination.
Carry out the mode circuit of matching treatment and the mode circuit rule of this mode circuit correspondence of taking out according to the next needs of determining, continue the pending trial circuit theory diagrams are examined.All mode circuit segments in the pending trial circuit are all examined.
Then, provide the examination report of final pending trial circuit theory diagrams.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (17)
1, a kind of matching process of mode circuit is characterized in that, comprising:
A, in the pending trial circuit theory diagrams feature device and the character network of search pattern circuit;
B, according to described feature device and the character network that finds, between pending trial circuit theory diagrams and mode circuit, mate.
According to the matching process of the described mode circuit of claim 1, it is characterized in that 2, described steps A further comprises:
A1, in the pending trial circuit theory diagrams core devices of search pattern circuit, if find this core devices, execution in step A2 then; Otherwise the coupling flow process of mode circuit finishes;
A2, in the pending trial circuit theory diagrams, be the center, press feature device and the character network of breadth-first strategy by lining and outer search pattern circuit with the core devices.
According to the matching process of the described mode circuit of claim 2, it is characterized in that 3, described steps A 2 specifically comprises:
A21, the core devices that finds in the described pending trial circuit theory diagrams is related with the core devices foundation in the mode circuit, also the device on these two all-networks that core devices connected and this all-network is mated, between the device that the match is successful, set up related;
Whether the feature device of A22, checking mode circuit all has corresponding related with all devices in the character network in the pending trial circuit theory diagrams with network, if, then in the pending trial circuit theory diagrams, search and obtain feature device and character network, otherwise, determine in the pending trial circuit theory diagrams, not find feature device and character network.
According to the matching process of the described mode circuit of claim 3, it is characterized in that 4, described steps A 21 also comprises:
Successively with the device on described two all-networks that core devices connected as new core devices, all-network that core devices connected that this is new and the device on this all-network mate, between the device that the match is successful, set up related, the all-network and the device that comprise on described two all-networks that core devices connected all mate, and have set up association.
According to the matching process of the described mode circuit of claim 4, it is characterized in that 5, described steps A 21 specifically comprises:
In the matching process of described device,, then directly set up related with certain device in the described mode circuit this device if certain device in the mode circuit has only a device to match in the pending trial circuit theory diagrams; If there is one group of device to match, then from this group of device, selects a device and set up related with certain device in the described mode circuit.
According to the matching process of the described mode circuit of claim 5, it is characterized in that 6, described steps A 21 specifically comprises:
According to the maximum search degree of depth of appointment, calculate the matching degree of corresponding device in each device in described one group of device and the mode circuit, therefrom select a device of matching degree maximum to set up related with the corresponding device in the mode circuit.
According to the matching process of the described mode circuit of claim 6, it is characterized in that 7, described steps A 21 specifically comprises:
The matching degree of described device equals the matching degree sum of each pin of device divided by the number of pins of device.
According to the matching process of the described mode circuit of claim 7, it is characterized in that 8, described steps A 21 specifically comprises:
If the current search depth registration is 0, the device count that the matching degree of pin equals to exist in the device that network that pin connects connects the device count of coupling to connect divided by the network that pin connected;
If the current search depth registration is greater than 1, then search depth is subtracted 1, the described device matching degree of recursive call algorithm, calculate the matching degree that has the device of coupling in the device that network that pin connected connects, the device count that the matching degree of pin equals to exist in the device that network that pin connects connects the matching degree sum of the device of coupling to connect divided by the network that pin connected.
According to the matching process of claim 1,2,3,4,5,6,7 or 8 described mode circuits, it is characterized in that 9, described step B specifically comprises:
B1, after confirming in the pending trial circuit theory diagrams, to find the feature device and character network of mode circuit, then confirm to exist in the pending trial circuit theory diagrams this mode circuit;
B2, corresponding device and network in all devices except that feature device and character network and network and the pending trial circuit theory diagrams in this mode circuit are mated one by one, between the device that the match is successful and network, set up related.
10, a kind of method that circuit theory diagrams are examined is characterized in that, comprising:
C, the rule of various mode circuits is deposited in the rule database;
The matching process of D, the described mode circuit of use, the corresponding mode circuit of coupling in the pending trial circuit theory diagrams, and according to the described rule that deposits the mode circuit in the rule database in, the pending trial circuit theory diagrams are examined.
11, according to the described method that circuit theory diagrams are examined of claim 10, it is characterized in that described step C specifically comprises:
C1, set up the universal data format description document of mode circuit;
C2, the core of using the universal data format description document description scheme circuit rule of described mode circuit, other slave part of tool using command language description scheme circuit rule, and with in the general format data file and rule description script typing rule database that generate.
12, according to the described method that circuit theory diagrams are examined of claim 11, it is characterized in that described step C1 specifically comprises:
C11, in the electric design automation eda tool schematic diagram of drawing mode circuit;
C12, use crossover tool, the schematic diagram of the mode circuit that eda tool is generated is converted to a kind of and the irrelevant universal data format description document of eda tool.
13, according to the described method that circuit theory diagrams are examined of claim 12, it is characterized in that described step C2 specifically comprises:
The supplementary of tool using command language description scheme circuit rule, this supplementary comprises: the core devices information of the name information of mode circuit rule, mode circuit and feature device and character network information.
14, according to the described method that circuit theory diagrams are examined of claim 13, it is characterized in that described step C2 specifically comprises:
The tool using command language is given each device and the constrained attributes of network building-out in the mode circuit, the corresponding one section ool instruction language script of this constrained attributes.
15, according to claim 10,11,12, the 13 or 14 described methods that circuit theory diagrams are examined, it is characterized in that described step D specifically comprises:
D1, definite needs and pending trial circuit theory diagrams carry out the various mode circuits of matching treatment, download the mode circuit rule of these various mode circuits from described rule database;
The matching process of D2, the described mode circuit of use, in the pending trial circuit theory diagrams, mate described various mode circuit respectively, be recorded in the mistake in the pending trial circuit theory diagrams of finding in the matching process, and, the pending trial circuit theory diagrams examined according to the mode circuit rule of described download.
16, according to the described method that circuit theory diagrams are examined of claim 15, it is characterized in that described step D2 specifically comprises:
In the mode circuit rule of described download, the ool instruction language script of the constrained attributes correspondence of device that taking-up is complementary between pending trial circuit theory diagrams and mode circuit and network, carry out this ool instruction language script, finish attribute inspection this device and network according to execution result.
17, according to the described method that circuit theory diagrams are examined of claim 15, it is characterized in that described step D also comprises:
Draw the pending trial circuit theory diagrams in eda tool, the audit function of using eda tool to carry is carried out preliminary inquiry to the pending trial circuit theory diagrams, and is a kind of general format data file that is independent of eda tool with the file conversion of pending trial circuit theory diagrams.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101034839A CN100403039C (en) | 2005-09-19 | 2005-09-19 | Method for checking circuit schematic diagram |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101034839A CN100403039C (en) | 2005-09-19 | 2005-09-19 | Method for checking circuit schematic diagram |
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| CN1862267A true CN1862267A (en) | 2006-11-15 |
| CN100403039C CN100403039C (en) | 2008-07-16 |
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| CNB2005101034839A Expired - Fee Related CN100403039C (en) | 2005-09-19 | 2005-09-19 | Method for checking circuit schematic diagram |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103368793A (en) * | 2013-07-18 | 2013-10-23 | 北京随方信息技术有限公司 | Method for achieving network inspection by identifying network overall attribute |
| CN103425807A (en) * | 2012-05-18 | 2013-12-04 | 瑞昱半导体股份有限公司 | Device and method for checking whether wiring errors exist in input and output elements in chip design |
| CN103838894A (en) * | 2012-11-26 | 2014-06-04 | 北京华大九天软件有限公司 | Method for achieving automatic PDK testing |
| CN109471637A (en) * | 2018-11-08 | 2019-03-15 | 西安电子科技大学 | The examination script debugging method of circuit diagram |
| CN112307694A (en) * | 2020-10-16 | 2021-02-02 | 烽火通信科技股份有限公司 | Method and device for comparing difference of circuit schematic diagram |
| CN113642284A (en) * | 2020-04-27 | 2021-11-12 | 上海复旦微电子集团股份有限公司 | Circuit schematic diagram checking method and device and computer readable storage medium |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5249133A (en) * | 1991-04-10 | 1993-09-28 | Sun Microsystems, Inc. | Method for the hierarchical comparison of schematics and layouts of electronic components |
| CN1298047A (en) * | 1999-12-02 | 2001-06-06 | 北京市市政工程研究院 | Double-amplitude building tamper |
| CN1521829A (en) * | 2003-01-29 | 2004-08-18 | 上海芯华微电子有限公司 | Topology verification method for integrated circuit |
| CN1521830A (en) * | 2003-02-12 | 2004-08-18 | 上海芯华微电子有限公司 | Technical method for integrated circuit design, test and measurement integration |
| CN1523660A (en) * | 2003-02-17 | 2004-08-25 | 上海芯华微电子有限公司 | Bidirectional technique system of integrated circuit design |
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2005
- 2005-09-19 CN CNB2005101034839A patent/CN100403039C/en not_active Expired - Fee Related
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| CN103425807A (en) * | 2012-05-18 | 2013-12-04 | 瑞昱半导体股份有限公司 | Device and method for checking whether wiring errors exist in input and output elements in chip design |
| CN103838894A (en) * | 2012-11-26 | 2014-06-04 | 北京华大九天软件有限公司 | Method for achieving automatic PDK testing |
| CN103838894B (en) * | 2012-11-26 | 2017-05-24 | 北京华大九天软件有限公司 | Method for achieving automatic PDK testing |
| CN103368793A (en) * | 2013-07-18 | 2013-10-23 | 北京随方信息技术有限公司 | Method for achieving network inspection by identifying network overall attribute |
| CN103368793B (en) * | 2013-07-18 | 2018-04-17 | 北京随方信息技术有限公司 | A kind of method for realizing Network Check by identifying network integrity attribute |
| CN109471637A (en) * | 2018-11-08 | 2019-03-15 | 西安电子科技大学 | The examination script debugging method of circuit diagram |
| CN109471637B (en) * | 2018-11-08 | 2021-07-06 | 西安电子科技大学 | Circuit diagram examination script debugging method |
| CN113642284A (en) * | 2020-04-27 | 2021-11-12 | 上海复旦微电子集团股份有限公司 | Circuit schematic diagram checking method and device and computer readable storage medium |
| CN113642284B (en) * | 2020-04-27 | 2024-03-26 | 上海复旦微电子集团股份有限公司 | Method and device for examining circuit schematic diagram, and computer readable storage medium |
| CN112307694A (en) * | 2020-10-16 | 2021-02-02 | 烽火通信科技股份有限公司 | Method and device for comparing difference of circuit schematic diagram |
| CN112307694B (en) * | 2020-10-16 | 2022-04-26 | 烽火通信科技股份有限公司 | Method and device for comparing difference of circuit schematic diagram |
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| CN100403039C (en) | 2008-07-16 |
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