CN1266757C - CMOS circuit and body silicon micromechanical system integraled method - Google Patents

CMOS circuit and body silicon micromechanical system integraled method Download PDF

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Publication number
CN1266757C
CN1266757C CN 03100303 CN03100303A CN1266757C CN 1266757 C CN1266757 C CN 1266757C CN 03100303 CN03100303 CN 03100303 CN 03100303 A CN03100303 A CN 03100303A CN 1266757 C CN1266757 C CN 1266757C
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China
Prior art keywords
silicon
mems
cmos
cmos circuit
single chip
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CN 03100303
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CN1516257A (en
Inventor
闫桂珍
郝一龙
朱泳
王成伟
张大成
王阳元
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Peking University
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Peking University
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Abstract

The present invention discloses a method for integrating a single chip CMOS and a body silicon micromechanical system, which comprises the following steps: 1), forming an isolation groove and using deep pool etching and SiO2 and polysilicon filling to realize the insulation of an MEMS structure and a CMOS circuit; 2), processing a standard CMOS circuit after the isolation groove is completed; 3), using SiO2 and Si3 N4 as masks, corroding silicon from back until SiO2 at the bottom of the isolation groove is exposed, and completing the thickness control of an MEMS silicon structure layer; 4), completing to metalize the CMOS circuit and mask the MEMS structure. An MEMS structure zone uses aluminum as a mask, a CMOS circuit zone uses thick etching rubber as a mask, and DRIE is used for releasing a silicon structure. The method of the present invention not only obtains large quality blocks, but also makes a structural capacitor by high depth-width ratio; meanwhile, a body silicon micro machine and the CMOS circuit are integrated. The present invention obviously raises the accuracy and the stability of an MEMS sensor, and has front edge performance and important practicability.

Description

The method of a kind of cmos circuit and the bulk silicon micro mechanic system integration
Technical field
The present invention relates to the microelectromechanical systems manufacture field.
Background technology
Microelectromechanical systems (MEMS) is a new and high technology of high speed development in recent years, adopt advanced semiconductor process techniques, whole mechanical structure is finished in chip piece, on volume, weight, price and power consumption, obvious advantages is arranged, obtained extensive use in Aero-Space, military affairs, biomedicine, automobile and other industries.But performance, the particularly precision index of micro mechanical sensor (for example gyroscope) are also less than traditional mechanical pick-up device at present, the occasion of low required precision in only being applicable to; Integrated circuit and MEMS structure are integrated on the chip piece, can significantly improve the precision and the reliability of transducer, existing a lot of application the in surface micro, but mass is smaller in the mechanical structure, the electric capacity output signal is very faint, has limited the performance and the scope of application of surperficial MEMS transducer.
Body silicon MEMS processing technology can be produced bigger mass and very high structure depth-to-width ratio, has increased the sensitivity of microsensor.The movable silicon structure of integrated circuit (IC) and body silicon MEMS is integrated on the chip piece, it is the bottleneck of micro mechanical technology research and development, if can address this problem, can not only obtain bigger mass and very high constructional depth ratio, can also significantly improve the precision and the stability of transducer, will bring more wide application prospect to MEMS.
Summary of the invention
The purpose of this invention is to provide a kind ofly, be about to cmos circuit and be integrated on the chip piece, with the precision and the stability of raising MEMS transducer and actuator with MEMS with cmos circuit and the integrated method of body silicon MEMS.
For achieving the above object, utilize silicon trench reactive ion etching (DRIE) technology and low-pressure chemical vapor phase deposition (LPCVD) medium filling technique to realize the insulation of body silicon structure part and circuit part, finish the processing of CMOS integrated circuit and body silicon MEMS on this basis.Concrete scheme is as follows:
1) forms isolation channel: adopt the silicon trench lithographic technique, fill, realize the insulation of MEMS structure and cmos circuit with silicon dioxide and polysilicon;
2) finish the processing of the laggard column criterion cmos circuit of isolation channel;
3) use SiO 2And Si 3N 4Make mask, from back side corrosion silicon, until the SiO that exposes the isolation channel bottom 2, finish the THICKNESS CONTROL of MEMS silicon structure layer;
4) finish cmos circuit metallization and MEMS structure mask: the MEMS structural area is made mask with aluminium, and the cmos circuit district makes mask with thick photoresist, discharges silicon structure with DRIE.
Described isolation channel is determined the silicon groove depth according to MEMS device architecture needs.
Described isolation channel adopts lithographic definition to go out the isolation channel figure, etches the silicon groove with DRIE.
Described SiO 2Fill and adopt the high-temperature oxydation growth method.
Described polysilicon adopts LPCVD deposit polysilicon to fill the silicon groove.
Described isolation channel front resist coating, photoresist and polysilicon with RIE (reactive ion etching) etching surface make flattening surface.
The processing of described standard CMOS circuitry comprises: the formation of P trap; P ditch metal-oxide-semiconductor grid are opened and are adjusted; N ditch metal-oxide-semiconductor grid are opened and are adjusted; Form polysilicon gate; P ditch metal-oxide-semiconductor source-drain area forms; N ditch metal-oxide-semiconductor source-drain area formation etc.
The characteristics of the inventive method are: utilize deep etching and deep trouth LPCVD filling technique to produce the electric insulation deep groove structure of high-aspect-ratio, realized the electric insulation of body silicon structure part with circuit part, the CMOS technology of combined standard, the technology of having finished integrated circuit and body silicon MEMS is integrated.Not only obtained bigger mass with the inventive method, and the structure capacitive of producing with the higher depth-to-width ratio of the present invention, realized the integrated of bulk silicon micro mechanic and cmos circuit simultaneously, significantly improved the precision and the stability of MEMS transducer, had frontier nature and important practical and be worth.
Below in conjunction with specific embodiment, the present invention is described in further detail.
Description of drawings
Fig. 1 is the integrated structural profile schematic diagram of CMOS and body silicon MEMS.
Fig. 2 is the plane graph of Fig. 1.
Fig. 3 is CMOS and body silicon MEMS structure integrated technique schematic flow sheet.
Embodiment
Embodiment: P trap CMOS and little gyro are integrated
Original material: twin polishing N type silicon chip, resistivity 5-8 Ω-cm,＜100〉crystal orientation, silicon wafer thickness is 400 microns.
1. the formation of isolation channel:
1) define the isolation channel figure with photoetching, groove width 3-4 micron etches the silicon groove with DRIE, and groove depth 40-100 μ m (determining the silicon groove depth according to MEMS device architecture needs) is shown in Fig. 3 (a);
2) the high-temperature thermal oxidation thick SiO of 5000 that grows 2(playing insulating effect) fills the silicon groove with the thick polysilicon of LPCVD deposit 2-2.5 μ m again, requires to fill up the silicon groove, and the cavity can not be arranged;
3) front resist coating, photoresist and polysilicon with RIE (reactive ion etching) etching surface make flattening surface.Suitably control oxygen and SF 6Ratio, silicon is 1.1: 1 with the selection ratio of photoresist in the control RIE etching process, shown in Fig. 3 (b).
2. form the P well region:
1) lithographic definition P well region, corrosion SiO 2
2) the boron ion injects, conventional energy and dosage, and the P trap advances, and junction depth is greater than 8 microns;
3) corrosion SiO 2, about 5000 .
3.P the raceway groove place is injected and the place selective oxidation:
1) high-temperature oxydation, the thick SiO of 800 grows 2, LPCVD deposit Si 3N 4(silicon nitride) 1600 ;
2) lithographic definition active area and MEMS structural area, RIE etching Si 3N 4, BOE (buffered hydrofluoric acid corrosive liquid) corrodes SiO 2
3) lithographic definition P raceway groove place, phosphorus, conventional energy and dosage are injected in the place;
4) SiO of hydrogen-oxygen synthetically grown 8000 2, use phosphoric acid corrosion Si 3N 4, shown in Fig. 3 (c).
4.P opening, ditch metal-oxide-semiconductor grid adjust:
1) lithographic definition P ditch active area;
2) ion injects, and conventional energy and dosage remove photoresist.
5.N opening, ditch metal-oxide-semiconductor grid adjust:
1) lithographic definition N ditch active area;
2) ion injects, and conventional energy and dosage remove photoresist.
6. formation polysilicon gate:
1) gate oxidation, 500 ;
2) LPCVD deposit polysilicon, thickness 3500 , polysilicon doping is carried out in phosphorous diffusion;
3) lithographic definition polysilicon grid region, the RIE etch polysilicon;
7.P ditch metal-oxide-semiconductor source-drain area forms:
1) lithographic definition P ditch source-drain area;
2) the boron ion injects, conventional energy and dosage.
8.N ditch metal-oxide-semiconductor source-drain area forms, shown in Fig. 3 (d):
1) lithographic definition N ditch source-drain area;
2) phosphonium ion injects, conventional energy and dosage.
9. ion-activated annealing and formation SiO 2Sidewall is isolated:
1) LPCVD deposit SiO 2, thickness 4000 ,
2) SiO 2Fine and close and ion-activated annealing, 950 ℃, 30 minutes,
3) RIE anisotropic etching SiO 2, form sidewall.
10. formation silicide:
1) LPCVD SiO 2, thickness 800 ;
2) lithographic definition silicide area, corrosion SiO 2
3) sputter Co or Ti, about 300 ;
4) under 700-800 ℃ of temperature, carry out RTP (quick high-temp annealing) and handle, use HCl+H 2O 2The Co of selective etching non-silicide region or Ti.
11. the corrosion unnecessary SiO in the back side 2And polysilicon:
1) front gluing protection;
2) RIE etching back side polysilicon 3500 , SiO 2500 , polysilicon 2-2.5 micron;
3) BOE corrosion SiO 25000 ;
12. form the insulation between polysilicon and metal bi lead-in wire:
LPCVD SiO 2, thickness 7000 carry out 900 ℃ of 30 minutes densification annealing then.
13. use SiO 2And Si 3N 4Protection, corrosion back side silicon forms the MEMS structure sheaf, shown in Fig. 3 (e):
1) front gluing protection, corrosion back side SiO 2, remain 1000 ;
2) LPCVD deposit Si 3N 4, thickness 1600 ;
3) back side lithographic definition goes out MEMS structural area and insulation layer, RIE etching Si 3N 4, BOE corrodes SiO 2
4) with TMAH (tetramethyl oxyammonia) corrosion silicon 320-360 micron, structure sheaf keeps the 40-80 micron on demand, exposes the bottom of isolation channel;
5) the positive Si of RIE etching 3N 4
14. open fairlead, shown in Fig. 3 (f):
1) lithographic definition cmos circuit lead-in wire porose area and MEMS structural area;
2) BOE corrosion SiO 2, about 7500 of thickness.
15. finish cmos circuit metallization and MEMS structure mask, shown in Fig. 3 (g):
1) sputter 500 titaniums and 8000 aluminium;
2) lithographic definition goes out metallization pattern and MEMS structural area figure;
3) RIE etching or wet etching 8000 aluminium and 500 titaniums.
16. alloy
Under 430 ℃, carry out 30 minutes alloy treatment.
17. pre-section and the protection of cmos circuit district:
1) front gluing, back side section, the degree of depth is the 200-250 micron, removes photoresist;
2) define the MEMS structural area with thick resist lithography, glue is thick in 2.5 microns;
18. make mask with thick photoresist and aluminium, the DRIE etching discharges the MEMS silicon structure, shown in Fig. 3 (h).
19. sliver, packaging and testing.
Device after CMOS that obtains and body silicon MEMS are integrated as shown in Figure 1 and Figure 2, among Fig. 1,1 is the PMOS pipe; 2 are the NMOS pipe, and 3 is insulation layer, and 4 is the MEMS structural area, and 5 is temperature sensor.Wherein 6,7,8,9,10,11 and 12 represent P-Si, SiO respectively 2, N +-Si, P-Si, P +-Si, Poly-Si and Al; Fig. 2 is integrated circuit and little gyro structural plan schematic diagram, and wherein A partly is the integrated circuit district, and B partly is temperature sensor and integrated circuit district, and C partly is the MEMS structural area.

Claims (7)

1, a kind of with single chip CMOS and the integrated method of bulk silicon micro mechanic, it is characterized by:
1) forms isolation channel: adopt deep etching, SiO 2Fill with polysilicon, realize the insulation of MEMS structure and cmos circuit;
2) finish the processing of the laggard column criterion cmos circuit of isolation channel;
3) use SiO 2And Si 3N 4Make mask, from back side corrosion silicon, until the SiO that exposes the isolation channel bottom 2, finish the THICKNESS CONTROL of MEMS silicon structure layer;
4) finish cmos circuit metallization and MEMS structure mask: the MEMS structural area is made mask with aluminium, and the cmos circuit district makes mask with thick photoresist, discharges silicon structure with the silicon trench reactive ion etching method.
2, according to claim 1 a kind of with single chip CMOS and the integrated method of bulk silicon micro mechanic, it is characterized in that: described isolation channel is determined the silicon groove depth according to MEMS device architecture needs.
3, according to claim 1 a kind of with single chip CMOS and the integrated method of bulk silicon micro mechanic, it is characterized in that: described isolation channel adopts lithographic definition to go out the isolation channel figure, etches the silicon groove with the silicon trench reactive ion etching method.
4, according to claim 1 a kind of with single chip CMOS and the integrated method of bulk silicon micro mechanic, it is characterized in that: described SiO 2Fill and adopt the high-temperature oxydation growth method.
5, according to claim 1 a kind of with single chip CMOS and the integrated method of bulk silicon micro mechanic, it is characterized in that: described polysilicon is filled and is adopted LPCVD deposit polysilicon to fill the silicon groove.
6, according to claim 1 a kind of with single chip CMOS and the integrated method of bulk silicon micro mechanic, it is characterized in that: described isolation channel front resist coating, photoresist and polysilicon with the RIE etching surface make flattening surface.
7, according to claim 1 a kind of with single chip CMOS and the integrated method of bulk silicon micro mechanic, it is characterized in that: the processing of described standard CMOS circuitry comprises: P ditch metal-oxide-semiconductor grid are opened and are adjusted; N ditch metal-oxide-semiconductor grid are opened and are adjusted; Form polysilicon gate; P ditch metal-oxide-semiconductor source-drain area forms; N ditch metal-oxide-semiconductor source-drain area forms.
CN 03100303 2003-01-10 2003-01-10 CMOS circuit and body silicon micromechanical system integraled method Expired - Fee Related CN1266757C (en)

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