CN103065942B - Control method and the semiconductor structure of the semiconductor film thickness that deep groove etching is formed - Google Patents

Control method and the semiconductor structure of the semiconductor film thickness that deep groove etching is formed Download PDF

Info

Publication number
CN103065942B
CN103065942B CN201310006414.0A CN201310006414A CN103065942B CN 103065942 B CN103065942 B CN 103065942B CN 201310006414 A CN201310006414 A CN 201310006414A CN 103065942 B CN103065942 B CN 103065942B
Authority
CN
China
Prior art keywords
semiconductor film
thickness
clear layer
protective clear
depth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310006414.0A
Other languages
Chinese (zh)
Other versions
CN103065942A (en
Inventor
苏佳乐
周国平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Corp
Original Assignee
Wuxi CSMC Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi CSMC Semiconductor Co Ltd filed Critical Wuxi CSMC Semiconductor Co Ltd
Priority to CN201310006414.0A priority Critical patent/CN103065942B/en
Publication of CN103065942A publication Critical patent/CN103065942A/en
Application granted granted Critical
Publication of CN103065942B publication Critical patent/CN103065942B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The invention discloses a kind of method controlling the semiconductor film thickness that deep groove etching is formed and semiconductor structure, by arranging measuring flume semiconductor crystal wafer first, and in measuring flume, form protective clear layer, make during subsequent corrosion forms semiconductor film, wafer material bottom measuring flume is corroded and exposes protective clear layer, the difference in height of itself and semiconductor film surface is obtained according to the reference plane limited bottom protective clear layer, the degree of depth according to measuring flume and described difference in height can be accurately obtained the current thickness of semiconductor film, thus control corrosion rate parameter is corroded and is obtained the accurate semiconductor film of thickness further.Instant invention overcomes the problem being difficult to monitor and measure due to the semiconductor film thickness caused of semiconductor crystal wafer thickness error.

Description

Control method and the semiconductor structure of the semiconductor film thickness that deep groove etching is formed
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of semiconductor film controlling deep groove etching formation The method of thickness and semiconductor structure.
Background technology
In semiconductor chip manufacture process, such as in the manufacture process of semiconductor pressure sensor, need logical Cross and make one layer of semiconductor film the thinnest in one chamber of corrosion, the corresponding region of semiconductor wafer back chip, The thickness of this semiconductor film is usually 10 microns.Semiconductor film may be used for induction pressure or other outside Boundary's parameter, thus, can the sensitivity of sensor depend greatly on and be accurately controlled semiconductor film Thickness.In prior art, the generally degree of depth by measuring the chamber of semiconductor crystal wafer thickness and corrosion calculates The thickness of semiconductor film.
But, due to wafer production technology, the thickness difference between different semiconductor crystal wafers is ± 5 More than Wei meter.And, also can deposit on silicon chip in the production process of wafer production gross thickness 1 micron with On material layer, this can bring error for silicon wafer thickness further.The error of silicon wafer thickness can make partly leading In the production process of body membrane structure, the control of etching process is extremely difficult, thus causes being difficult to accurately control deeply The semiconductor film thickness that groove corrosion is formed.
Summary of the invention
Technical problem solved by the invention is to provide a kind of semiconductor film thickness controlling deep groove etching formation Method and semiconductor structure.
The invention discloses a kind of method controlling the semiconductor film thickness that deep groove etching is formed, including:
First surface at semiconductor crystal wafer makes at least one measuring flume with first degree of depth;Wherein, institute State first degree of depth expectation thickness more than described semiconductor film;
Protective clear layer is formed in described measuring flume;
Region and described measuring flume that on the second surface of semiconductor crystal wafer, described semiconductor film is corresponding are corresponding Region carry out deep groove etching, to form described semiconductor film;Wherein, described second surface and described first Surface is relative, and described deep groove etching makes described protective clear layer expose;
The semiconductor film surface that described protective clear layer is formed is measured with corrosion from the second surface of semiconductor crystal wafer Between difference in height;
The current thickness of semiconductor film described in mathematic interpolation according to described first degree of depth and described difference in height;
The region that described semiconductor film is corresponding is corroded by current thickness according to described semiconductor film further The thickness making semiconductor film reaches described expectation thickness.
Preferably, described method also includes after deposition protective clear layer, is formed on described protective clear layer Metal level.
Preferably, the region corresponding with described measuring flume, described semiconductor film is corresponding region has a common boundary;
The described semiconductor film measuring described protective clear layer and corrosion formation from the second surface of semiconductor crystal wafer Difference in height between surface includes:
Directly measure the height of described protective clear layer and semiconductor film intersection terraced structure.
Preferably, the zone isolation that described semiconductor film is corresponding region is corresponding with described measuring flume;
The described semiconductor film measuring described protective clear layer and corrosion formation from the second surface of semiconductor crystal wafer Difference in height between surface includes:
The crystal column surface second degree of depth to protective clear layer is measured from the second surface of semiconductor crystal wafer;
The crystal column surface the 3rd degree of depth to described semiconductor film surface is measured from the second surface of semiconductor crystal wafer;
Difference according to the 3rd degree of depth and second degree of depth obtains described difference in height.
Preferably, measure use step instrument to carry out.
Preferably, the described first surface at semiconductor crystal wafer makes at least one measurement with first degree of depth Groove includes:
On described semiconductor crystal wafer, equally distributed diverse location makes multiple measurements with first degree of depth Groove.
Preferably, described semiconductor crystal wafer is Silicon Wafer, and described protective clear layer is silicon nitride or silicon oxide.
The present invention by making the measurement for measuring semiconductor film thickness in advance in the front of semiconductor crystal wafer Groove so that corrosion progress can be monitored with measuring flume for reference in corrosion forms the technical process of semiconductor film, Meanwhile, measure, according to the counter structure of measuring flume, the thickness of semiconductor film that corrosion is formed, overcome due to The problem that the semiconductor film thickness caused of semiconductor crystal wafer thickness error is difficult to monitor and measure.
Accompanying drawing explanation
Fig. 1 is the stream of the method controlling the semiconductor film thickness that deep groove etching is formed of first embodiment of the invention Cheng Tu;
Fig. 2 is the stream that the example that the present invention second implements controls the method for the semiconductor film thickness that deep groove etching is formed Cheng Tu;
Fig. 3 a-Fig. 3 c is the schematic cross-section of semiconductor crystal wafer after different step in second embodiment of the invention;
Fig. 4 is the cross section signal of the Silicon Wafer in one preferred implementation of second embodiment of the invention after corrosion Figure;
Fig. 5 is the stream of the method controlling the semiconductor film thickness that deep groove etching is formed of third embodiment of the invention Cheng Tu;
Fig. 6 be third embodiment of the invention a preferred implementation in the cross section of Silicon Wafer after corrosion show It is intended to;
Fig. 7 is the semiconductor junction controlling the semiconductor film thickness that deep groove etching is formed of fourth embodiment of the invention The structural representation of structure.
Detailed description of the invention
Further illustrate technical scheme below in conjunction with the accompanying drawings and by detailed description of the invention.
Fig. 1 is the stream of the method controlling the semiconductor film thickness that deep groove etching is formed of first embodiment of the invention Cheng Tu.As it is shown in figure 1, described method includes:
Step 110, make at least one measuring flume with first degree of depth at the first surface of semiconductor crystal wafer; Wherein, described first degree of depth is more than the expectation thickness of described semiconductor film.
The expectation thickness that the degree of depth of measuring flume is set greater than semiconductor film is to form half in order to follow-up in corrosion During electrically conductive film, when the degree of depth of corrosion nearly forms the semiconductor film of expectation thickness, bottom measuring flume Wafer material is the most all corroded, consequently facilitating whether observe semiconductor film already close to expectation thickness. Further, the measuring flume degree of depth makes measuring flume compared with conference and tentatively corrodes existence height between the semiconductor film obtained Difference, this difference in height can be used for calculating the thickness tentatively corroding the semiconductor film obtained.
Step 120, in described measuring flume formed protective clear layer.
Protective clear layer uses the material of the corrosion that is not corroded to be formed, and its role is to the bottom for measuring flume There is provided be not corroded technique corrosion structure so that follow-up can by measure measuring flume surface to crystal column surface Distance and semiconductor film surface calculate the thickness of semiconductor film to the distance of crystal column surface.Secondly, thoroughly After bright protective layer prevents the material of measuring flume structured rear surface to be etched, etching liquid oozes from the second surface of wafer Thoroughly wafer is caused to damage to first surface.Meanwhile, protective layer is set to transparent, is in order in manufacture process In can expose by checking the region that measuring flume is corresponding whether this protective layer of translumination observation having corroded, Thus convenient in etching process, the time of control corrosion rate.
Step 130, the region that described semiconductor film is corresponding on the second surface of semiconductor crystal wafer and described survey The region that measuring tank is corresponding carries out deep groove etching, to form described semiconductor film;Wherein, described second surface with Described first surface is relative, and described deep groove etching makes described protective clear layer expose.
Tentatively corroding and form the semiconductor film with current thickness, meanwhile, this corrosion makes transparency protected Layer exposes, thus conveniently observes that the thickness of semiconductor film is already close to expectation thickness.
Step 140, measure partly leading of described protective clear layer and corrosion formation from the second surface of semiconductor crystal wafer Difference in height between body film surface.
Step 150, current according to semiconductor film described in the mathematic interpolation of described first degree of depth and described difference in height Thickness.
The region that described semiconductor film is corresponding is entered by step 160, current thickness according to described semiconductor film One step corrosion makes the thickness of semiconductor film reach described expectation thickness.
Measure and calculate after obtaining the thickness tentatively corroding the semiconductor film obtained, both can be according to current thickness Arrange technological parameter with expectation thickness further to be corroded thus control the thickness of semiconductor film and reach the phase Hope thickness.The step of this measurement-calculating-corrosion can be repeated as many times as desired the precision required for obtaining.
The present embodiment by making the measurement for measuring semiconductor film thickness in advance in the front of semiconductor crystal wafer Groove so that corrosion progress can be monitored with measuring flume for reference in corrosion forms the technical process of semiconductor film, Meanwhile, measure, according to the counter structure of measuring flume, the thickness of semiconductor film that corrosion is formed, overcome due to The problem that the semiconductor film thickness caused of semiconductor crystal wafer thickness error is difficult to monitor and measure.
Fig. 2 is the flow process that second embodiment of the invention controls the method for the semiconductor film thickness that deep groove etching is formed Figure.Second embodiment of the invention is introduced as a example by manufacturing thin film on Silicon Wafer, but, this area skill Art personnel are appreciated that the method for the present embodiment is equally applicable to such as germanium, GaAs, indium phosphide, antimony The semiconductor crystal wafer that other materials such as indium, carborundum, cadmium sulfide, gallium arsenic silicon, sapphire glass manufacture.
As in figure 2 it is shown, described method includes:
Step 210, make at least one measuring flume with first degree of depth at the first surface of Silicon Wafer;Wherein, Described first degree of depth is more than the expectation thickness of semiconductor film.
The size and location arranging measuring flume in the present embodiment makes region and the semiconductor film that measuring flume is corresponding Corresponding region has a common boundary.In a preferred embodiment, measuring flume forms the semiconductor film pair of a certain chip In the region answered and its size is less than this region.So, other flow process need not be made by manufacture process repair Change.
Fig. 3 a is the schematic cross-section of Silicon Wafer after step 210.Formed on the first surface 31 of Silicon Wafer 30 There is measuring flume 32.Measuring flume 32 has first degree of depth A.Such as, it is 8 micro-at desired semiconductor film thickness Meter Shi, the measuring flume of 15 micrometer depth of formation.
Step 220, in described measuring flume deposit protective clear layer.
The effect of protective clear layer is to provide the structure of the technique corrosion that is not corroded for the bottom of measuring flume, makes Follow-up can be by measuring measuring flume surface to the distance of crystal column surface and semiconductor film surface to wafer table The distance in face calculates the thickness of semiconductor film.Secondly, protective clear layer prevents the material of measuring flume structured rear surface After material is etched, etching liquid penetrates into first surface from the second surface of wafer and causes wafer to damage.Meanwhile, Protective layer is set to transparent, is to be in the fabrication process by checking the region that measuring flume is corresponding This protective layer of no translumination observation has corroded and has exposed, thus convenient in etching process, control corrosion rate Time.
Fig. 3 b is the schematic cross-section of Silicon Wafer after step 220.Inside deposition at measuring flume 32 is formed Protective clear layer 33.
In a preferred implementation of the present embodiment, protective clear layer selects silicon nitride (SiN) or oxidation Silicon (SiO2) formed as material.Silicon nitride and silicon oxide will not be used to corrode the corrosive liquid corrosion of Silicon Wafer, Therefore the reference surface measuring semiconductor film thickness can be provided during manufacturing semiconductor film.
Step 230, the region that described semiconductor film is corresponding on the second surface of semiconductor crystal wafer and described survey The region that measuring tank is corresponding carries out deep groove etching, to form described semiconductor film;Wherein, described second surface with Described first surface is relative, and described deep groove etching makes described protective clear layer expose.
In the present embodiment, carry out preliminary corrosion depth and carry out preliminary corrosion, after completing, observe Silicon Wafer Region corresponding to upper test trough whether printing opacity, if printing opacity, then illustrates that the thickness of semiconductor film is already close to the phase Hope the degree of depth, after needing to measure, further control technical process.
Fig. 3 c is the schematic cross-section of Silicon Wafer after step 230.As shown in Figure 3 c, after step 230, brilliant The second surface 34 of circle 30 is corroded and forms chamber, and the bottom in chamber is required semiconductor film 35.Step 230 Corrosion be preliminary corrosion, the silicon bottom test trough 32 is eroded by it, so that protective clear layer is revealed Go out.Owing to, in the present embodiment, the region that the region of test trough 32 correspondence is corresponding with semiconductor film 35 has a common boundary, Therefore, the protective clear layer 33 exposed and semiconductor film form the structure 36 of step at intersection.
Step 240, measure terraced structure height as the height between semiconductor film surface and protective clear layer It is poor to spend.
In the present embodiment, the region corresponding with semiconductor film due to protective clear layer has a common boundary, and both are having a common boundary Region forms the structure 36 of step, therefore can directly utilize step instrument and test the height of this terraced structure 36 Degree B.
Step 250, current according to semiconductor film described in the mathematic interpolation of described first degree of depth and described difference in height Thickness.
Described step is deducted by distance (namely first degree of depth) A to Silicon Wafer first surface bottom test trough The height B of structure 36 i.e. can obtain the thickness of current semiconductor film.
The region that described semiconductor film is corresponding is entered by step 260, current thickness according to described semiconductor film One step corrosion makes the thickness of semiconductor film reach described expectation thickness.
Measure and calculate after obtaining the thickness tentatively corroding the semiconductor film obtained, both can be according to current thickness Arrange technological parameter with expectation thickness further to be corroded thus control the thickness of semiconductor film and reach the phase Hope thickness.The step of this measurement-calculating-corrosion can be repeated as many times as desired the precision required for obtaining.
In a preferred implementation of the present embodiment, a step can also be included after step 220 220a, i.e. forms layer of metal layer on protective clear layer again.Described metal level is used for carrying out reflective, so may be used To become apparent from observe whether protective clear layer is exposed.
Fig. 4 is the schematic cross-section of the Silicon Wafer under this preferred implementation after corrosion.At protective clear layer 32 It is formed above metal level 37.
The present embodiment selects test trough to be formed in the region that semiconductor film has a common boundary so that quasiconductor after corrosion Transparency protected bottom the surface of film and test trough is shaped as terraced structure, is convenient for measuring both differences in height, Improve measurement efficiency.
It should be noted that Fig. 3,4 only illustrate for the cross section on Silicon Wafer chip area.This Skilled person is appreciated that in the fabrication process, a Silicon Wafer would generally make multiple with array The chip of form arrangement, each chip corresponds to a chip area.At least one core therein can be selected Panel region makes measuring flume.After making measuring flume, corresponding chip structure changes, and has manufactured It is non-serviceable after one-tenth, accordingly, it would be desirable to select according to practical situation in the quantity and distribution of measuring flume Select.Select rational measuring flume quantity, and make it be evenly distributed on the diverse location of whole Silicon Wafer, can To prevent from causing semiconductor film THICKNESS CONTROL that error occurs owing to Silicon Wafer itself is in uneven thickness.
Fig. 5 is the stream of the method controlling the semiconductor film thickness that deep groove etching is formed of third embodiment of the invention Cheng Tu.Third embodiment of the invention is introduced as a example by manufacturing thin film on Silicon Wafer, but, this area Those of skill will appreciate that, the method for the present embodiment is equally applicable to such as germanium, GaAs, indium phosphide, antimony Change the semiconductor crystal wafer that other materials such as indium, carborundum, cadmium sulfide, gallium arsenic silicon, sapphire glass manufacture.
As it is shown in figure 5, described method includes:
Step 510, make at least one measuring flume with first degree of depth at the first surface of Silicon Wafer.
Wherein, first degree of depth is more than the expectation thickness of semiconductor film.And, measuring flume at Silicon Wafer by individually It is made so that its region corresponding to region corresponding with semiconductor film is mutually isolated.
In an optimal way of the present invention, measuring flume can be formed as occupying whole the half of a certain chip Electrically conductive film region, so, on measuring flume and Silicon Wafer, other semiconductor film is mutually isolated.
Step 520, in described measuring flume deposit protective clear layer.
In the present embodiment, protective clear layer selects silicon nitride (SiN) or silicon oxide (SiO2) as material Formed.Silicon nitride and silicon oxide will not be corroded Silicon Wafer corrosive liquid corrosion, therefore can manufacture partly lead Body membrane process provides the reference surface measuring semiconductor film thickness.
Step 530, the region that described semiconductor film is corresponding on the second surface of Silicon Wafer and described measuring flume Corresponding region carries out deep groove etching, to form described semiconductor film;Wherein, described second surface is with described First surface is relative, and described deep groove etching makes described protective clear layer expose.
In the present embodiment, carry out preliminary corrosion depth and carry out preliminary corrosion, after completing, observe Silicon Wafer Region corresponding to upper test trough whether printing opacity, if printing opacity, then illustrates that the thickness of semiconductor film is already close to the phase Hope the degree of depth, after needing to measure, further control technical process.
Step 540, the semiconductor film formed with corrosion from the second surface described protective clear layer of measurement of Silicon Wafer Difference in height between surface.
In the present embodiment, isolate with the surface of semiconductor film due to the bottom of measuring flume so that between the two There is not the structure that can directly carry out height difference measuring, it is therefore desirable to carry out multiple step and carry out difference in height Measure.Specifically include:
Step 541, second degree of depth of measurement Silicon Wafer second surface to protective clear layer.
Step 542, the 3rd degree of depth of measurement Silicon Wafer second surface to described semiconductor film surface.
Step 543, difference according to the 3rd degree of depth and second degree of depth obtain described difference in height.
The method of the present embodiment also includes after step 540:
Step 550, current according to semiconductor film described in the mathematic interpolation of described first degree of depth and described difference in height Thickness.
The region that described semiconductor film is corresponding is entered by step 560, current thickness according to described semiconductor film One step corrosion makes the thickness of semiconductor film reach described expectation thickness.
Measure and calculate after obtaining the thickness tentatively corroding the semiconductor film obtained, both can be according to current thickness Arrange technological parameter with expectation thickness further to be corroded thus control the thickness of semiconductor film and reach the phase Hope thickness.The step of this measurement-calculating-corrosion can be repeated as many times as desired the precision required for obtaining.
In a preferred implementation of the present embodiment, a step can also be included after step 520 520a, i.e. forms layer of metal layer on protective clear layer again.Described metal level is used for carrying out reflective, so may be used To become apparent from observe whether protective clear layer is exposed.
Fig. 6 is the schematic cross-section of the Silicon Wafer under this preferred implementation after corrosion.As shown in Figure 6, Silicon Wafer 60 includes the first chip area 61 and the second chip area 62, and measuring flume 63 is formed at the first chip In region, occupy the entire area of semiconductor film in the first chip area, so that the first chip area 61 Form an independent process control module structure.Protective clear layer 64 it is formed with bottom measuring flume 63.Enter One step ground, is formed above metal level 65 at protective clear layer.There is corrosion to be formed in the lower section of Silicon Wafer 60 First chamber 66 and the second chamber 67, the bottom in the first chamber 66 is protective clear layer 64, the bottom in the second chamber 67 It it is the semiconductive thin film 68 of the second chip area 62 correspondence.
The present embodiment is by being formed as test trough and the region of semiconductor film isolation so that the area of test trough Can be formed bigger, it is simple to observe whether protective clear layer exposes.Simultaneously as with semiconductor film region Isolation, the protective clear layer in test trough structure further enhances for preventing the ability of corrosive liquid seepage.
It should be noted that Fig. 6 only illustrate for the cross section on Silicon Wafer chip area.Ability Field technique personnel are appreciated that in the fabrication process, a Silicon Wafer would generally make multiple with array shape The chip of formula arrangement, the corresponding chip area of each chip.At least one chip region therein can be selected Territory makes measuring flume.After making measuring flume, corresponding chip structure changes, after having manufactured It is non-serviceable, accordingly, it would be desirable to select according to practical situation in the quantity and distribution of measuring flume. Select rational measuring flume quantity, and make it be evenly distributed on the diverse location of whole Silicon Wafer, can in case There is error in the semiconductor film thickness only caused on wafer owing to Silicon Wafer itself is in uneven thickness.
Fig. 7 is partly leading of the semiconductor film thickness for controlling deep groove etching formation of fourth embodiment of the invention The structural representation of body structure.As it is shown in fig. 7, described structure includes being formed at the first of semiconductor crystal wafer 70 The measuring flume 72 with first degree of depth on surface 71, wherein, described first degree of depth is more than described semiconductor film Expectation thickness, and described first surface is relative with the second surface of deep groove etching to be carried out.By measuring flume It is for the follow-up process forming semiconductor film in corrosion that the degree of depth is set greater than the expectation thickness of semiconductor film In, when the degree of depth of corrosion nearly forms the semiconductor film of expectation thickness, the material at the measuring flume back side is whole It is corroded, consequently facilitating whether observe semiconductor film already close to expectation thickness.Further, the measuring flume degree of depth Relatively conference makes measuring flume and tentatively corrodes between the semiconductor film obtained and there is difference in height, and this difference in height can be used In calculating the thickness tentatively corroding the semiconductor film obtained.
Described structure also includes the protective clear layer 73 being formed in measuring flume.Acting on of protective clear layer 73 The structure of the technique corrosion that is not corroded is provided so that follow-up can be measured by measurement in the bottom for measuring flume Rooved face calculates semiconductor film to the distance of crystal column surface and semiconductor film surface to the distance of crystal column surface Thickness.Secondly, after protective clear layer prevents the material of measuring flume structured rear surface to be etched, etching liquid from The second surface of wafer penetrates into first surface and causes wafer to damage.Meanwhile, protective layer is set to transparent, It is in order in the fabrication process can be by checking whether this protective layer of translumination observation is in the region that measuring flume is corresponding No corrosion exposes, thus convenient in etching process, the time of control corrosion rate.
In a preferred implementation of the present embodiment, described structure can also include being formed at transparency protected Metal level 74 on layer 73.Described metal level is used for carrying out reflective, so can observe transparent with becoming apparent from Whether protective layer 73 is exposed.
In a preferred implementation of the present embodiment, region corresponding to described semiconductor film and described measurement The region that groove is corresponding has a common boundary.
Or, in another preferred implementation of the present embodiment, region corresponding to described semiconductor film with The zone isolation that described measuring flume is corresponding.
The present embodiment by making the measurement for measuring semiconductor film thickness in advance in the front of semiconductor crystal wafer Groove so that corrosion progress can be monitored with measuring flume for reference in corrosion forms the technical process of semiconductor film, Meanwhile, measure, according to the counter structure of measuring flume, the thickness of semiconductor film that corrosion is formed, overcome due to The problem that the semiconductor film thickness caused of semiconductor crystal wafer thickness error is difficult to monitor and measure.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for this area skill For art personnel, the present invention can have various change and change.All institutes within spirit and principles of the present invention Any modification, equivalent substitution and improvement etc. made, should be included within the scope of the present invention.

Claims (7)

1. the method controlling the semiconductor film thickness that deep groove etching is formed, including:
First surface at semiconductor crystal wafer makes at least one measuring flume with first degree of depth;Wherein, institute State first degree of depth expectation thickness more than described semiconductor film;
Protective clear layer is formed in described measuring flume;
Region and described measuring flume that on the second surface of semiconductor crystal wafer, described semiconductor film is corresponding are corresponding Region carry out deep groove etching, to form described semiconductor film;Wherein, described second surface and described first Surface is relative, and described deep groove etching makes described protective clear layer expose;
The semiconductor film surface that described protective clear layer is formed is measured with corrosion from the second surface of semiconductor crystal wafer Between difference in height;
The current thickness of semiconductor film described in mathematic interpolation according to described first degree of depth and described difference in height;
The region that described semiconductor film is corresponding is corroded by current thickness according to described semiconductor film further The thickness making semiconductor film reaches described expectation thickness.
Method the most according to claim 1, it is characterised in that described method is forming protective clear layer After also include, on described protective clear layer formed metal level.
Method the most according to claim 1, it is characterised in that region corresponding to described semiconductor film with The region that described measuring flume is corresponding has a common boundary;
The described semiconductor film measuring described protective clear layer and corrosion formation from the second surface of semiconductor crystal wafer Difference in height between surface includes:
Directly measure the height of described protective clear layer and semiconductor module intersection terraced structure.
Method the most according to claim 1, it is characterised in that region corresponding to described semiconductor film with The zone isolation that described measuring flume is corresponding;
The described semiconductor film measuring described protective clear layer and corrosion formation from the second surface of semiconductor crystal wafer Difference in height between surface includes:
The crystal column surface second degree of depth to protective clear layer is measured from the second surface of semiconductor crystal wafer;
The crystal column surface the 3rd degree of depth to described semiconductor film surface is measured from the second surface of semiconductor crystal wafer;
Difference according to the 3rd degree of depth and second degree of depth obtains described difference in height.
5. according to the method described in claim 3 or 4, it is characterised in that measure and use step instrument to carry out.
Method the most according to claim 1, it is characterised in that described the first table at semiconductor crystal wafer Face makes at least one measuring flume with first degree of depth and includes:
On described semiconductor crystal wafer, equally distributed diverse location makes multiple measurements with first degree of depth Groove.
Method the most according to claim 1, it is characterised in that described semiconductor crystal wafer is Silicon Wafer, Described protective clear layer is silicon nitride or silicon oxide.
CN201310006414.0A 2013-01-08 2013-01-08 Control method and the semiconductor structure of the semiconductor film thickness that deep groove etching is formed Active CN103065942B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310006414.0A CN103065942B (en) 2013-01-08 2013-01-08 Control method and the semiconductor structure of the semiconductor film thickness that deep groove etching is formed

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310006414.0A CN103065942B (en) 2013-01-08 2013-01-08 Control method and the semiconductor structure of the semiconductor film thickness that deep groove etching is formed

Publications (2)

Publication Number Publication Date
CN103065942A CN103065942A (en) 2013-04-24
CN103065942B true CN103065942B (en) 2016-10-19

Family

ID=48108514

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310006414.0A Active CN103065942B (en) 2013-01-08 2013-01-08 Control method and the semiconductor structure of the semiconductor film thickness that deep groove etching is formed

Country Status (1)

Country Link
CN (1) CN103065942B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104377141B (en) * 2013-08-16 2017-05-03 无锡华润华晶微电子有限公司 Method for detecting actual critical dimension and over-etching of deep groove structure in wafer
CN112271143A (en) * 2020-09-25 2021-01-26 华东光电集成器件研究所 Monitoring method for residual thickness of silicon wafer film layer corrosion
CN113651291B (en) * 2021-07-15 2023-11-24 复旦大学 Preparation method of self-supporting micron-thickness silicon diaphragm

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3888708A (en) * 1972-02-17 1975-06-10 Kensall D Wise Method for forming regions of predetermined thickness in silicon
EP0362090A1 (en) * 1988-09-29 1990-04-04 Société Anonyme : VECTAVIB Method of producing a mechanical device comprising a sensitive portion of a given thickness, and device obtained by said method
CN1391234A (en) * 2002-07-19 2003-01-15 中国科学院上海微系统与信息技术研究所 Method for preparing tip of silicon with three protective surfaces at its bottom
CN1516257A (en) * 2003-01-10 2004-07-28 北京大学 CMOS circuit and body silicon micromechanical system integraled method
CN101517728A (en) * 2006-09-22 2009-08-26 Nxp股份有限公司 Electronic device and method for making the same
CN101802588A (en) * 2007-08-02 2010-08-11 威科仪器公司 The method that is used for the probe unit and the processing probe unit of gauging instrument
CN102097287A (en) * 2009-12-15 2011-06-15 北大方正集团有限公司 Method for monitoring chip groove depth and wafer

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3888708A (en) * 1972-02-17 1975-06-10 Kensall D Wise Method for forming regions of predetermined thickness in silicon
EP0362090A1 (en) * 1988-09-29 1990-04-04 Société Anonyme : VECTAVIB Method of producing a mechanical device comprising a sensitive portion of a given thickness, and device obtained by said method
CN1391234A (en) * 2002-07-19 2003-01-15 中国科学院上海微系统与信息技术研究所 Method for preparing tip of silicon with three protective surfaces at its bottom
CN1516257A (en) * 2003-01-10 2004-07-28 北京大学 CMOS circuit and body silicon micromechanical system integraled method
CN101517728A (en) * 2006-09-22 2009-08-26 Nxp股份有限公司 Electronic device and method for making the same
CN101802588A (en) * 2007-08-02 2010-08-11 威科仪器公司 The method that is used for the probe unit and the processing probe unit of gauging instrument
CN102097287A (en) * 2009-12-15 2011-06-15 北大方正集团有限公司 Method for monitoring chip groove depth and wafer

Also Published As

Publication number Publication date
CN103065942A (en) 2013-04-24

Similar Documents

Publication Publication Date Title
CN103065942B (en) Control method and the semiconductor structure of the semiconductor film thickness that deep groove etching is formed
CN105241369B (en) A kind of MEMS strain gauges chip and its manufacturing process
CN101124467B (en) Micro slit viscometer with monolithically integrated pressure sensors
US11232956B2 (en) Electrochemical additive manufacturing of interconnection features
CN103373700A (en) Methods for producing a cavity within a semiconductor substrate
CN103344374A (en) Hidden-type MEMS pressure sensor sensitive chip and manufacturing method thereof
CN102427046A (en) Electrochemical deposition result determining method
CN202075068U (en) Single silicon substrate micropressure sensor of high stability and high sensitivity
CN105905866A (en) Composite sensor and production method
US11881412B2 (en) Electrochemical additive manufacturing method using deposition feedback control
CN105021328A (en) Piezoresistive pressure sensor compatible with CMOS process and preparation method of piezoresistive pressure sensor
CN110155937A (en) A kind of high consistency pressure sensor chip preparation method of low cost
CN118533230A (en) Ocean temperature and salt deep flow integrated micro-nano sensor and preparation method thereof
CN104165715B (en) A kind of pressure transducer manufacture method and structure thereof
CN107342254B (en) The calibration method of crystal edge etching machine bench
CN108751122A (en) A kind of three-dimensional micro-heater and preparation method thereof
CN107452642A (en) A kind of detection method of epitaxial structure etching rate
CN102522436B (en) Silicon chip for testing bulk service life, silicon chip manufacturing method, and bulk service life test method
CN104697700B (en) A kind of piezoresistive pressure gage chip structure and preparation method thereof
CN106125163B (en) Highly sensitive huge pressure drag rain sensor of micro-nano and preparation method thereof, measurement structure
CN102446783A (en) Method used for monitoring ion implantation dosage
US9211626B2 (en) Semiconductor device and grinding method of semiconductor device
CN109728123B (en) Ultrathin silicon PIN radiation detector based on bonded substrate and preparation method
CN103528567B (en) Tilt angle sensor based on pressure sensing
CN102491260A (en) Method for manufacturing flow sensor by etch self-stopping technology

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20170905

Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8

Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd.

Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China

Patentee before: Wuxi CSMC Semiconductor Co., Ltd.

TR01 Transfer of patent right