CN100364094C - Chip integrated by FinFET circuit and nano electromechanical beam and preparing method - Google Patents
Chip integrated by FinFET circuit and nano electromechanical beam and preparing method Download PDFInfo
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- CN100364094C CN100364094C CNB2005100050317A CN200510005031A CN100364094C CN 100364094 C CN100364094 C CN 100364094C CN B2005100050317 A CNB2005100050317 A CN B2005100050317A CN 200510005031 A CN200510005031 A CN 200510005031A CN 100364094 C CN100364094 C CN 100364094C
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Abstract
The present invention relates to a chip integrated with a nano electromechanical beam by a FinFET circuit and a making method thereof. The product of the present invention comprises a chip body. The present invention is characterized in that the chip body comprises an electromechanical region and a circuit region, wherein the electromechanical region comprises a fixed end which is arranged on the chip body, a nano electromechanical beam with fixed single end or fixed double ends and an electromechanical region electrode; the circuit region comprises a circuit system which is built by using a FinFET as a unit; a FinFET unit comprises a source, drain, Fin and a grid; the grid crosses the Fin; the circuit region is connected with the electromechanical region by a metal lead wire; in the electromechanical region, the metal lead wire is connected with the fixed end or an electrode of the electromechanical region; in the circuit region, the metal lead wire is connected with the grid or the source or the drain of the FinFET unit of a circuit system; external connection ports of the circuit region and the electromechanical region are respectively communicated with external connection wiring. The present invention can be used for making an NEMS with high performance; besides, the integration level and the production efficiency of systems are greatly improved, and the production cost of industrialization is reduced. The present invention is mainly applied to fields, such as little-change environment of sensing, radio frequency, detection, etc.
Description
Technical field
The present invention relates to a kind of chip and preparation method thereof, particularly about integrated chip of a kind of FinFET (Fin Field EffectTransistor fin-shaped field effect pipe) circuit and nano electromechanical beam and preparation method thereof.The inventive method make the deep-submicron high speed integrated circuit with receive Mechatronic Systems (Nano-Electromechanical Systems, hereinafter to be referred as NEMS) device organically combines, the signal that can solve the NEMS device is preferably drawn and is handled problems, and improves the integrated level and the production efficiency of system greatly.
Background technology
After entering the deep-submicron yardstick, a kind of Novel MOS transistor arrangement FinFET of function admirable comes into one's own day by day, has become transistorized important development direction, has a extensive future.Can realize the device such as sensing, calculating, communication, storage, execution of novel concept based on the NEMS technology, its performance can break through the limit of existing conventional device such as MEMS (MEMS (micro electro mechanical system)) device, become the raising of the order of magnitude, comprise China, NEMS has become a worldwide important research focus.Nano electromechanical beam is a kind of basic NEMS device architecture, because its scale effect and skin effect, has very high resonance frequency, and motion or state are very sensitive to the minor variations in the environment.That is to say that nano electromechanical beam can be used for producing dither, also can be used for the minor variations of sensitivity, testing environment etc., so it there is important application in fields such as sensing, radio frequency, detections.But one of challenge that development NEMS faces is a signal draws and handles relatively difficulty.
Summary of the invention
Draw and handle problems at the signal of above-mentioned NEMS device, the purpose of this invention is to provide integrated chip of a kind of FinFET circuit and nano electromechanical beam and preparation method thereof.
To achieve these goals, the present invention takes following technical scheme: a kind of FinFET circuit and the integrated chip of nano electromechanical beam, it comprises a chip body, it is characterized in that: comprise electromechanical area and circuit region on the described chip body, described electromechanical area comprises the stiff end that is arranged on the described chip body, nano electromechanical beam and electromechanical area electrode that single-ended or both-end is fixing; Described circuit region comprises with FinFET being the Circuits System of cell formation, described FinFET comprises source, leakage, Fin and grid in the unit, described grid are crossed over described Fin, connect by metal lead wire between described circuit region and the electromechanical area, described metal lead wire connects grid or the source or the leakage of FinFET unit in the described Circuits System of the described stiff end of described electromechanical area or described electromechanical area electrode and described circuit region, and the external-connected port of described circuit region and electromechanical area is communicated with external wiring respectively.
The manufacture method of a kind of FinFET circuit and nano electromechanical beam integrated chip, it is characterized in that: it may further comprise the steps: chip substrate is selected and cleaned in (1); (2) at described substrate surface resist coating, make circuit region by lithography, and described circuit region is mixed; (3) at described substrate surface resist coating, make electromechanical area by lithography, and described electromechanical area is mixed; (4) at source, leakage and the Fin of described circuit region formation FinFET, form nano electromechanical beam, stiff end and electromechanical area electrode at described electromechanical area; (5) the overall thermal oxidation forms silicon dioxide, at described silica surface deposit grid material, and produces gate figure; (6) whole resist coating makes circuit region by lithography, and described circuit region is mixed; (7) whole deposit silicon dioxide, and open the hole at described silicon dioxide layer exposes the external connection end of FinFET circuit and nano electromechanical beam, and the lead end that is connected with electromechanical area of circuit region; (8) whole depositing metal makes the metal lead wire figure by lithography, finishes being electrically connected between FinFET circuit and the nano electromechanical beam, and the wiring of circuit; (9) whole silicon dioxide of corrosion parcel nano electromechanical beam discharge the nano electromechanical beam structure, obtain chip product.
Form source, leakage and the Fin of FinFET at described circuit region, form in the process of nano electromechanical beam, stiff end and electromechanical area electrode at described electromechanical area, adopt the photoresist ashing technology, concrete steps are as follows: (1) adopts the photoresist ashing technology to form little mask of nano electromechanical beam and Fin; (2) photoetching with photoresist forms and comprises nano beam stiff end, the mask pattern of the source of electromechanical area electrode mask and FinFET and the mask of leakage; (3) constitute compound mask by described mask pattern and little mask, carry out etching, form source, leakage, the Fin of circuit region FinFET, and electromechanical area electrode, stiff end and the nano electromechanical beam that does not discharge.
Form source, leakage and the Fin of FinFET at described circuit region, form employing side wall technology in nano electromechanical beam, stiff end and the electromechanical area electrode process at described electromechanical area, concrete steps are as follows: (1) is deposit layer of silicon dioxide and one deck polysilicon successively, obtains polysilicon graphics after the photoetching; (2) deposit layer of silicon dioxide, the described silicon dioxide of dry etching, thus form the sidewall structure that silicon dioxide constitutes; (3) etch polysilicon stays sidewall structure; (4) silicon dioxide layer below the dry etching exposes silicon face; (5) photoetching with photoresist erodes unwanted sidewall structure; (6) photoetching with photoresist, form the mask pattern on the single-crystal silicon device layer, constitute compound mask, carry out etching with described mask pattern and described sidewall structure, form source, leakage, the Fin of described circuit region FinFET, and electromechanical area electrode, stiff end and the nano electromechanical beam that do not discharge; (7) remove the silicon dioxide sidewall structure with dry etching.
Form the Fin of FinFET at described circuit region, and in the process of the nano electromechanical beam that described electromechanical area forms, adopt one of electron beam exposure or normal optical lithography, form source and the leakage of FinFET at described circuit region, and in stiff end that electromechanical area forms and electromechanical area electrode process, adopt the normal optical lithography.
Described gate figure adopts a kind of formation in electron beam exposure, photoresist ashing, the normal optical lithography.
Described gate figure adopts the side wall technology to form, and concrete steps are as follows: (1) is adopted the ion injection that polysilicon is carried out grid and is mixed; (2) priority deposit layer of silicon dioxide and one deck polysilicon obtain polysilicon graphics after the photoetching; (3) deposit layer of silicon dioxide, the described silicon dioxide of dry etching, thus form the sidewall structure that silicon dioxide constitutes; (4) etch polysilicon stays sidewall structure; (5) silicon dioxide layer below the dry etching exposes silicon face; (6) photoetching with photoresist erodes unwanted sidewall structure; (7) photoetching forms the mask pattern of grid, constitutes compound mask with described mask pattern and described sidewall structure, and polysilicon layer is carried out etching, forms gate figure.
When whole silicon dioxide of corrosion parcel nano electromechanical beam, adopt a kind of in dry method, sublimed method or the wet method.
The present invention is owing to take above technical scheme, it has the following advantages: 1, the present invention is integrated in FinFET circuit and nano electromechanical beam on the chip, make the deep-submicron high speed integrated circuit and receive the Mechatronic Systems device and organically combine, make product of the present invention integrate whole advantages of two technology, have high resonance frequency, the contour performance index of sensitivity, it has a extensive future.2, the present invention passes through process integration, creatively proposed to adopt same flow process FinFET circuit and nano electromechanical beam to be carried out a whole set of process of integrated parallel processing, realized that nano electromechanical beam and peripheral signal draw the integrated manufacturing of monolithic of circuit, signal processing circuit, better solve the NEMS device signal thus and drawn and handled difficult problem, made things convenient for design, production and the test of NEMS, will play positive impetus the development of NEMS.3, not only more high-performance NEMS potentiality are very big to producing in the present invention, and improved the integrated level and the production efficiency of system greatly, reduced industrial production cost.The present invention has important application in fields such as various sensings, radio frequency, testing environment minor variations.
Description of drawings
Fig. 1～Figure 22 is the vertical view and the sectional view of technological process of the present invention
Figure 23 is the schematic three dimensional views (silicon dioxide layer of protection does not draw) that the present invention processes the device that obtains.
Figure 24～36th, another embodiment of technological process of the present invention (adopting the side wall technology to form nano electromechanical beam and Fin).
Figure 37～43rd, an embodiment again of technological process of the present invention (adopting the side wall technology to form nano electromechanical beam, Fin and gate figure)
Embodiment
Embodiment 1:
Adopt SOI (two-layer silicon therebetween one deck silica) chip substrate, by adopting photoresist ashing fabrication techniques Fin and nano electromechanical beam, adopt the normal optical lithography to make gate figure, concrete steps are as follows:
1, selects soi wafer as chip substrate 1, and clean;
2, as shown in Figure 1 and Figure 2,3 photoetching with photoresist (be common photoetching corrosion method, below identical) go out circuit region 2, are mask with photoresist 3, with ion implantation (following identical) circuit region 2 are mixed 4, remove photoresist 3 then;
3, as shown in Figure 3, Figure 4,5 making electromechanical area 6 by lithography with photoresist, is mask with photoresist 5 then, and electromechanical area 6 is mixed 7, removes photoresist 5 then;
4,, adopt the photoresist ashing technology to form little mask 8 of nano electromechanical beam and Fin as Fig. 5, shown in Figure 6;
5, photoetching with photoresist forms nano electromechanical beam stiff end, electromechanical area electrode, the source of FinFET, the mask pattern of leakage;
6, as Fig. 7, shown in Figure 8, constitute compound mask by above-mentioned mask pattern and little mask 8, dry method is carried out etching to single-crystal silicon device layer, form source 9, leakage 10, the Fin11 of circuit region FinFET, and the stiff end 12 of electromechanical area, nano electromechanical beam 13 of Shi Fanging and mechanical region electrode 14 are not removed photoresist and little mask 8 then;
7, as Fig. 9, shown in Figure 10, the overall thermal oxidation, growthing silica 15 is as the gate medium of FinFET;
8, at silica 15 surface deposition one deck grid material 16, for example polysilicon, metal silicide or metals;
9, as Figure 11, shown in Figure 12, photoetching with photoresist, dry etching goes out the figure of grid 17, removes photoresist then;
10, as Figure 13, shown in Figure 14,18 make circuit region 19 by lithography with photoresist, 18 circuit region 19 is mixed 20 with photoresist for mask, remove photoresist 18 then;
11, as Figure 15, shown in Figure 16, whole deposit silicon dioxide 21 forms circuit protecting layer;
12, as Figure 17, shown in Figure 180, photoetching corrosion is left through hole on silicon dioxide 21, exposes the external connection end 22,23,24,25 of FinFET circuit and nano electromechanical beam, and the lead end 26,27 that is connected with electromechanical area of circuit region, removes photoresist then;
13, as Figure 19, shown in Figure 20, depositing metal makes metal lead wire figure 28 by lithography, thereby realizes being electrically connected between FinFET circuit and the nano electromechanical beam, and the wiring of circuit;
14, as Figure 21, shown in Figure 22, electromechanical area 30 is left in 29 photoetching on silicon dioxide 21 with photoresist, exposes the zone of nano electromechanical beam 13, and the whole silicon dioxide 21 with wet etching parcel nano electromechanical beam 13 discharge structure.
15, remove residual photoresist 29, just obtain the chip (as shown in figure 23) that the present invention is integrated with FinFET circuit and nano electromechanical beam.
In the foregoing description, step 1, is therefore mixed respectively because the requirement of mixing is different with step 2, but the doping order can change.Kind of impurity (as phosphorus, arsenic etc.) and dopant dose all can change.
Embodiment 2:
Present embodiment adopts the soi chip substrate, adopts the side wall technology to form Fin and nano electromechanical beam, adopts electron beam exposure to form the polysilicon gate figure, and concrete steps are as follows:
1, as shown in figure 24, select soi chip substrate 31, and substrate is cleaned;
2, with embodiment 1 identical (as shown in Figure 1 and Figure 2), make circuit region by lithography, and be mask, remove photoresist after circuit region is mixed with the photoresist;
3, with embodiment 1 identical (as shown in Figure 3, Figure 4), make electromechanical area by lithography, and be mask, remove photoresist after electromechanical area is mixed with the photoresist;
4, as shown in figure 25, deposit layer of silicon dioxide successively 32 and one deck polysilicon 33, photoetching corrosion obtains polysilicon graphics, removes photoresist then;
5, as shown in figure 26, the deposit layer of silicon dioxide, this layer of dry etching silicon dioxide, thus form the sidewall structure 34 that silicon dioxide constitutes;
6, as shown in figure 27, dry method or wet etching polysilicon 33 stay sidewall structure 34;
7, as shown in figure 28, the silicon dioxide layer 32 below the dry etching exposes SOI substrate 31 surfaces;
8, as shown in figure 29, photoetching is with photoresist fallen unwanted sidewall structure 34 by wet etching, stay the sidewall structure 34 that needs, and removes photoresist then;
9, as shown in figure 30, photoetching with photoresist forms the mask pattern on the single-crystal silicon device layer, constitute compound mask with this figure and above-mentioned sidewall structure, single-crystal silicon device layer is carried out dry etching, form source, leakage, the Fin35 of FinFET and comprise the nano electromechanical beam 36 that does not discharge of nano electromechanical beam stiff end and mechanical region electrode 37 etc.;
10, as shown in figure 31, remove silicon dioxide sidewall structure 34 with dry etching;
11, shown in figure 32, the overall thermal oxidation, growthing silica 38 is as the gate medium of FinFET;
12, as shown in figure 33, at silicon dioxide 38 surface deposition one deck polysilicons 39 as grid material;
13, as shown in figure 34, the employing electron beam exposure forms the polysilicon gate figure 40 of FinFET, and dry etching polysilicon 39, removes the photoresist of electron beam exposure then;
14, with embodiment 1 identical (shown in Figure 13～20), make circuit region with photoresist by lithography, and circuit region is mixed; Whole deposit silicon dioxide 21 forms circuit protecting layer; Photoetching corrosion is left through hole 22,23,24,25,26,27 on silicon dioxide 21, exposes the external connection end of FinFET circuit and nano electromechanical beam, and the lead end that is connected with electromechanical area of circuit region;
15, as shown in figure 35, depositing metal makes metal lead wire figure 41 by lithography, thereby realizes being electrically connected and the wiring of circuit between FinFET circuit and the nano electromechanical beam;
16, as shown in figure 36, electromechanical area is left in photoetching on silicon dioxide, and the whole silicon dioxide with dry etching parcel nano electromechanical beam 36 discharge structure, and remove photoresist, just obtain product of the present invention.
Embodiment 3:
In the present embodiment, if the mode that all adopts the side wall technology to form in Fin, nano electromechanical beam and polysilicon gate figure make, then step 1～12 and embodiment 2 identical (as Figure 24～shown in Figure 33), the step of remainder is:
13, as shown in figure 37, adopt ion to inject and mixed in polysilicon 39 surfaces as grid material, promptly finish grid and mix;
14, as shown in figure 38, identical with embodiment 2 steps 4, successively deposit one deck two silicon dioxide 42 and one deck polysilicon 43 obtain polysilicon graphics after the photoetching, also marked among the figure under silicon dioxide and the polysilicon figure 44 as a reference;
15, as shown in figure 39 (Figure 39 is the sectional side view at Figure 38 dotted line place), the deposit layer of silicon dioxide, this layer of dry etching silicon dioxide, thus form the sidewall structure 45 that silicon dioxide constitutes;
16, as shown in figure 40, dry method or wet etching polysilicon 43 stay sidewall structure 45;
17, as shown in figure 41, the silicon dioxide layer 42 below the dry etching exposes polysilicon 39 surfaces;
18, as shown in figure 42, photoetching with photoresist erodes unwanted side wall mask 45, removes photoresist;
19, as shown in figure 43, photoetching forms the mask pattern of grid, and constitutes compound mask with this figure and above-mentioned sidewall structure, and polysilicon layer 39 is carried out dry etching, forms gate figure 46;
20, as shown in figure 44, making circuit region by lithography, is mask with the side wall on the polysilicon gate figure 46 45, and circuit region is mixed, and has also marked the figure 46 under the side wall 45 among the figure, and the figure 44 under the gate oxide as a reference;
21, identical with embodiment 1 step 11～13 (as Figure 15～shown in Figure 20) whole deposit silicon dioxide forms circuit protecting layer; Photoetching corrosion is left through hole on silicon dioxide, exposes the external connection end of FinFET circuit and nano electromechanical beam, and the lead end that is connected with electromechanical area of circuit; Depositing metal carves the metal lead wire figure, thereby realizes being electrically connected and the wiring of circuit between FinFET circuit and the nano electromechanical beam;
22, electromechanical area is left in photoetching on silicon dioxide, adopts whole silicon dioxide of sublimed method corrosion parcel nano electromechanical beam, and structure is discharged, and removes photoresist, obtains product of the present invention.
In the various embodiments described above, the SOI substrate can adopt thin film deposition equivalence SOI substrate to replace, as silicon substrate+silicon dioxide+polysilicon structure etc.; Aspect the formation of Fin, nano electromechanical beam and gate figure, can adopt multiple technologies ways and meanses such as electron beam lithography, side wall technology, photoresist ashing method, common photoetching; In the selection of grid material, can use polysilicon, metal silicide or metal gate; When whole silicon dioxide of corrosion parcel nano electromechanical beam discharge structure, can adopt the corrosion technology of various routines such as dry method, sublimed method or wet method.
Claims (10)
1. FinFET circuit and the integrated chip of nano electromechanical beam, it comprises a chip body, it is characterized in that: comprise electromechanical area and circuit region on the described chip body, described electromechanical area comprises the stiff end that is arranged on the described chip body, nano electromechanical beam and electromechanical area electrode that single-ended or both-end is fixing; Described circuit region comprises with FinFET being the Circuits System of cell formation, described FinFET comprises source, leakage, Fin and grid in the unit, described grid are crossed over described Fin, connect by metal lead wire between described circuit region and the electromechanical area, described metal lead wire connects grid or the source or the leakage of FinFET unit in the described Circuits System of the described stiff end of described electromechanical area or described electromechanical area electrode and described circuit region, and the external-connected port of described circuit region and electromechanical area is communicated with external wiring respectively.
2. the manufacture method of FinFET circuit and nano electromechanical beam integrated chip, it is characterized in that: it may further comprise the steps:
(1) selects and cleans chip substrate;
(2) at described substrate surface resist coating, make circuit region by lithography, and described circuit region is mixed;
(3) at described substrate surface resist coating, make electromechanical area by lithography, and described electromechanical area is mixed;
(4) at source, leakage and the Fin of described circuit region formation FinFET, form nano electromechanical beam, stiff end and electromechanical area electrode at described electromechanical area;
(5) the overall thermal oxidation forms silicon dioxide, at described silica surface deposit grid material, and produces gate figure;
(6) whole resist coating makes circuit region by lithography, and described circuit region is mixed;
(7) whole deposit silicon dioxide, and open the hole at described silicon dioxide layer exposes the external connection end of FinFET circuit and nano electromechanical beam, and the lead end that is connected with electromechanical area of circuit region;
(8) whole depositing metal makes the metal lead wire figure by lithography, finishes being electrically connected between FinFET circuit and the nano electromechanical beam, and the wiring of circuit;
(9) whole silicon dioxide of corrosion parcel nano electromechanical beam discharge the nano electromechanical beam structure, obtain chip product.
3. the manufacture method of a kind of FinFET circuit as claimed in claim 2 and nano electromechanical beam integrated chip, it is characterized in that: the source, leakage and the Fin that form FinFET at described circuit region, form in the process of nano electromechanical beam, stiff end and electromechanical area electrode at described electromechanical area, adopt the photoresist ashing technology, concrete steps are as follows:
(1) adopt the photoresist ashing technology to form little mask of nano electromechanical beam and Fin;
(2) photoetching with photoresist forms and comprises nano beam stiff end, the mask pattern of the source of electromechanical area electrode mask and FinFET and the mask of leakage;
(3) constitute compound mask by described mask pattern and little mask, carry out etching, form source, leakage, the Fin of circuit region FinFET, and electromechanical area electrode, stiff end and the nano electromechanical beam that does not discharge.
4. the manufacture method of a kind of FinFET circuit as claimed in claim 2 and nano electromechanical beam integrated chip, it is characterized in that: the source, leakage and the Fin that form FinFET at described circuit region, form employing side wall technology in nano electromechanical beam, stiff end and the electromechanical area electrode process at described electromechanical area, concrete steps are as follows:
(1) priority deposit layer of silicon dioxide and one deck polysilicon obtain polysilicon graphics after the photoetching;
(2) deposit layer of silicon dioxide, the described silicon dioxide of dry etching, thus form the sidewall structure that silicon dioxide constitutes;
(3) etch polysilicon stays sidewall structure;
(4) silicon dioxide layer below the dry etching exposes silicon face;
(5) photoetching with photoresist erodes unwanted sidewall structure;
(6) photoetching with photoresist, form the mask pattern on the single-crystal silicon device layer, constitute compound mask, carry out etching with described mask pattern and described sidewall structure, form source, leakage, the Fin of described circuit region FinFET, and electromechanical area electrode, stiff end and the nano electromechanical beam that do not discharge;
(7) remove the silicon dioxide sidewall structure with dry etching.
5. the manufacture method of a kind of FinFET circuit as claimed in claim 2 and nano electromechanical beam integrated chip, it is characterized in that: the Fin that forms FinFET at described circuit region, and in the process of the nano electromechanical beam that described electromechanical area forms, adopt one of electron beam exposure or normal optical lithography, form source and the leakage of FinFET at described circuit region, and in stiff end that electromechanical area forms and electromechanical area electrode process, adopt the normal optical lithography.
6. as the manufacture method of claim 2 or 3 or 4 or 5 described a kind of FinFET circuit and nano electromechanical beam integrated chip, it is characterized in that: described gate figure adopts a kind of formation in electron beam exposure, photoresist ashing, the normal optical lithography.
7. as the manufacture method of claim 2 or 3 or 4 or 5 described a kind of FinFET circuit and nano electromechanical beam integrated chip, it is characterized in that: described gate figure adopts the side wall technology to form, and concrete steps are as follows:
(1) adopts ion to inject polysilicon is carried out the grid doping;
(2) priority deposit layer of silicon dioxide and one deck polysilicon obtain polysilicon graphics after the photoetching,
(3) deposit layer of silicon dioxide, the described silicon dioxide of dry etching, thus form the sidewall structure that silicon dioxide constitutes;
(4) etch polysilicon stays sidewall structure;
(5) silicon dioxide layer below the dry etching exposes silicon face;
(6) photoetching with photoresist erodes unwanted sidewall structure;
(7) photoetching forms the mask pattern of grid, constitutes compound mask with described mask pattern and described sidewall structure, and polysilicon layer is carried out etching, forms gate figure.
8. as the manufacture method of claim 2 or 3 or 4 or 5 described a kind of FinFET circuit and nano electromechanical beam integrated chip, it is characterized in that: when whole silicon dioxide of corrosion parcel nano electromechanical beam, adopt a kind of in dry method, sublimed method or the wet method.
9. the manufacture method of a kind of FinFET circuit as claimed in claim 6 and nano electromechanical beam integrated chip is characterized in that: when whole silicon dioxide of corrosion parcel nano electromechanical beam, adopt a kind of in dry method, sublimed method or the wet method.
10. the manufacture method of a kind of FinlFET circuit as claimed in claim 7 and nano electromechanical beam integrated chip is characterized in that: when whole silicon dioxide of corrosion parcel nano electromechanical beam, be used in a kind of in method, sublimed method or the wet method.
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| CNB2005100050317A CN100364094C (en) | 2005-01-31 | 2005-01-31 | Chip integrated by FinFET circuit and nano electromechanical beam and preparing method |
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| CN100364094C true CN100364094C (en) | 2008-01-23 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040100306A1 (en) * | 2002-11-22 | 2004-05-27 | Zoran Krivokapic | Two transistor nor device |
| CN1507064A (en) * | 2002-12-13 | 2004-06-23 | 台湾积体电路制造股份有限公司 | Integrated transistor and its manufacture |
| CN1542930A (en) * | 2003-04-29 | 2004-11-03 | ̨������·����ɷ�����˾ | Semiconductor with fin structure and method for manufacturing same |
| WO2005004206A2 (en) * | 2003-07-01 | 2005-01-13 | International Business Machines Corporation | Integrated circuit having pairs of parallel complementary finfets |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040100306A1 (en) * | 2002-11-22 | 2004-05-27 | Zoran Krivokapic | Two transistor nor device |
| CN1507064A (en) * | 2002-12-13 | 2004-06-23 | 台湾积体电路制造股份有限公司 | Integrated transistor and its manufacture |
| CN1542930A (en) * | 2003-04-29 | 2004-11-03 | ̨������·����ɷ�����˾ | Semiconductor with fin structure and method for manufacturing same |
| WO2005004206A2 (en) * | 2003-07-01 | 2005-01-13 | International Business Machines Corporation | Integrated circuit having pairs of parallel complementary finfets |
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