JP2009526390A - CMOS device with hybrid channel orientation and method of manufacturing the same - Google Patents

Abstract

【Task】
To provide a semiconductor substrate having different surface orientation (ie, hybrid surface orientation) that provides optimal performance for a particular device.
[Solution]
The present invention relates to a semiconductor substrate comprising at least first and second element regions, the first element region comprising a first recess having an inner surface oriented along a first set of equivalent crystal planes, The second element region comprises a second recess having an inner surface oriented along a second different set of equivalent crystal planes. The semiconductor element structure can be formed using such a semiconductor substrate. Specifically, at least one n-channel field effect transistor (n-FET) can be formed in the first device region with a channel extending along the inner surface of the first recess. It is. At least one p-channel field effect transistor (p-FET) can be formed in the second device region with a channel extending along the inner surface of the second recess.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device that can be used in a complementary metal oxide semiconductor (CMOS) circuit. More specifically, the present invention relates to a CMOS circuit comprising at least one n-channel field effect transistor (n-FET) with a hybrid channel orientation and at least one p-channel field effect transistor (p-FET). In other words, the n-FET and p-FET of the CMOS circuit comprise channels that are oriented along different sets of crystal planes of the semiconductor substrate on which the CMOS circuit is disposed.

  In current semiconductor technology, CMOS devices such as n-FETs and p-FETs are typically oriented along one of a single set of equivalent crystal planes of the semiconductor material (eg, Si) that forms the substrate. Manufactured on semiconductor wafers each having a substrate surface. In particular, most current semiconductor devices are built on a silicon wafer having a wafer surface oriented along one of the {100} silicon crystal planes.

  Electrons are known to have high mobility along the {100} silicon crystal plane, while holes are known to have high mobility along the {110} silicon crystal plane. ing. Specifically, the hole mobility value along the {100} plane is approximately one-half to one-fourth of the corresponding electron mobility value along the plane. In contrast, the hole mobility value along the {110} silicon surface is about twice that along the {100} silicon surface, but the electron mobility along the {110} surface is , Significantly lower than that along the {100} plane.

  As can be inferred from the above contents, the {110} silicon surface is excellent in forming a p-FET element because of its excellent hole mobility along the {110} surface, and thus the p− The drive current in the FET increases. However, this aspect is completely unsuitable for forming n-FET devices. Instead, the {100} silicon surface is optimal for forming an n-FET device because of its high electron mobility along the {100} surface, resulting in a high drive current in the n-FET.

  In view of the above, there is a need to provide a semiconductor substrate having different surface orientation (ie, hybrid surface orientation) that provides optimal performance for a particular device.

  There is also a need to provide a method for forming an integrated semiconductor device formed on a substrate with a hybrid surface orientation, the integrated semiconductor device comprising at least an n-FET having a hybrid channel orientation. And the p-FET, ie, the n-FET channel is oriented along a first set of equivalent crystal planes that provide relatively high electron mobility, and the p-FET channel is relatively high hole transport Oriented along different sets of equivalent crystal planes providing degrees.

  The present invention provides a semiconductor substrate with hybrid surface orientation. The semiconductor substrate of the present invention is a bulk semiconductor structure or semiconductor on layered insulator that can be processed by an etching step to form recesses having internal surfaces oriented along different sets of crystal planes of semiconductor substrate material. (SOI) structure. Using such a semiconductor substrate, a CMOS circuit including n-FETs and p-FETs having different channel orientations can be easily formed.

  In one aspect, the invention is a semiconductor substrate comprising at least first and second device regions, the first device region having an inner surface oriented along a first set of equivalent crystal planes. A semiconductor substrate comprising a second recess having an inner surface oriented along a second different set of equivalent crystal planes, the second device region being disposed in the first device region A second element region, wherein the n-FET comprises a channel extending along the inner surface of the first recess, the n-FET being at least one n-channel field effect transistor (n-FET) At least one p-channel field effect transistor (p-FET), the p-FET comprising a channel extending along the internal surface of the second recess. ,semiconductor About the child.

  As used herein, the term “equivalent crystal plane” refers to an equivalent crystal plane or facet family defined by the Miller index, described in more detail below.

  In another aspect, the present invention provides a step of forming a semiconductor substrate comprising at least first and second element regions, a first recess in the first element region of the semiconductor substrate, and a second in the second element region. A first recess having an inner surface oriented along a first set of equivalent crystal planes, and a second recess in a second different set of equivalent crystal planes. Forming an internal surface oriented along, forming at least one n-FET in a first device region and at least one p-FET in a second device region, wherein n The FET comprises a channel extending along the inner surface of the first recess, and the p-FET comprises a channel extending along the inner surface of the second recess. To form an element A method for.

  In another aspect, the invention relates to a semiconductor substrate comprising at least first and second device regions, wherein the first device region has a first surface having an inner surface oriented along a first set of equivalent crystal planes. And the second device region comprises a second recess having an inner surface oriented along a second different set of equivalent crystal planes.

  In yet another aspect, the present invention provides a step of forming a semiconductor substrate comprising at least a first and a second element region, and a first recess in the first element region and a second element region in the semiconductor substrate. Forming two recesses, wherein the first recess has an interior surface oriented along a first set of equivalent crystal planes, and the second recess is a second different set of equivalent crystal planes. And having an internal surface oriented along.

  Other aspects, features, and advantages of the invention will become more fully apparent from the ensuing disclosure and appended claims.

  In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps, and techniques, in order to provide a thorough understanding of the present invention. However, one skilled in the art will understand that the invention may be practiced without these specific details. In other instances, well-known structures or process steps have not been described in detail in order not to obscure the present invention.

  When an element as a layer, region, or substrate is referred to as being “on” another element or “over” the other element, this is It may be directly above or there may be intervening elements. In contrast, when an element is referred to as being “directly over” another element or “directly over” another element, there are no intervening elements present. Also, if an element is referred to as being “beneath” of another element or “under” another element, this is considered to be directly under the other element. It will also be appreciated that there may be intervening elements that may be present. In contrast, when an element is referred to as being “directly under” another element or “directly covered” another element, there are no intervening elements present.

  This embodiment provides a hybrid semiconductor substrate that includes a plurality of recesses having internal surfaces oriented along different sets of crystal planes of semiconductor substrate material. More specifically, the first recess (or first set of recesses) is a first set of equivalent crystal planes that increases the mobility of certain types of charge carriers (ie, holes or electrons). Having an internal surface oriented along. A second recess (or second set of recesses) is an interior oriented along a second different set of equivalent crystal planes that increases the mobility of different types of charge carriers (ie, electrons or holes). Having a surface.

  The hybrid semiconductor substrate of the present invention includes, but is not limited to, Si, SiC, SiGe, SiGeC, Ge alloy, GaAs, InAs, InP, and other III-V or II-VI compound semiconductors. Any single crystal semiconductor material can be provided.

  In a single crystal semiconductor material, all lattice directions and lattice planes in a unit cell of the single crystal material can be expressed by a mathematical description called a Miller index. Specifically, the notation [hkl] in the Miller index defines the direction or orientation of the crystal. FIG. 1 shows a single crystal silicon unit cell, which is a cubic cell. Specific crystal directions such as [001], [100], [010], [110], and [111] are specifically indicated by arrows in the cubic unit cell. In contrast, the crystal plane or facet of a single crystal silicon unit cell is defined by the Miller index notation (hkl), which refers to a specific crystal plane or facet perpendicular to the [hkl] direction. FIG. 2 exemplarily shows the crystal planes (100), (110), and (11) of the single crystal silicon unit cell perpendicular to the [100], [110], and [111] directions, respectively.

  Furthermore, since the unit cell is periodic in the semiconductor crystal, there is a family or set of equivalent crystal directions and planes. Thus, the Miller index notation <hkl> defines a family or set of equivalent crystal directions or planes. For example, the <100> direction includes equivalent crystal directions of [100], [010] and [001], and the <110> direction includes [110], [011], [101], [-1-10], [-1-10], [-1-10], 0-1-1], [-10-1], [-110], [0-11], [-101], [1-10], [01-1], and [10-1] equivalents Including the crystal direction, the <111> direction includes equivalent crystal directions of [111], [−111], [1-11], and [11-1]. Similarly, the notation {hkl} defines a family or set of equivalent crystal faces or facets, each perpendicular to the <hkl> direction. For example, the {100} plane includes a set of equivalent crystal planes each perpendicular to the <100> direction.

  In a particularly preferred (but not essential) embodiment of the invention, the hybrid semiconductor substrate comprises single crystal silicon. Thus, the first recess or first recess set can have an interior surface oriented along the {100} silicon surface, while the second recess or second recess set is {110}. It is possible to have an internal surface oriented along the silicon surface. As described above, the hybrid semiconductor substrate of the present invention includes one or more n-FETs having channels oriented along the inner surface of the first recess or the first recess set, and the second recess or the second recess. It can be used in the manufacture of CMOS circuits with one or more p-FETs having channels oriented along the inner surface of the two recess sets.

  Alternatively, the first recess or first recess set can have an interior surface oriented along the {100} silicon surface, while the second recess or second recess set. Can have an internal surface oriented along the {111} silicon surface. Further, the first recess or first recess set can have an interior surface oriented along the {111} silicon surface, while the second recess or second recess set is { It is possible to have an internal surface oriented along the 110} silicon surface. Any other suitable plane orientation combination can also be provided in the recesses in the hybrid semiconductor substrate to achieve improved device performance.

  FIG. 3 specifically illustrates a cross-sectional view of a CMOS circuit fabricated on a semiconductor substrate 12 in accordance with one embodiment of the present invention. The semiconductor substrate 12 has at least one p-FET device region (left side) and at least one having a substrate surface oriented along one of the {110} planes and separated from each other by a trench isolation region 14. Two n-FET device regions (right side) are provided.

  The aforementioned semiconductor substrate 12 includes any, but not limited to, Si, SiC, SiGe, SiGeC, Ge alloy, GaAs, InAs, InP, and other III-V or II-VI compound semiconductors. It is possible to provide a single crystal semiconductor material. Preferably, such a hybrid semiconductor substrate is composed of a Si-containing semiconductor material, ie, a semiconductor material containing silicon. For example, the hybrid semiconductor substrate can consist essentially of bulk single crystal silicon. Alternatively, the hybrid semiconductor substrate can comprise an SOI structure that includes a thin film single crystal silicon layer disposed over a buried insulating layer that functions to reduce leakage current in the substrate. The hybrid semiconductor substrate can be doped or undoped, or can have doped and undoped regions therein. For example, the semiconductor substrate can also include a first doping (n or p) region and a second doping (p or n) region. The first doping region and the second doping region can be the same or have different conductivity and / or doping concentration. These doping regions are known as “wells” and can be used to define various device regions.

  For example, at least one isolation region such as trench isolation region 14 may be provided in the semiconductor substrate 12 to separate the p-FET device region and the n-FET device region. The isolation region can be a trench isolation region (shown) or a field oxide isolation region. The trench isolation region is formed using a conventional trench isolation process well known to those skilled in the art. For example, in forming a trench isolation region, trench lithography, etching, and filling using a trench dielectric can be used. Optionally, a liner can be formed in the trench prior to trench filling, a densification step can be performed after trench filling, and a planarization process can be performed following trench filling. The field oxide film can be formed using a so-called local oxidation process of silicon.

  A first recess defined by the inner surface 25 is disposed in the p-FET device region. The inner surface 25 of this first recess is oriented along the {110} crystal plane indicated by the arrow in the upper right corner of FIG. The p-FET element region of the semiconductor substrate 12 is disposed along the inner surface 25 of the first recess and the source and drains 22 and 24 disposed on both sides of the first recess, and between the source and drains 22 and 24. A p-FET device with a channel oriented in the vertical direction. The p-FET device further comprises a gate stack including a gate dielectric 26 formed over the inner surface 25 of the first recess and a gate electrode 28 disposed on top of the gate dielectric 26.

  A second recess defined by the inner surface 35 is disposed in the n-FET device region. The inner surface 35 of the second recess is oriented along a {100} crystal plane that is inclined at an angle of 45 ° with respect to the {110} crystal plane. The n-FET element region of the semiconductor substrate 12 extends along the inner surface 35 of the second recess disposed between the source and drain 32 and 34, and the source and drain 32 and 34 disposed on both sides of the second recess. A n-FET device with a channel oriented in a vertical direction. The n-FET device further comprises a gate stack including a gate dielectric 36 formed over the inner surface 35 of the second recess and a gate electrode 38 disposed on top of the gate dielectric 36.

  In this way, the channel of the p-FET device is oriented along the {110} plane with high hole mobility, while the channel of the n-FET device is along the {100} plane with high electron mobility. Oriented.

  Another important advantage of the present invention is that the channel length of both p-FET and n-FET devices is longer than their respective gate lengths. Specifically, the p-FET channel length is approximately equal to the sum of the gate length GL and twice the height h of the first recess (ie, λGL + 2h). Furthermore, the n-FET channel length is approximately equal to 2.8 times the gate length GL (ie, λ2 × √2GL).

  Due to the shrinking CMOS technology, it is very difficult to reduce the channel length in a conventional planar metal oxide semiconductor field effect transistor (MOSFET) due to the severe short channel effect in devices with channel lengths less than 30 nm. Have difficulty. However, reducing the MOSFET size is important to increase circuit density, reduce manufacturing costs, and improve device performance. The present invention can further reduce the MOSFET size (defined by the gate length) without reducing the channel length by proposing a MOSFET structure with a channel length longer than the gate length. .

  FIG. 4 shows a cross-sectional view of a CMOS circuit fabricated on a semiconductor substrate 42 according to another embodiment of the present invention that is similar to the embodiment shown in FIG. 3, but slightly different.

  The semiconductor substrate 42 has a substrate surface oriented along one of the {100} planes, instead of the {110} plane as shown in FIG. The substrate 42 comprises at least one n-FET device region (left side) and at least one p-FET device region (right side) separated from each other by a trench isolation region 44.

  A first recess defined by the inner surface 55 is disposed in the n-FET device region. The inner surface 55 of this first recess is oriented along the {100} crystal plane indicated by the arrow in the upper right corner of FIG. The n-FET element region of the semiconductor substrate 42 is disposed between the source and drain 52 and 54 disposed on both sides of the first recess, and between the source and drain 52 and 54 and along the inner surface 55 of the first recess. A n-FET device with a channel oriented in a vertical direction. The n-FET device further comprises a gate stack including a gate dielectric 56 formed over the inner surface 55 of the first recess and a gate electrode 58 disposed on top of the gate dielectric 56.

  A second recess defined by the inner surface 65 is disposed in the p-FET device region. The inner surface 65 of the second recess is oriented along a {110} crystal plane inclined at an angle of 45 ° with respect to the {100} crystal plane. The p-FET element region of the semiconductor substrate 42 extends along the inner surface 65 of the second recess disposed between the source and drain 62 and 64 and the source and drain 62 and 64 disposed on both sides of the second recess. A p-FET device with a channel oriented in the vertical direction. The p-FET device further comprises a gate stack including a gate dielectric 66 formed over the inner surface 65 of the second recess and a gate electrode 68 disposed on top of the gate dielectric 66.

  In this way, the channel of the n-FET device is oriented along the {100} plane with high electron mobility, while the channel of the p-FET device is along the {110} plane with high hole mobility. Oriented. Furthermore, the n-FET channel length is approximately equal to the sum of the gate length GL and twice the height h of the first recess (ie, λGL + 2h). Furthermore, the p-FET channel length is approximately equal to 2.8 times the gate length GL (ie, λ2 × √2GL).

  The embodiment shown in FIGS. 3 and 4 differs in the surface orientation of the semiconductor substrates 12 and 42. As shown in FIG. 3, when the substrate surface orientation is aligned to one of a set of equivalent crystal planes that provide relatively high hole mobility, the recess in the p-FET device region is While having an approximately rectangular cross-section with an internal surface oriented either parallel or perpendicular to the substrate surface, the recesses in the n-FET device region are at a specific angle with respect to the substrate surface. It will have a substantially triangular cross-section with a slanted internal surface. In contrast, if the substrate surface orientation is aligned to one of a set of equivalent crystal planes that provide relatively high electron mobility, as shown instead in FIG. The recess in the device region will have a substantially rectangular cross-section with the inner surface oriented either parallel or perpendicular to the substrate surface, while the recess in the p-FET device region is on the substrate surface. It will have a generally triangular cross-section with the inner surface inclined at a specific angle to it.

  3-4 exemplify exemplary CMOS device structures in accordance with certain embodiments of the present invention, those skilled in the art will recognize such device structures consistent with the above description. Note that it can be easily modified to meet the application requirements of For example, although the semiconductor substrate shown in FIGS. 3-4 represents a bulk semiconductor substrate, it should be understood that a semiconductor-on-insulator (SOI) substrate can also be used in the practice of this specification. Further, in FIGS. 3 to 4, the {110} and {100} crystal planes of single crystal silicon are mainly shown to define the channel orientation of the p-FET device and the n-FET device. Other suitable crystal planes such as {111}, {211}, {311}, {511}, and {711} planes of single crystal silicon are also optional to define the channel orientation of n-FET devices Can be used in any suitable combination. In addition, other single crystal semiconductor substrate materials with non-cubic unit cells such as single crystal gallium nitride with hexagonal unit cells also have different sets of crystal planes where these other single crystal semiconductor materials have different carrier mobility values. As long as it is included, it can be used to manufacture the CMOS device of the present invention. Those skilled in the art can readily modify the device structures shown in FIGS. 3 and 4 to be compatible with other substrate structures, crystal orientations, or semiconductor materials consistent with the spirit and principles of the present invention. Can do.

  The hybrid crystal orientation substrate of the present invention can be easily formed by a selective etching step.

  Specifically, first, it is possible to have a substrate surface oriented along one of a specific set of equivalent crystal planes (eg, {100}, {110}, or {111} planes). A semiconductor substrate is provided. Such semiconductor substrates as described above include, but are not limited to, Si, SiC, SiGe, SiGeC, Ge alloys, GaAs, InAs, InP, and other III-V or II-VI compound semiconductors. Any single crystal semiconductor material can be provided.

  Equivalent crystal planes that can be the same set of equivalent crystal planes in which the planes of the substrate surface are aligned (ie, the substrate surface) or different sets of equivalent crystal planes that are inclined at an angle with respect to the plane of the substrate surface A first selective region on the substrate surface is selectively etched to form a first recess having an interior surface oriented along the first set of the first set. If the first set of equivalent crystal planes needs to be the same set of equivalent crystal planes as the plane of the substrate surface, the first recess is along a direction perpendicular to the substrate surface (ie, the substrate It can be formed by an anisotropic etching process that etches the semiconductor substrate (straight relative to). Alternatively, if the first set of equivalent crystal planes need to be different from the plane of the substrate surface, the first recess etches the semiconductor substrate along all directions, crystallographic. ) Although it can be formed by an etching process, it is faster along the plane of the substrate surface than along the first set of equivalent crystal planes.

  Thereafter, a second selected region on the substrate surface is selectively etched to form a second recess having an inner surface oriented along a second different set of equivalent crystal planes. If the second different set of equivalent crystal planes is the same set of equivalent crystal planes as the plane of the substrate surface, the second recess is along a direction perpendicular to the substrate surface (ie, relative to the substrate It can be formed by a (straight) anisotropic etching process. Alternatively, if the second different set of equivalent crystal planes need to be different from the plane of the substrate surface, the second recess etches the semiconductor substrate along all directions, a crystallographic etch It can be formed by a process, but it is faster along the plane of the substrate surface than along a second different set of equivalent crystal planes.

  The anisotropic and crystallographic etching processes as described above can be performed by any suitable dry or wet etching technique or both techniques known in the art.

  Preferably, the anisotropic etching of the semiconductor substrate comprises one or more dry etching such as reactive ion etching, sputter etching, gas phase etching, ion beam etching, plasma etching, and laser ablation. It can be performed by an etching process, but is not limited thereto. The dry etch process is directional, but is nearly non-selective for different crystal planes or orientations, i.e., etches the semiconductor substrate at approximately equal rates along all directions. In certain preferred embodiments of the present invention, dry etching is performed using a reactive ion etching (RIE) process.

  The crystallographic etching of the semiconductor substrate is preferably one or more wet etching processes using an etchant, such as a hydroxide base etchant, an ethylene diamine pyrocatechol (EDP) based etchant, or the like. Implemented by the process. These wet etch processes typically etch a semiconductor substrate along all directions, but with crystallographic selectivity, ie, significantly different etch rates along different crystal planes or directions (herein Is called "crystallographic etching"). Thus, the etching pattern formed by the crystallographic etching process travels along the crystal plane that is etched at high speed and eventually terminates at the crystal plane that is etched at low speed.

  For example, an etchant comprising about 23.4% KOH, 13.3% isopropyl alcohol (IPA), and 63.3% water, along the {100} plane when heated to about 80 ° C. In this case, single crystal silicon is etched at an etching rate of about 1.0 im / min, but the etching rate is about 0.06 im / min along the {110} plane. In other words, this etchant etches the {100} plane at a rate approximately 17 times that of the {110} plane. Accordingly, the silicon substrate can be etched using such an etchant so as to form a recess that terminates in the {110} plane.

  In contrast, an etchant comprising about 44% KOH and 56% water, when heated to about 120 ° C., is about 11.7 im / min along the {110} plane and on the {100} plane. The single crystal silicon is etched at an etch rate of about 5.8 im / min along the {111} plane and about 0.02 im / min along the {111} plane. In other words, this etchant etches the {110} and {100} planes at a much faster rate (more than 550 and 250 times respectively) than the {111} plane. Therefore, the silicon substrate can be etched using such an etchant so as to form a recess that terminates in the {111} plane.

  Note that dry etching is typically used for anisotropic etching, but certain dry etching techniques such as RIE can also be used for crystallographic etching. In the case of RIE, a substrate is placed inside a reactor into which several gases are introduced. A plasma is introduced into the gas mixture using a radio frequency (RF) power source to decompose the gas molecules into ions. The ions are accelerated towards the surface of the material being etched and react with it to form other gaseous materials. This is known as the chemical part of reactive ion etching that is crystallographically possible, i.e. with crystallographic selectivity along different crystal planes or directions. RIE also has physical characteristics, and if the ions have sufficiently high energy, they can drive atoms out of the material being etched without chemical reaction. This physical etching feature of RIE has a high degree of anisotropy, but no crystallographic selectivity. Thus, RIE is a complex process that involves both chemical and physical etching. By carefully adjusting the RIE chemistry, and the balance between chemical and physical characteristics, this process can be used to achieve either anisotropic or crystallographic etching results. . Similarly, although wet etching is typically used for crystallographic etching, certain wet etching chemistries can also be used to achieve anisotropic etching results.

  Thus, the present invention is not limited to using dry etching for anisotropic etching processes and using wet etching for crystallographic etching processes, although the desired differences as described above. Includes all suitable etching processes and techniques that can be used to achieve isotropic and crystallographic results.

  After forming the first and second recesses in the semiconductor substrate, additional CMOS processing steps can be performed to form n-FETs and p-FETs in the first and second device regions. The n-FET and p-FET are each oriented along an equivalent crystal plane in which the n-FET and p-FET channels improve the mobility of their respective carriers in the n-FET and p-FET channels, respectively. Arranged and constructed to extend along the inner surfaces of the first and second recesses.

  5-17 illustrate exemplary processing steps used to form a COMS circuit that includes p-FETs and n-FETs with hybrid channel orientation, according to one embodiment of the present invention.

  Reference is first made to FIG. 5, which shows a semiconductor substrate 102 having a substrate surface aligned with one of the {110} silicon crystal planes. The semiconductor substrate comprises a p-FET element region (left side) and an n-FET element region (right side) separated from each other by a trench isolation region 104.

  A gate dielectric layer 106 is formed over the substrate 102. The gate dielectric layer 106 can be formed by a thermal growth process such as oxidation, nitridation, oxynitridation, and the like. Alternatively, the gate dielectric layer 106 may be formed using, for example, chemical vapor deposition (CVD), plasma assisted CVD, atomic layer deposition (ALD), vapor deposition, reactive sputtering, chemical solution deposition, and other deposition processes, such as It can be formed by a deposition process. The gate dielectric layer 106 can also be formed using any combination of the above processes.

The gate dielectric layer 106 is comprised of an insulating material including, but not limited to, oxides, nitrides, oxynitrides, or silicates including metal silicates and metal nitrides. It will never be done. In one embodiment, gate dielectric layer 106, for example such as _{SiO 2, HfO 2, ZrO 2} , Al 2 O 3, TiO 2, La 2 O 3, SrTiO 3, LaAlO 3, and mixtures thereof, oxides Preferably it consists of.

  Although the physical thickness of the gate dielectric layer 106 can vary, typically the gate dielectric layer 106 has a thickness of about 0.5 nm to about 10 nm, and a thickness of about 1 nm to about 5 nm. More typical.

  After forming the gate dielectric layer 106, a blanket dielectric hard mask layer 108 is deposited over the gate dielectric layer 106, as shown in FIG. One is patterned to form at least two etch openings in the p-FET device region. The dielectric hard mask layer 108 can comprise an oxide, nitride, oxynitride, or any combination thereof and uses a deposition process such as physical vapor deposition or chemical vapor deposition, for example. And can be deposited. Preferably, the dielectric hard mask layer 108 comprises nitride and has a thickness in the range of about 50 nm to about 150 nm, more preferably about 80 nm to about 120 nm, but is not limited thereto.

  The blanket dielectric hard mask layer 108 can be patterned by lithography and etching. The lithography step preferably defines a gate level, applies a photoresist (not shown) to the top surface of the blanket dielectric hard mask layer 108, and exposes the photoresist to a desired radiation pattern. Developing the exposed photoresist using a conventional resist developer. Next, the pattern in the photoresist is transferred to the dielectric mask layer 108 using one or more dry etching steps to form an etching opening. Suitable dry etching processes that can be used to pattern the dielectric hard mask layer 108 of the present invention include reactive ion etching (RIE), ion beam etching, plasma etching, or laser ablation. Including, but not limited to. Preferably, the etching is performed by a nitride RIE step that terminates on the gate dielectric layer 106. The patterned photoresist is then removed by resist stripping after etching is complete.

  Next, a block mask (not shown) is selectively formed covering the n-FET device region but not the p-FET device region, and then in the p-FET device region as shown in FIG. The gate dielectric layer 106 is selectively etched. Selective etching of the gate dielectric layer 106 is an optional etch that selectively etches the gate dielectric material in the layer 106 relative to the semiconductor material in the underlying substrate 102 and the masking material in the dielectric hard mask layer 108. Can be implemented by any suitable etching process. Preferably, if the gate dielectric layer 106 comprises an oxide and the dielectric hard mask layer 108 comprises a nitride and a hydrofluoric acid base etchant is used, the etchant may be silicon or the like. It etches oxides much faster than semiconductor materials and does not etch nitrides at all.

  Thereafter, an anisotropic etching step (described above) is performed for selective etching of the p-FET device region, thereby forming the p-FET device region in the semiconductor substrate 102 as shown in FIG. A recess 110 is formed. The recess 110 thus formed includes an inner surface 111 having a substantially rectangular cross section and substantially aligned with the {110} crystal plane. Preferably, the anisotropic etching step includes, but is not limited to, anisotropic RIE using a previously formed n-FET block mask for selective etching of the p-FET device region.

  Following the anisotropic etching, a sacrificial oxide layer 112 covering the inner surface of the recess 110 is formed by an oxidation process, as shown in FIG. The oxidation process can be either a thermal oxidation process or a chemical oxidation process.

  After the sacrificial oxide layer 112 is formed, the n-FET block mask is removed from the substrate surface. Thereafter, as shown in FIG. 10, another block mask (not shown) is selectively formed over the p-FET device region but not the n-FET device region, followed by the n-FET. The gate dielectric layer 106 is selectively etched in the device region. After selective etching of the gate dielectric layer 106, the p-FET block mask is removed.

  Next, a crystallographic etching step (described above) is performed for selective etching of the n-FET device region, thereby forming an n-FET device region in the semiconductor substrate 102 as shown in FIG. A recess 114 is formed on the surface. Preferably, the crystallographic etching step is performed using a wet etch process using a hydroxide base etchant that etches the {110} face much faster than the {100} face, In the meantime, a mask is used in order to prevent etching of the p-FET device region. Alternatively, if the crystallographic etch step is performed using a crystallographic RIE process, the aforementioned p-FET block mask is retained after selective etching of the gate dielectric layer 106. As such, it can be used as a mask during the crystallographic RIE process. Therefore, the recess 114 formed in this way has a substantially triangular cross-section and is substantially aligned with the {100} crystal plane, but is inclined at an angle of 45 ° with respect to the {110} plane. A surface 115 is included.

  Following the crystallographic etch, the sacrificial oxide layer 112 is removed from the p-FET device region, preferably by an oxide etch process, so that the inner surfaces of both recesses 110 and 114 are shown in FIG. 111 and 115 are exposed. The inner surface 111 of the recess 110 is oriented along the {110} plane, and the inner surface 115 of the recess 114 is oriented along the {100} plane. FIG. 13 shows a top view of the semiconductor substrate 102 of FIG. 12 and includes two recesses 110 and 114 with different internal surface orientations.

  Thereafter, as shown in FIG. 14, additional gate dielectric layers 116 and 118 are formed over recesses 110 and 114 using processes similar to those described above to form gate dielectric layer 106. Is formed. A blank gate conductor layer 120 is then deposited over the entire structure, as shown in FIG. The gate conductor layer 120 can comprise any suitable conductive material, such as metals, metal alloys, metal silicides, metal nitrides, and doped silicon-containing semiconductor materials (polysilicon, SiGe, etc.) It can have a layer thickness in the range of about 50 nm to about 150 nm, more typically about 80 nm to about 120 nm. Thereafter, the gate conductor layer 120 is planarized (eg, by a chemical mechanical polishing process) to form two gate conductors 120A and 120B, and the top surfaces of the gate conductors 120A and 120B are shown in FIG. Thus, it is flush with the top surface of the dielectric hard mask layer 108. Thereafter, the dielectric hard mask layer 108 is moved to form exposed gate conductors 120A and 120B, as shown in FIG.

  Therefore, the structure shown in FIG. 17 covers the p-FET gate dielectric layer 116 and the p-FET gate conductor 120A formed covering the recess in the p-FET device region, and the recess in the n-FET device region. N-FET gate dielectric layer 118 and n-FET gate conductor 120B. The p-FET gate dielectric layer 116 demarcates the p-FET channel extending along the inner surface of the recess in the p-FET device region, and the n-FET gate dielectric layer 118 is the n-FET. Delimits the n-FET channel extending along the inner surface of the recess in the device region.

  Subsequently, conventional CMOS processing steps not described in detail herein are performed to provide a p-FET in the p-FET device region and an n-FET in the n-FET device region similar to those shown in FIG. A complete CMOS circuit including can be formed.

  It should be noted that the drawings of the present invention are provided for illustrative purposes and are not drawn to scale.

  Although the present invention has been described above with reference to specific embodiments, features, and aspects, the present invention is not limited in this manner, but rather has utility in other modifications, variations, applications, It is to be understood that such other modifications, variations, coverages, and embodiments are considered to be within the spirit and scope of the present invention, and to the extent that it is extended to.

It is a figure which shows the silicon crystal unit cell (unit cell) with the certain crystal orientation specifically shown by the arrow. It is a figure which shows a certain specific crystal plane in a silicon crystal unit cell. 1 is a cross-sectional view illustrating a CMOS circuit fabricated on a semiconductor substrate having a substrate surface oriented along one of the {110} silicon surfaces, according to one embodiment of the invention, Including at least one p-FET having its channel oriented along a {110} silicon surface and at least one n-FET having its channel oriented along a {100} silicon surface. 1 is a cross-sectional view illustrating a CMOS circuit fabricated on a semiconductor substrate having a substrate surface oriented along one of the {100} silicon planes, according to one embodiment of the invention, Including at least one n-FET having its channel oriented along a {100} silicon surface and at least one p-FET having its channel oriented along a {110} silicon surface. FIG. 4 illustrates exemplary processing steps used to fabricate a COMS circuit including p-FETs and n-FETs with hybrid channel orientation, in accordance with one embodiment of the present invention. FIG. 4 illustrates exemplary processing steps used to fabricate a COMS circuit including p-FETs and n-FETs with hybrid channel orientation, in accordance with one embodiment of the present invention. FIG. 4 illustrates exemplary processing steps used to fabricate a COMS circuit including p-FETs and n-FETs with hybrid channel orientation, in accordance with one embodiment of the present invention. FIG. 4 illustrates exemplary processing steps used to fabricate a COMS circuit including p-FETs and n-FETs with hybrid channel orientation, in accordance with one embodiment of the present invention. FIG. 4 illustrates exemplary processing steps used to fabricate a COMS circuit including p-FETs and n-FETs with hybrid channel orientation, in accordance with one embodiment of the present invention. FIG. 4 illustrates exemplary processing steps used to fabricate a COMS circuit including p-FETs and n-FETs with hybrid channel orientation, in accordance with one embodiment of the present invention. FIG. 4 illustrates exemplary processing steps used to fabricate a COMS circuit including p-FETs and n-FETs with hybrid channel orientation, in accordance with one embodiment of the present invention. FIG. 4 illustrates exemplary processing steps used to fabricate a COMS circuit including p-FETs and n-FETs with hybrid channel orientation, in accordance with one embodiment of the present invention. FIG. 4 illustrates exemplary processing steps used to fabricate a COMS circuit including p-FETs and n-FETs with hybrid channel orientation, in accordance with one embodiment of the present invention. FIG. 4 illustrates exemplary processing steps used to fabricate a COMS circuit including p-FETs and n-FETs with hybrid channel orientation, in accordance with one embodiment of the present invention. FIG. 4 illustrates exemplary processing steps used to fabricate a COMS circuit including p-FETs and n-FETs with hybrid channel orientation, in accordance with one embodiment of the present invention. FIG. 4 illustrates exemplary processing steps used to fabricate a COMS circuit including p-FETs and n-FETs with hybrid channel orientation, in accordance with one embodiment of the present invention. FIG. 4 illustrates exemplary processing steps used to fabricate a COMS circuit including p-FETs and n-FETs with hybrid channel orientation, in accordance with one embodiment of the present invention.

Claims (13)

A semiconductor substrate comprising at least a first and a second element region, wherein the first element region comprises a first recess having an inner surface oriented along a first set of equivalent crystal planes; A second substrate region comprising a second recess having an inner surface oriented along a second different set of equivalent crystal planes;
At least one n-channel field effect transistor (n-FET) disposed in the first device region, the n-FET comprising a channel extending along the inner surface of the first recess; , N-FET,
At least one p-channel field effect transistor (p-FET) disposed in the second device region, the p-FET comprising a channel extending along the inner surface of the second recess; , P-FET,
A semiconductor device comprising:   The semiconductor substrate is oriented along one of the first set of equivalent crystal planes, or oriented along one of the second set of equivalent crystal planes The semiconductor device according to claim 1, comprising: The semiconductor substrate comprises single crystal silicon,
(A) the first set of equivalent crystal faces is a {100} silicon face and the second different set of equivalent crystal faces is a {110} silicon face;
(B) the first set of equivalent crystal planes is a {100} silicon plane and the second different set of equivalent crystal planes is a {111} silicon plane; or (c) the semiconductor substrate is a single Comprising crystalline silicon, the first set of equivalent crystal faces being {111} silicon faces, and the second different set of equivalent crystal faces being {110} silicon faces;
The semiconductor device according to claim 1, which is any one of the following.   The n-FET further comprises a source region and a drain region disposed on both sides of the channel, and a gate stack disposed over the channel, and the n-FET has a channel longer than its gate length. The p-FET further comprises source and drain regions disposed on opposite sides of the channel, and a gate stack disposed over the channel, the p-FET comprising: The semiconductor device according to claim 1, 2 or 3 having a channel length longer than the gate length. Forming a semiconductor substrate comprising at least first and second element regions;
Forming a first recess in the first element region and a second recess in the second element region of the semiconductor substrate, wherein the first recess is a first set of equivalent crystal planes. Forming an internal surface oriented along, and wherein the second recess has internal surfaces oriented along a second different set of equivalent crystal planes;
Forming at least one n-FET in the first element region and at least one p-FET in the second element region, wherein the n-FET is in the interior of the first recess. Forming a channel extending along a surface, the p-FET comprising a channel extending along the internal surface of the second recess;
A method for forming a semiconductor device comprising:   The semiconductor substrate has a substrate surface oriented along one of the first set of equivalent crystal planes, and the first recess is along the direction perpendicular to the substrate surface. A first set of equivalent crystal planes, wherein the second recess is formed by a crystallographic etch that etches the semiconductor substrate along all directions. 6. The method of claim 5, wherein along is faster than along a second different set of equivalent crystal planes.   The semiconductor substrate has a substrate surface oriented along one of the second different set of equivalent crystal planes, and the first recess etches the semiconductor substrate along all directions. Formed by crystallographic etching, but along the second different set of equivalent crystal planes is faster than along the first set of equivalent crystal planes, and the second recess is the substrate 6. The method of claim 5, formed by an anisotropic etching process that etches the semiconductor substrate along a direction perpendicular to the surface.   The semiconductor substrate comprises single crystal silicon, the first set of equivalent crystal planes is a {100} silicon plane, and the second different set of equivalent crystal planes is a {110} silicon plane. Or the method according to 7.   The method according to claim 6 or 7, wherein the anisotropic etching process is a dry etching process and the crystallographic etching process is a wet etching process.   8. The method of claim 6 or 7, wherein the dry etching process is performed using reactive ions and the wet etching process is performed using a hydroxide base etchant.   The n-FET further comprises a source region and a drain region disposed on both sides of the channel, and a gate stack disposed over the channel, and the n-FET has a channel longer than its gate length. The p-FET further comprises source and drain regions disposed on opposite sides of the channel, and a gate stack disposed over the channel, the p-FET comprising: 6. The method of claim 5, having a channel length that is longer than the gate length.   A semiconductor substrate comprising at least a first and a second element region, wherein the first element region comprises a first recess having an inner surface oriented along a first set of equivalent crystal planes; A semiconductor substrate, wherein the second device region comprises a second recess having an inner surface oriented along a second different set of equivalent crystal planes. Forming a semiconductor substrate comprising at least first and second element regions;
Forming a first recess in the first element region and a second recess in the second element region of the semiconductor substrate, wherein the first recess is a first set of equivalent crystal planes. Forming an internal surface oriented along the second recess, the internal surface oriented along a second different set of equivalent crystal planes; and
Including methods.

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