CN109573941B - Large-scale manufacturing method of CMOS-MEMS integrated chip - Google Patents

Abstract

The present disclosure provides a method for manufacturing a CMOS-MEMS integrated chip in a large scale, which organically integrates a CMOS process and a MEMS bulk silicon manufacturing process, including: step A: selecting an SOI substrate and dividing a CMOS circuit area and an MEMS resonant cantilever beam sensor area on the SOI substrate; the SOI substrate comprises top silicon (1), a buried oxide layer (2) and bulk silicon (3); and B: c, manufacturing a CMOS circuit and an MEMS resonant cantilever beam sensor circuit on the top silicon (1) of the SOI substrate selected in the step A by adopting a CMOS process; and C: the gold electrode and the MEMS resonant cantilever beam are prepared to complete the preparation of the CMOS-MEMS integrated chip, and the Inter-CMOS and Post-CMOS processes are fused, so that the parasitic capacitance of the device is reduced, the signal noise is reduced, and the stability and the yield of the device are greatly improved.

Description

Large-scale manufacturing method of CMOS-MEMS integrated chip

Technical Field

The disclosure relates to the field of semiconductor chips and manufacturing, in particular to a large-scale manufacturing method of a CMOS-MEMS integrated chip.

Background

MEMS is an abbreviation for Micro Electro Mechanical Systems, i.e., microelectromechanical Systems. The micro-electronic processing system is developed on the basis of a micro-electronic manufacturing technology, integrates various micro-processing technologies, and can realize acquisition, processing, control and execution of various information quantities (force, heat, electromagnetism, light, chemistry and the like). The MEMS processing technology mainly adopts a monocrystalline silicon substrate and a polycrystalline silicon film, and combines the photoetching technology to manufacture fine two-dimensional and three-dimensional micro mechanisms such as cantilever beams, films, channels with high depth-to-width ratios, cavities in inverted pyramid shapes and the like. Since the last 80 century, the MEMS technology has been developed rapidly due to the advantages of miniaturization, multifunction, low cost, etc. [ 1 ], and sensing devices such as optical MEMS, biological MEMS, micro-fluidic, RF MEMS, etc. have been developed in large quantities.

The cantilever beam biochemical sensor takes a cantilever beam as a structural unit, is manufactured on an SOI substrate by adopting a micro-nano processing technology, namely, a cantilever beam structure is manufactured on the SOI substrate by photoetching and dry etching technologies, and an electrical sensing element is manufactured by ion implantation and electron beam evaporation technologies. With the continuous expansion of the application range of micro-sensing, the requirements on future micro-sensors are higher and higher: miniaturization and integration; low power consumption and low cost; high precision and long service life; multi-functional and intelligent. The integration of silicon-based micromachining techniques with integrated circuit processing techniques can meet the above requirements. The integration method of the MEMS sensor and the CMOS integrated circuit is to manufacture the MEMS sensor and the CMOS integrated circuit separately, and then fix them on a common substrate, and wire bonding, but since the signal passes through the bonding point and the lead, the signal transmission quality is degraded in high frequency application, and the cost is high. In recent years, researchers have begun to monolithically integrate MEMS and CMOS, which has advantages including small parasitic capacitance, small chip size, low cost, small packaging difficulty, reliability, portability, etc. [ 2 ].

Currently, the monolithic integration MEMS technology includes Pre-CMOS (Pre-CMOS), hybrid CMOS (Inter-CMOS) and Post-CMOS (Post-CMOS) [ 3 ] [ 4 ] integration methods, the Pre-CMOS integration method has the problem of step coverage of interconnection between a sensor and a circuit, and the use of Inter-CMOS process is limited by process standards, in contrast, Post-CMOS is the most widely used scheme for CMOS-MEMS monolithic integration. In the Post-CMOS scheme, the influence of the high-temperature MEMS microstructure processing temperature on the processed CMOS circuit is the key point for solving the monolithic integrated MEMS system.

Reference to the literature

【1】R.T.Howe，R.S.Muller，K.J.Gabriel and W.S.N.Trimmer，Silicon micro-mechanics：sensor and actuators on a chip，IEEE Spectrum，7，29-35，1990.

【2】Maria Villarroya，Jaume Verd a，Jordi Teva，System on chip mass sensor based on polysilicon cantileversarrays for multiple detection，Sensors and Actuators A132154-164，2006.

【3】Nikiaus F，Haasi S，Stemme G.Arrays of monocrystaiiine siiicon micromirrorsFabricated using CMOS compatibie transfer bonding[J].Microeiectromechanicai Systems，2003，12(4)：465-469.

【4】Lange D，Hagieitner C，Hieriemann A，Compiementary metaioxide semiconductor cantiiever array on a singie chip：Mass-sensitivedetection of voiatiie organic compounds[J].Anai Chem，2002，74：3084-3095。

Disclosure of Invention

Technical problem to be solved

Based on the above problems, the present disclosure provides a method for manufacturing a CMOS-MEMS integrated chip on a large scale, so as to alleviate technical problems such as incompatibility between the MEMS process and the CMOS process in the prior art.

(II) technical scheme

The present disclosure provides a method for manufacturing a CMOS-MEMS integrated chip in a large scale, which organically integrates a CMOS process and a MEMS bulk silicon manufacturing process, including: step A: selecting an SOI substrate and dividing a CMOS circuit area and an MEMS resonant cantilever beam sensor area on the SOI substrate; the SOI substrate comprises top silicon 1, a buried oxide layer 2 and bulk silicon 3; and B: b, manufacturing a CMOS circuit and an MEMS resonant cantilever beam sensor circuit on the top silicon 1 of the SOI substrate selected in the step A by adopting a CMOS process; and C: and preparing an electrode and an MEMS resonant cantilever beam to complete the preparation of the CMOS-MEMS integrated chip.

In this disclosure, the SOI substrate selected in step a is a P-type top silicon SOI substrate or an N-type top silicon SOI substrate.

In an embodiment of the present disclosure, the top layer silicon 1 in the step a includes: p-type silicon of 100 crystal plane or N-type silicon of 100 crystal plane.

In an embodiment of the present disclosure, the step B includes: step B1: preparing an N trap 4 and field oxide 5 on the top layer silicon 1; step B2: preparing gate oxide 6 on the surface of the device after the step B1 is finished, and preparing a polysilicon gate 7 on the surface of the gate oxide 6 prepared in the CMOS circuit area; step B4: preparing a dielectric layer 10 and an Al transmission line 11 on the surface of the SOI substrate after the step B3 is finished; step B3: ion implantation is carried out in the CMOS circuit area and the MEMS resonant cantilever beam sensor area to form P + (8), and ion implantation is carried out in the CMOS circuit area to form N + (9); step B5: preparing a passivation layer 12 on the surface of the SOI substrate after the step B4 is completed, and opening an electrical leading-out hole Pad; and step B6: and etching a part of the MEMS resonant cantilever beam region to the top layer silicon 1 to form a channel region.

In this embodiment of the present disclosure, in step B3, the SOI substrate after the step B2 is processed by a CMOS process to complete the implantation of boron ions and phosphorus ions in the CMOS circuit region, and complete the implantation of boron ions in the MEMS resonant cantilever sensor region, so as to form the piezoresistance.

In the embodiment of the present disclosure, in the step B3, when the ion implantation forms P + (8), the ion implantation is performed along the 110 crystal orientation of the top layer silicon 1; when ion implantation forms N + (9), implantation is performed along the 100 crystal orientation of the top silicon 1.

In an embodiment of the present disclosure, the step C includes: step C1: preparing an electrode in the electrical lead-out hole Pad prepared in the step B5; step C2: etching the top silicon 1 in the channel region formed in the step B6 to manufacture an MEMS resonant cantilever beam pattern; step C3: and preparing the MEMS resonant cantilever beam to complete the preparation of the CMOS-MEMS integrated chip.

In an embodiment of the present disclosure, the electrode material prepared in step C1 includes: cr, Pt, Au, Ti, or a combination thereof.

In the embodiment of the present disclosure, in the step C2, the top layer silicon 1 is etched by a dry etching process to produce the MEMS resonant cantilever pattern, and the etching stop layer is the buried oxide layer 2.

In the embodiment of the present disclosure, in the step C3, a plasma enhanced chemical vapor deposition method is used to deposit silicon dioxide thin films 13 on the front and back sides of the SOI substrate after the step C2, and a mask pattern is made by using a double-sided alignment lithography; photoetching and patterning the silicon dioxide film 13 on the front surface of the SOI substrate, and performing mask compensation on the cantilever beam by using the silicon dioxide film 13 on the front surface; etching bulk silicon on the back of the SOI substrate by adopting a deep reactive ion etching process until the thickness of the residual bulk silicon is 100-200 microns, then growing a layer of metal Al film 14 on the back of the wafer, and isotropically etching the residual bulk silicon from the front; and removing the buried oxide layer 2 and the metal Al film 14 of the exposed SOI substrate in the channel region by adopting a wet etching method, and releasing the MEMS resonant cantilever structure.

(III) advantageous effects

According to the technical scheme, the scale manufacturing method of the CMOS-MEMS integrated chip disclosed by the invention has at least one or part of the following beneficial effects:

(1) the MEMS cantilever beam structure is prepared by organically integrating a CMOS process and an MEMS bulk silicon manufacturing process by adopting an Inter-CMOS and Post-CMOS process, and completing the MEMS electrical structure in the Inter-CMOS process, so that the influence of a high-temperature process in the conventional MEMS electrical structure manufacturing on a CMOS circuit is avoided, a passivation layer is protected on a silicon wafer after the CMOS process is completed, and then the MEMS bulk silicon process is carried out to obtain the MEMS cantilever beam structure. The two processes are fused, so that the parasitic capacitance of the device is reduced, the signal noise is reduced, and the stability and the yield of the device are greatly improved;

(2) the MEMS sensor can be reduced in size and packaging pressure, the occupied area is reduced by nearly 90% compared with similar MEMS devices and circuit modules, and the MEMS sensor is very suitable for portable detection, especially a wearable system and can be widely applied to the fields of biological medical treatment, food safety, chemical engineering, aerospace national defense and the like;

(3) the conventional CMOS process and the MEMS body process are adopted to be popularized and applied to the integrated manufacturing of other silicon-based MEMS devices and CMOS, and the mass on-line chip-loading process of CMOS is utilized to achieve the large-scale manufacturing. The method provides a widely applicable integrated micro-system solution for the portable application of the MEMS sensor, and provides an effective technical means for multi-source information acquisition in a complex environment.

Drawings

Fig. 1 is a flow chart exploded view of a method for manufacturing a CMOS-MEMS integrated chip on a large scale according to an embodiment of the present disclosure.

Fig. 2 is a graph of resistivity distribution for p-type and n-type 100-plane silicon in accordance with an embodiment of the present disclosure.

FIG. 3 is a schematic cross-sectional view of a mass-fabricated CMOS-MEMS integrated chip according to an embodiment of the present disclosure.

Fig. 4 is a flow chart of a method for manufacturing a CMOS-MEMS integrated chip in a large scale according to an embodiment of the present disclosure.

[ description of main reference numerals in the drawings ] of the embodiments of the present disclosure

1-top layer silicon; 2-buried oxide layer; 3-bulk silicon; 4-N trap; 5-field oxygen; 6-gate oxide;

7-polysilicon gate; 8-P +; 9-N +; 10-a dielectric layer; 11-Al transmission lines;

12-a passivation layer; 13-a silicon dioxide film; 14-Al thin film.

Detailed Description

The invention provides a large-scale manufacturing method of a CMOS-MEMS integrated chip, which adopts a CMOS process N well/P well injection link to manufacture an N well/P well in an MEMS region and inject P +/N + into the N well/P well to manufacture a piezoresistive part of the MEMS region, thereby solving the contradiction that the CMOS process tends to adopt a P-type substrate and the MEMS resonant cantilever beam manufacturing process tends to adopt an N-type substrate. The method adopts the Inter-CMOS and Post-CMOS processes, organically fuses the CMOS process and the MEMS bulk silicon manufacturing process, completes the manufacture of the MEMS electrical structure in the CMOS process, protects the passivation layer of a silicon wafer after the CMOS process is completed, completes the manufacture of the MEMS resonant cantilever beam through the MEMS bulk silicon process, avoids the influence of a high-temperature process in the conventional manufacture of the MEMS electrical structure on the CMOS circuit, is compatible with the MEMS process and the CMOS process, improves the radiation resistance of the CMOS circuit, inhibits the latch-up effect, reduces the parasitic capacitance of a device, reduces the signal noise, improves the stability and the yield of the device, is a CMOS-MEMS integrated chip manufacturing method with high process compatibility, and is convenient for large-scale manufacture.

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

In an embodiment of the present disclosure, a method for manufacturing a CMOS-MEMS integrated chip in a large scale is provided, where fig. 1 is a flow exploded view of the method for manufacturing a CMOS-MEMS integrated chip in a large scale, fig. 3 is a schematic cross-sectional view of a CMOS-MEMS integrated chip prepared in a large scale, fig. 4 is a flow block diagram of the method for manufacturing a CMOS-MEMS integrated chip in a large scale, and the method for manufacturing a CMOS-MEMS integrated chip in a large scale includes, with reference to fig. 1, fig. 3, and fig. 4:

step A: selecting an SOI substrate and dividing a CMOS circuit area and an MEMS resonant cantilever beam sensor area on the SOI substrate;

the SOI substrate includes:

top layer silicon 1;

the buried oxide layer 2 is positioned below the top silicon layer 1; and

and bulk silicon 3 is positioned below the buried oxide layer 2.

The top layer silicon 1 is P-type silicon or N-type silicon and is a 100 crystal face;

in the embodiment of the present disclosure, an SOI substrate is selected as a substrate material for preparing a CMOS-MEMS integrated cantilever sensor, the top layer silicon 1 of the SOI substrate is a 100-plane P-type silicon, and a CMOS circuit region and an MEMS resonant cantilever sensor region are divided on the same SOI substrate according to a pre-design, as shown in fig. 1 a. As shown, the left side of the dotted line is a CMOS circuit area, and the right side is an MEMS resonant cantilever beam sensor area.

And B: b, manufacturing a CMOS circuit and an MEMS resonant cantilever beam sensor circuit on the top silicon 1 of the SOI substrate selected in the step A by adopting a CMOS process; the method comprises the following steps:

step B1: preparing an N trap 4 and field oxide 5 on the top layer silicon 1;

carrying out thermal oxidation on the SOI substrate at 1000 ℃, forming silicon dioxide on the surface of the top silicon 1 to be used as a mask for ion implantation and protect the top silicon 1, and implanting P ions into the top silicon 1 through patterning of a photoresist to form an N well 4; depositing silicon nitride by LPCVD (Low Pressure Chemical Vapor deposition) and patterning, protecting the part of the MEMS resonant cantilever sensor area needing piezoresistance and the device position of the CMOS circuit area, and growing field oxygen 5 on the unprotected area of the silicon nitride, as shown in FIG. 1 b;

step B2: preparing gate oxide 6 on the surface of the device after the step B1 is finished, and preparing a polysilicon gate 7 on the surface of the gate oxide 6 prepared in the CMOS circuit area;

growing gate oxide 6 on the surface of the SOI substrate prepared in the step B1 by adopting a PECVD process, depositing and patterning by adopting an LPCVD process, and preparing a polysilicon gate 7 on the surface of the gate oxide 6 grown in the CMOS circuit region, as shown in figure 1 c;

step B3: ion implantation is carried out in the CMOS circuit area and the MEMS resonant cantilever beam sensor area to form P + (8), and ion implantation is carried out in the CMOS circuit area to form N + (9);

b2, implanting boron ions and phosphorus ions into the SOI substrate, and completing the ion implantation of a CMOS circuit region and an MEMS resonant cantilever beam sensor region by utilizing a P +/N + impurity implantation process in the CMOS process to form a piezoresistor; in the MEMS area, a P + type piezoresistance is formed; the boundary of the P +8/N +9 area is aligned with the graphic boundary of the polysilicon gate 7, and the position of the piezoresistance is positioned at the root of the MEMS resonant cantilever beam. As shown in FIG. 1 d;

step B4: preparing a dielectric layer 10 and an Al transmission line 11 on the surface of the SOI substrate after the step B3 is finished;

the surface of the SOI substrate is grown and deposited with phosphorosilicate glass by adopting a PECVD process to form a dielectric layer 10, and the contact hole is patterned by utilizing photoetching and etching processes. And filling the contact holes by a physical vapor deposition metal Al process to finish the manufacture of the contact holes, forming metal wiring on the metal Al film by photoetching, etching or stripping and patterning to manufacture an Al transmission line 11, and further finishing the electrical connection among the MEMS resonant cantilever beam sensor area circuits, the CMOS circuits and the MEMS resonant cantilever beam sensor area circuits and the CMOS circuit area. Step B4 may be repeated as needed for the device design. As shown in FIG. 1 e;

step B5: preparing a passivation layer 12 on the surface of the SOI substrate after the step B4 is completed, and opening an electrical leading-out hole Pad;

depositing silicon nitride on the surface of the device obtained in the step B4 by using an LPCVD (low pressure chemical vapor deposition) process to form a passivation layer 12, photoetching, patterning and etching, and forming an electrical lead-out hole Pad as shown in figure 1 f;

step B6: etching a part of the MEMS resonant cantilever beam region to the top layer silicon 1 to form a channel region;

removing all the dielectric layers 10 and the passivation layers 12 above the top layer silicon 1 of one part of the MEMS resonant cantilever beam area layer by layer until the top layer silicon 1 leaks out by adopting a dry etching process for the device finished in the step B5, as shown in figure 1 g;

and C: and preparing an electrode and an MEMS resonant cantilever beam to complete the preparation of the CMOS-MEMS integrated chip.

Step C1: preparing an electrode in the electrical lead-out hole Pad prepared in the step B5;

the material of the electrode includes: common metals such as Cr, Pt, Au, Ti, etc. or combinations thereof;

for the device prepared in the step B, preparing an electrode pattern on the electrical lead-out hole Pad prepared in the step B5 through deposition, photoetching, stripping or etching and other processes, wherein the electrode pattern is consistent with the electrical lead-out hole Pad pattern, as shown in fig. 1 h;

step C2: etching the top silicon 1 in the channel region formed in the step B6 to manufacture an MEMS resonant cantilever beam pattern;

patterning the top layer silicon 1 in the channel region by adopting a dry etching process to form an MEMS resonant cantilever beam pattern, wherein an etching stop layer is an oxygen buried layer 2 of the SOI substrate, and is shown in figure 1 i;

step C3: and preparing the MEMS resonant cantilever beam to complete the preparation of the CMOS-MEMS integrated chip.

Depositing silicon dioxide films 13 on the front and back surfaces of the SOI substrate obtained in the step C2 by adopting PECVD, and manufacturing mask patterns by adopting double-surface alignment photoetching; photoetching and patterning the silicon dioxide film 13 on the front surface of the SOI substrate, and performing mask compensation on the cantilever beam by using the silicon dioxide film 13 on the front surface; etching bulk silicon from the back of the SOI substrate by adopting DRIE (DRIE etching) until the thickness of the rest is 100-200 microns; then growing a layer of metal Al film 14 on the back of the wafer, and isotropically etching the residual silicon from the front; the metal Al thin film 14 serves as a cut-off layer for front isotropic etching and also plays a role in heat conduction to ensure that the wafer can be effectively cooled in the etching process, as shown in fig. 1 j;

and removing the buried oxide layer 2 and the metal Al film 14 of the exposed SOI substrate in the channel region by adopting a wet etching method, releasing the MEMS resonant cantilever beam structure, preparing the MEMS resonant cantilever beam, and finishing the preparation of the CMOS-MEMS integrated chip. As shown in fig. 1 k.

In the embodiment of the present disclosure, fig. 2 is a distribution diagram of the piezoresistive coefficients in P-type and N-type 100 crystal plane silicon, and as shown in fig. 2, it can be seen that the piezoresistive coefficient of the P-type doped silicon wafer reaches the maximum value in the <110> crystal direction, and the piezoresistive coefficient of the N-type doped silicon wafer reaches the maximum value in the <100> crystal direction, so that the P-type impurity should be implanted along the <110> crystal direction, and the N-type impurity should be implanted along the <100> crystal direction, so as to reach the maximum value of the piezoresistive coefficient, thereby improving the detection performance and sensitivity of the sensor manufactured by the device. The ions implanted in step B2 should be implanted along the <110> crystal orientation.

So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.

From the above description, those skilled in the art should clearly understand the present disclosure as a method for manufacturing a CMOS-MEMS integrated chip on a large scale.

In summary, the present disclosure provides a method for manufacturing a CMOS-MEMS integrated chip in a large scale, in which a link of injecting an N well/a P well by a CMOS process is used to manufacture the N well/the P well in an MEMS region, and P +/N + is injected into the N well/the P well to manufacture a piezoresistive portion of the MEMS region, thereby solving a contradiction that the CMOS process tends to use a P-type substrate and the MEMS resonant cantilever manufacturing process tends to use an N-type substrate. The method adopts the Inter-CMOS and Post-CMOS processes, organically fuses the CMOS process and the MEMS bulk silicon manufacturing process, completes the manufacture of the MEMS electrical structure in the CMOS process, protects the passivation layer of a silicon wafer after the CMOS process is completed, completes the manufacture of the MEMS resonant cantilever beam through the MEMS bulk silicon process, avoids the influence of a high-temperature process in the conventional manufacture of the MEMS electrical structure on the CMOS circuit, is compatible with the MEMS process and the CMOS process, improves the radiation resistance of the CMOS circuit, inhibits the latch-up effect, reduces the parasitic capacitance of a device, reduces the signal noise, improves the stability and the yield of the device, is a CMOS-MEMS integrated chip manufacturing method with high process compatibility, and is convenient for large-scale manufacture.

It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure.

And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.

Unless otherwise indicated, the numerical parameters set forth in the specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by the present disclosure. In particular, all numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about". Generally, the expression is meant to encompass variations of ± 10% in some embodiments, 5% in some embodiments, 1% in some embodiments, 0.5% in some embodiments by the specified amount.

Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.

In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.

The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims (6)

1. A scale manufacturing method of CMOS-MEMS integrated chip organically fuses CMOS process and MEMS bulk silicon manufacturing process, comprising the following steps:

step A: selecting an SOI substrate and dividing a CMOS circuit area and an MEMS resonant cantilever beam sensor area on the SOI substrate; the SOI substrate comprises top silicon (1), a buried oxide layer (2) and bulk silicon (3);

and B: c, manufacturing a CMOS circuit and an MEMS resonant cantilever beam sensor circuit on the top silicon (1) of the SOI substrate selected in the step A by adopting a CMOS process;

the step B comprises the following steps:

step B1: preparing an N trap (4) and field oxygen (5) on the top layer silicon (1);

step B2: preparing gate oxide (6) on the surface of the device after the step B1 is finished, and preparing a polysilicon gate (7) on the surface of the gate oxide (6) prepared in the CMOS circuit area;

step B3: ion implantation is carried out in the CMOS circuit area and the MEMS resonant cantilever beam sensor area to form P + (8), and ion implantation is carried out in the CMOS circuit area to form N + (9);

step B4: preparing a dielectric layer (10) and an Al transmission line (11) on the surface of the SOI substrate after the step B3 is finished;

step B5: preparing a passivation layer (12) on the surface of the SOI substrate after the step B4 is finished, and opening an electrical lead-out hole; and

step B6: etching a part of the MEMS resonant cantilever beam region to the top layer silicon (1) to form a channel region;

and C: preparing an electrode and an MEMS resonant cantilever beam to complete the preparation of the CMOS-MEMS integrated chip;

the step C comprises the following steps:

step C1: preparing an electrode in the electrical outlet prepared in step B5;

step C2: etching the top layer silicon (1) in the channel region formed in the step B6 to manufacture an MEMS resonant cantilever beam pattern;

step C3: preparing an MEMS resonant cantilever beam to complete the preparation of the CMOS-MEMS integrated chip;

the electrode material prepared in the step C1 includes: cr, Pt, Au, Ti, or a combination thereof;

in the step C3, silicon dioxide films (13) are deposited on the front and back sides of the SOI substrate after the step C2 by adopting a plasma enhanced chemical vapor deposition method, and mask patterns are manufactured by adopting double-sided alignment photoetching; photoetching and patterning the silicon dioxide film (13) on the front surface of the SOI substrate, and performing mask compensation on the cantilever beam by using the silicon dioxide film (13) on the front surface; etching the bulk silicon on the back surface of the SOI substrate by adopting a deep reactive ion etching process until the residual thickness is 100-200 microns, then growing a layer of metal Al film (14) on the back surface of the wafer, and isotropically etching the residual bulk silicon from the front surface; and removing the buried oxide layer (2) and the metal Al film (14) of the exposed SOI substrate in the channel region by adopting a wet etching method, and releasing the MEMS resonant cantilever structure.

2. The method for the scaled production of the CMOS-MEMS integrated chip according to claim 1, wherein the SOI substrate selected in the step A is a P-type top silicon SOI substrate or an N-type top silicon SOI substrate.

3. The method for the scaled fabrication of CMOS-MEMS integrated chips according to claim 1, wherein the top silicon (1) in step a comprises: (100) crystal plane P-type silicon or (100) crystal plane N-type silicon.

4. The method for manufacturing an integrated chip of CMOS-MEMS according to claim 1, wherein in step B3, the implantation of boron ions and phosphorus ions in the CMOS circuit region and the implantation of boron ions in the MEMS resonant cantilever sensor region are completed by the CMOS process on the SOI substrate after the step B2 is completed, so as to form the piezoresistance.

5. The method for mass-producing CMOS-MEMS integrated chip as claimed in claim 1, wherein in step B3, when ion implantation forms P + (8), implantation is carried out along the (110) crystal orientation of the top layer silicon (1); when the ion implantation forms N + (9), the ion implantation is carried out along the (100) crystal orientation of the top layer silicon (1).

6. The large-scale manufacturing method of the CMOS-MEMS integrated chip according to claim 1, wherein in the step C2, the top layer silicon (1) is etched by a dry etching process to manufacture the MEMS resonant cantilever beam pattern, and the etching stop layer is the buried oxide layer (2).

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