CN106365106B - MEMS device and its manufacturing method - Google Patents
MEMS device and its manufacturing method Download PDFInfo
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- CN106365106B CN106365106B CN201610847980.8A CN201610847980A CN106365106B CN 106365106 B CN106365106 B CN 106365106B CN 201610847980 A CN201610847980 A CN 201610847980A CN 106365106 B CN106365106 B CN 106365106B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0032—Packages or encapsulation
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00349—Creating layers of material on a substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00388—Etch mask forming
- B81C1/00404—Mask characterised by its size, orientation or shape
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2201/00—Specific applications of microelectromechanical systems
- B81B2201/02—Sensors
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/09—Packages
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Abstract
This application discloses MEMS device and its manufacturing methods.The MEMS device includes：Substrate；MEMS sensor on substrate, the MEMS sensor include cavity formed on a substrate and the structure sheaf on cavity；And the transistor in MEMS sensor, wherein at least part of the transistor is formed in the structure sheaf of the MEMS sensor.MEMS sensor and transistor stack are formed vertical structure by the MEMS device, to reducing chip size, improving chip performance and reducing device cost.
Description
Technical field
The invention belongs to microelectromechanical systems (MEMS) technical fields, more particularly, to single chip integrated MEMS devices
Part and its manufacturing method.
Background technology
MEMS (Micro Electromechanical System, i.e. microelectromechanical systems) refers to collection micro sensing
Device, actuator and signal processing and control circuit, interface circuit, communication and power supply are in the Micro Electro Mechanical System of one.Using
Microsensor, microactrator, micro parts, Micromechanical Optics device, vacuum microelectronic device, the electric power electricity of MEMS technology making
Sub- device etc. is in Aeronautics and Astronautics, automobile, biomedicine, environmental monitoring, military affairs and all spectra that almost people are touched
In suffer from very wide application prospect.Currently, the leading products in the markets MEMS are pressure sensor, accelerometer, micro- top
Spiral shell instrument and hard drive head etc..
With the development of integrated circuit miniaturization and multifunction, MEMS sensor and signal processing circuit it is integrated
As a kind of inexorable trend.There are three types of the integrated approaches of the two：Hybrid integrated, the integrated and complete single-chip integration of meromict.Mixing
Integrated is to manufacture MEMS sensor in different tube cores from signal processing circuit, is then packaged as a package assembling.Half
Hybrid integrated is produced on MEMS sensor and signal processing circuit on different silicon wafers, real using the bonding of silicon wafer chip level
Both existing interconnection, is then packaged as a package assembling.Complete single-chip integration is then by MEMS sensor and signal processing electricity
Road is produced on the same silicon wafer, forms singulated dies.Single chip integrated MEMS device is current most mainstream and state-of-the-art
Technology.
In existing Monolithic integrated MEMS device fabrication, signal processing is made in the first area of silicon wafer first
Then the structures such as the transistor of circuit use sacrificial layer to protect first area, MEMS sensings are made in the second area of silicon wafer
Device.The transistor of MEMS sensor and signal processing circuit forms planar structure, eventually forms metal interconnection.In this manufacture work
In skill, the manufacture craft of MEMS sensor and transistor is independent of one another, incompatible, thus there is manufacturing steps to lead to work more
The problem of skill complicates.
In addition, since MEMS sensor and signal processing circuit are arranged according to planar structure, die area is caused to increase
Add.
Invention content
In view of the above problems, MEMS sensor and transistor stack are formed vertically the purpose of the present invention is to provide a kind of
The MEMS device and its manufacturing method of structure, to reducing chip size, improving chip performance and reducing device cost.
According to an aspect of the present invention, a kind of MEMS device is provided, including：Substrate；MEMS sensor on substrate,
The MEMS sensor includes cavity formed on a substrate and the structure sheaf on cavity；And it is located at MEMS sensor
On transistor, wherein at least part of the transistor is formed in the structure sheaf of the MEMS sensor.
Preferably, the MEMS sensor further includes：The first seed layer on substrate, in first seed layer
Form the cavity；Second of sublayer on the cavity, wherein the structure sheaf include second of sublayer and
The epitaxial layer formed on the surface of first seed layer and second of sublayer.
Preferably, the MEMS sensor further includes：The first isolation structure in first seed layer, described
One isolation structure surrounds the cavity, the active region for limiting the MEMS sensor.
Preferably, first isolation structure is the doped region in first seed layer, first isolation junction
Structure is extended downwardly from the first described sub-layer surface, and junction depth is 5 microns or more.
Preferably, the transistor is CMOS transistor or bipolar transistor.
Preferably, the well region of the transistor is formed in the structure sheaf of the MEMS sensor, and the transistor also wraps
The first gate stack for including the source/drain region being formed in well region and being formed on well region.
Preferably, the transistor further includes the grid curb wall positioned at the first gate stack both sides, and folded positioned at the first grid
Silicide layer in layer surface.
Preferably, further include：Interlayer dielectric layer；The opening formed in interlayer dielectric layer；And on interlayer dielectric layer
Form the interconnection that the source/drain region and first gate stack are reached via opening.
Preferably, further include：Passivation layer on the transistor, the internal junction for protecting the MEMS device
Structure.
Preferably, further include：Second isolation structure, the active area for limiting the transistor, wherein described second every
It is the oxide layer formed using silicon location oxidation of silicon process from structure.
Preferably, further include：Third isolation structure, the active area for limiting the transistor, wherein the third every
It is shallow trench isolation from structure.
Preferably, the MEMS sensor is piezoresistive transducer.
Preferably, further include：Multiple sensitive resistances, the doped region being respectively located in the epitaxial layer, wherein described more
A sensitive resistance is located at the outside of the active area of the transistor.
Preferably, further include：Multiple second gate stacks, are located on the multiple sensitive resistance, wherein the multiple
One one corresponding in the multiple sensitive resistance of second gate stack separately constitutes resistive element, for improving pressure-sensitive electricity
The temperature coefficient of resistance.
Preferably, the number of the multiple sensitive resistance is four, and the MEMS device further includes：Interconnection is used for institute
It states four sensitive resistances and connects into Wheatstone bridge.
Preferably, the MEMS sensor is capacitance type sensor.
Preferably, further include：Contact zone, the contact zone are the doped region in the epitaxial layer, wherein described to connect
Touch the outside that area is located at the active area of the transistor.
Preferably, the thickness of the structure sheaf is 6 microns to 10 microns.
Preferably, the thickness of first seed layer is 10 microns to 50 microns.
Preferably, the well region extends downwardly 2 microns to 4 microns from the surface of the structure sheaf.
Preferably, the source/drain region extends downwardly 0.5 micron to 2 microns from the surface of the well region.
According to another aspect of the present invention, a kind of manufacturing method of MEMS device is provided, including：MEMS is formed on substrate
Sensor, the MEMS sensor include cavity formed on a substrate and the structure sheaf on cavity；And in MEMS
Transistor is formed on sensor, wherein at least part of the transistor is formed in the structure sheaf of the MEMS sensor.
Preferably, the step of forming the MEMS sensor include：The first seed layer is formed on substrate；Described first
The first isolation structure is formed in seed layer, first isolation structure is used to limit the active region of the MEMS sensor；
Electrochemical corrosion is carried out in the active region that first isolation structure limits, to be formed each other in first seed layer
Adjacent the first porous layer and the second porous layer, first porous layer are located at the lower section of second porous layer, and described
The porosity of first porous layer is higher than second porous layer；It anneals so that first porous layer is transformed into the sky
Chamber and second porous layer are transformed into second of sublayer.
Preferably, the thickness of first porous layer is 5.5 to 6.5 microns, the thickness of second porous layer be 0.5 to
1.5 micron.
Preferably, the porosity of first porous layer is 70%-90%, and the porosity of second porous layer is
10%-40%.
Preferably, first seed layer is P-type silicon layer, and first isolation structure is N-doped zone.
Preferably, in electrochemical corrosion, the positive electrode of the first seed layer connection power supply, the substrate connects power supply
Negative electrode.
Preferably, in the electrochemical corrosion, first after-applied first electric current and the second electric current, wherein first electricity
The current density of stream is less than the current density of second electric current.
Preferably, the current density of first electric current is 20 to 50 milliamperes every square centimeter, and the electric current of the second electric current is close
Degree is every square centimeter for 50 to 100 milliamperes.
Preferably, acid solution is used in the electrochemical corrosion.
Preferably, the temperature of the annealing is higher than 1050 degrees Celsius.
Preferably, between the step of forming the first isolation structure and the step of carrying out electrochemical corrosion, further include：Institute
It states and forms hard mask in the first seed layer, wherein the hard mask is aligned with first isolation structure, and with described first
Isolation structure limits the active region of the MEMS sensor together.
Preferably, the hard mask is silicon nitride layer.
Preferably, the step of formation structure sheaf includes：In the surface shape of first seed layer and second of sublayer
At epitaxial layer.
Preferably, the thickness of the structure sheaf is 6 microns to 10 microns.
Preferably, the transistor is CMOS transistor or bipolar transistor.
Preferably, the well region of the transistor is formed in the structure sheaf of the MEMS sensor, and the transistor also wraps
The first gate stack for including the source/drain region being formed in well region and being formed on well region.
Preferably, after the step of forming transistor, further include：Interlayer dielectric layer is formed on the transistor；
Opening is formed in interlayer dielectric layer；And it is formed on interlayer dielectric layer and reaches the source/drain region and described first via opening
The interconnection of gate stack.
Preferably, after the step of forming transistor, further include：Passivation layer is formed on the transistor, for protecting
Protect the internal structure of the MEMS device.
Preferably, the thickness of first seed layer is 10 microns to 50 microns.
Preferably, the well region extends downwardly 2 microns to 4 microns from the surface of the structure sheaf.
Preferably, the source/drain region extends downwardly 0.5 micron to 2 microns from the surface of the well region.
Preferably, the step of formation transistor further includes：The second isolation structure is formed, for limiting having for the transistor
Source region, wherein second isolation structure is the oxide layer formed using silicon location oxidation of silicon process.
Preferably, the step of formation transistor further includes：Third isolation structure is formed, for limiting having for the transistor
Source region, wherein the third isolation structure is shallow trench isolation.
Preferably, the MEMS sensor is piezoresistive transducer.
Preferably, the step of formation MEMS sensor further includes：Multiple sensitive resistances are formed in the epitaxial layer,
In, the multiple sensitive resistance is respectively multiple doped regions of the outside of the active area positioned at the transistor.
Preferably, after the step of forming multiple sensitive resistances, further include：It is formed on the multiple sensitive resistance more
A second gate stack a, wherein difference corresponding in the multiple sensitive resistance of the multiple second gate stack
Form resistive element, the temperature coefficient for improving varistor.
Preferably, the number of the sensitive resistance is four, and the method further includes forming interconnection, described to interconnect institute
It states four sensitive resistances and connects into Wheatstone bridge.
Preferably, the MEMS sensor is capacitance type sensor.
Preferably, further include：Contact zone is formed in the epitaxial layer, wherein the contact zone is positioned at the crystal
The doped region of the outside of the active area of pipe.
MEMS device and its manufacturing method according to the ... of the embodiment of the present invention pass the transistor of signal processing circuit and MEMS
Sensor is integrated in one single chip, and stacks the MEMS device for forming vertical structure.The structure sheaf of MEMS sensor is used for shape
At the well region of transistor.The volume of the integrated system reduces, lower power consumption.The number of pin of package assembling is reduced, to advantageous
In the volume, the external complexity connected up of reduction and raising reliability that reduce package assembling.In addition, the quantity of peripheral cell subtracts
It is few, so as to reduce circuit cost.
Further, in the MEMS device, the transistor of signal processing circuit is located near MEMS sensor, to subtract
Small parasitic capacitance and distribution capacity can improve the precision of MEMS device.
In a preferred embodiment, the thickness of epitaxial layer is, for example, 6 microns to 10 microns, preferably 8 microns.Transistor
Source/drain region is only located in the range of 2 microns of the surface of epitaxial layer.Therefore, the response characteristic of MEMS sensor is not affected by top
Transistor arrangement significantly affects.The MEMS device can take into account the design requirement of MEMS sensor and signal processing circuit, from
And realize the respective performance optimization of the two.
Further, the MEMS device manufacturing method and existing ic process compatibility, can be directly in integrated circuit
It is applied on production line, need not be that the making of MEMS sensor divides special making region.Further, since the present invention is set
The technological process of meter intersects technique using IC-MEMS-IC, that is, the photoetching, injection, etching of integrated circuit technology is utilized to make MEMS
Then the substrate and separation layer of sensor utilize MEMS electrochemical corrosive process to form the cavity structure of MEMS sensor, finally
It uses circuit technology to complete the integrated of MEMS sensor and transistor circuit part in vertical direction, realizes MEMS sensor
With the single-chip integration of signal processing circuit, specific MEMS or protection using integrated circuit layer need not be made, technological process is simplified.
Description of the drawings
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings：
The signal in each stage of MEMS device manufacturing method according to a first embodiment of the present invention is shown respectively in Fig. 1 to 10
Property sectional view.
Figure 11 shows schematically cutting for a part of stage of MEMS device manufacturing method according to a second embodiment of the present invention
Face figure.
Specific implementation mode
Hereinafter reference will be made to the drawings is more fully described various embodiments of the present invention.In various figures, identical element
It is indicated using same or similar reference numeral.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.
The present invention can be presented in a variety of manners, some of them example explained below.
The signal in each stage of MEMS device manufacturing method according to a first embodiment of the present invention is shown respectively in Fig. 1 to 10
Property sectional view.
As shown in Figure 1, forming the first seed layer 102 on substrate 101, and first is formed in the first seed layer 102
Isolation structure 103 is to limit the active region of MEMS sensor.
Preferably, which can be semiconductor substrate.It is highly preferred that semiconductor substrate 101 is, for example, silicon substrate.
It is further preferred that the e.g. crystal orientation of semiconductor substrate 101 is<100>P-type silicon substrate.The doping concentration of substrate 101 is controlled,
Make its resistivity for example in the range of 0.5 ohmcm.
Preferably, the first seed layer 102 is, for example, the P-type silicon layer being lightly doped.The doping for controlling the first seed layer 102 is dense
Degree, makes its resistivity for example in the range of 1~5 ohmcm.
For example, low-pressure chemical vapor phase deposition (LPVCD) or plasma enhanced chemical vapor deposition may be used
The methods of (PECVD), silicon is deposited on substrate 101 to form the first seed layer 102.The thickness of first seed layer 102 is 10
Micron is to 50 microns, preferably 30 microns.
Preferably, the first isolation structure 103 is, for example, the N-doped zone being lightly doped.First isolation structure 103 from the first
The surface of sublayer 102 extends downwardly, and junction depth is not less than 5 microns, preferably 10 microns.
Resist layer is formed in the step of forming the first isolation structure 103, such as on the surface of the first seed layer 102,
The pattern for including opening is formed in resist layer using photoetching process.Using resist layer as mask, ion implanting is carried out.
After ion implanting, resist layer can be removed by being dissolved in ashing or solvent.
Above-mentioned ion implanting forms doped region as the first isolation structure 103 in the presumptive area of the first seed layer 102.The
The shape of patterns of openings in the pattern and mask of one isolation structure 103 is identical.
Then, hard mask 104 is formed in the first seed layer 102, and carries out electrochemical corrosion via hard mask 104,
A part for first seed layer, 102 neighbouring surface is transformed into first porous layer 105 and the second porosity of the first porosity
Second porous layer 106, as shown in Figure 2.
In this embodiment, corroded twice using different electric currents in electrochemical corrosion so that formation it is porous
The characteristic feature of layer is double-layer structure, the first porous layer 105 of respectively the first porosity and the second of the second porosity porous
Layer 106.First porous layer 105 is located at the lower section of the second porous layer 106, and the first porosity is more than the second porosity.
Insulating layer and patterning are formed in the step of forming hard mask 104, such as on the surface of the first seed layer 102
Insulating layer.The thickness of the insulating layer is, for example, hundreds of nanometers, preferably 150 to 200 nanometers.
The methods of magnetron sputtering or plasma enhanced chemical vapor deposition (PECVD) may be used, in the first seed
102 deposit silicon nitride of layer are to form insulating layer.
In the patterned insulation layer the step of, such as on the surface of insulating layer resist layer is formed, is existed using photoetching process
The pattern for including opening is formed in resist layer.Using resist layer as mask, insulating layer is removed using the etchant of selectivity
Expose portion.Due to the selectivity of etching, which can stop on the surface of the first seed layer 102.After the etching, may be used
To remove resist layer by being dissolved in ashing or solvent.
In the electrochemical corrosion the step of, using above-mentioned patterned insulating layer as hard mask 104.In hard mask 104
Opening is corresponding with the active region that the first isolation structure 103 limits, and the size of the opening is less than or equal to the size of active area.
Preferably, the opening in hard mask 104 is aligned with the first isolation structure 103.
Positive electrode is connected on surface of first seed layer 102 via the opening exposure in hard mask 104, in substrate 101
Negative electrode is connected on the surface opposite with the first seed layer 102, then immerses entire semiconductor structure in acid solution, such as
The mixed liquor of ethyl alcohol/hydrofluoric acid/water or the mixed liquor of acetone/hydrofluoric acid/water.
External power supply is connected to positive and negative electrode, and first after-applied different size of electric current.First current density is general
It is every square centimeter for 20 to 50 milliamperes, the second current density be generally 50 to 100 milliamperes it is every square centimeter.Preferably, the first electricity
Current density is 30 to 40 milliamperes every square centimeter, and the second current density is 60 to 70 milliamperes every square centimeter.
The electric current flowed through between above-mentioned anode and cathode, the corresponding seed layer of opening in the hard mask 104 are adjacent
Electrochemical corrosion is generated in the region of near surface, to form the first porous layer 105 and the second porous layer 106.It then will be positive and negative
Electrode is removed from first seed layer 102 and substrate 101, stops electrochemical corrosion.By entire semiconductor structure from corrosion
It takes out, is cleaned in liquid, to complete electrochemical corrosion step.Then, hard mask is removed using the etchant of selectivity
104, it is cleaned and is dried, so as to continuously form additional layer in subsequent technique.
In above-mentioned electrochemical corrosion step, more than first are limited together using hard mask 104 and the first isolation structure 103
The position of aperture layer 105 and the second porous layer 106.Further, the corrosion current and etching time of above-mentioned electrochemical corrosion are controlled
Size, to control the first porous layer 105 and the second porous layer 106 porosity and thickness.The thickness of first porous layer can
Think 5.5 to 6.5 microns, the thickness of the second porous layer can be 0.5 to 1.5 micron, for example, the hole of the first porous layer 105
Rate is 70%-90%, and thickness is about 6 microns, and the porosity 10%-40% of the second porous layer 106, thickness is about 1 micron.At this
In embodiment, the overall thickness of the first porous layer 105 and the second porous layer 106 is less than the junction depth of the first isolation structure 103 so that institute
The lateral extensions of the first porous layer 105 and the second porous layer 106 can be limited by stating the first isolation structure 103.
Then, it anneals in the hydrogen gas atmosphere so that the porous silicon in the first porous layer 105 and the second porous layer 106
Mutually fusion.First porous layer 105 forms cavity 107, the second porous layer since porosity is larger during silicon merges
106, due to porosity, are densified during silicon merges, and second seed fine and close above cavity is covered in be formed
Layer 108, as shown in Figure 3.
In above-mentioned annealing steps, annealing temperature is generally greater than 1050 degrees Celsius, and the time is 5 minutes to 30 minutes.It is excellent
Selection of land, annealing temperature are 1100 to 1300 degrees Celsius, and the time is 20 minutes.Annealing at such a temperature can obtain quasi- monocrystalline knot
Second of sublayer 108 of structure.In this embodiment, using hydrogen environment, to prevent the oxidation of second seed layer.In the reality of replacement
It applies in example, inert gas may be used and substitute hydrogen, to realize similar effect.
Second of sublayer 108 is mainly merged by the silicon of the second porous layer 106 and is formed, and the thickness of the two is suitable.In the implementation
In example, the thickness of second of sublayer 108 is about 1 micron.
Then, epitaxial layer 110 is formed on the surface of the first seed layer 102 and second of sublayer 108, as shown in Figure 4.
For example, low-pressure chemical vapor phase deposition (LPVCD) or plasma enhanced chemical vapor deposition may be used
The methods of (PECVD), the epitaxial growth monocrystalline silicon on the surface of the first seed layer 102 and second of sublayer 108 is outer to be formed
Prolong layer 110.Epitaxial growth temperature is generally greater than 1050 degrees Celsius.Preferably, epitaxial growth temperature is 1100 to 1300 degrees Celsius.
By the composition and concentration and deposition time of control vaporous precursors, the thickness of epitaxial layer 110 can be controlled.
In this embodiment, the thickness of epitaxial layer 110 is, for example, 6 microns to 10 microns, preferably 8 microns.In epitaxial layer
110 and the thickness of second of sublayer 108 be respectively that the thickness for the structure sheaf being made of the two is about in the case of 8 microns and 1 micron
It is 9 microns.In final MEMS device, the structure of epitaxial layer 110 and second of sublayer 108 together as MEMS sensor
Layer.The thickness of structure sheaf is related to the sensitivity of MEMS sensor and structural strength.If the thickness of structure sheaf is excessive, sensitive
Spend low, if thickness is too small, structural strength is low to lead to device failure and poor reliability.
The epitaxial layer 110 can be doping to N-type in situ, or use individual ion implantation doping at N after the deposition
Type.The doping concentration for controlling epitaxial layer 110, makes its resistivity for example in the range of 1~5 ohmcm.
Then, well region 112 and the second isolation structure 111 are formed in epitaxial layer 110, as shown in Figure 5.
The epitaxial layer 110 will be used to form transistor, which can be Complementary Metal Oxide Semiconductor Field Effect
(CMOS) transistor or bipolar transistor, the second isolation structure 111 are used to limit the active area of transistor.It is N in transistor
In the case of type metal oxide semiconductor field-effect transistor (N-MOSFET), well region 112 is, for example, the p-type doping being lightly doped
Area.The depth that the well region 112 is extended downwardly from the surface of epitaxial layer 110 is less than 5 microns, preferably 2 microns to 4 microns so that
The well region is located in epitaxial layer 110.
Resist layer is formed in the step of forming well region 112, such as on the surface of epitaxial layer 110, using photoetching process
The pattern for including opening is formed in resist layer.Using resist layer as mask, ion implanting is carried out.Ion implanting it
Afterwards, resist layer can be removed by being dissolved in ashing or solvent.
Above-mentioned ion implanting forms doped region as well region 112 in the presumptive area of epitaxial layer 110.The pattern of well region 112
Shape with the patterns of openings in mask is identical.
Silicon location oxidation of silicon process is used in the step of forming the second isolation structure 111, such as on the surface of epitaxial layer 110
(LOCOS) oxide layer is formed, as the second isolation structure 111.
LOCOS techniques are the regional area oxidation technologies carried out using silicon nitride layer as hard mask, wherein utilizing hard mask
Pattern limit oxide regions.After forming the second isolation structure 111, hard mask 104 is removed using the etchant of selectivity,
It is cleaned and is dried.
Then, in the case of MEMS sensor is piezoresistive transducer, such as four sensitivities are formed in epitaxial layer 110
Resistance 113, as shown in Figure 6.Four sensitive resistances 113 are symmetrically distributed in the active area periphery of transistor, such as positioned at sky
In the perimeter of chamber 107.
Preferably, sensitive resistance 113 is, for example, the P-doped zone being lightly doped.Table of the sensitive resistance 113 from epitaxial layer 110
Extend downwards, junction depth is about 1 micron to 2 microns.
Resist layer is formed in the step of forming sensitive resistance 113, such as on the surface of epitaxial layer 110, using photoetching
Technique forms the pattern for including opening in resist layer.Using resist layer as mask, ion implanting, implantation dosage example are carried out
Such as it is about E15 every square centimeter.After ion implantation, resist layer can be removed by being dissolved in ashing or solvent.
Above-mentioned ion implanting forms doped region as sensitive resistance 113 in the presumptive area of epitaxial layer 110.Sensitive resistance
The shape of patterns of openings in 113 pattern and mask is identical.
In alternate embodiments, such as in the case of MEMS sensor is capacitance type sensor, contact may be used
Area replaces varistor.The contact zone becomes for connecting external electrode so as to the capacitance between detection structure layer and substrate
Change.
Then, oxide skin(coating) and conductor layer are sequentially formed on the surface of semiconductor structure, and by oxide skin(coating) and are led
Body pattern layers are at the gate stack including gate oxide 114 and grid conductor 115, and form source/drain region in well region 112
116, as shown in Figure 7.
In the above-mentioned formation oxide skin(coating) the step of, for example, on the surface of well region 112 and sensitive resistance 113, using heat
Oxidation forms oxide skin(coating).It, can be with the thickness of control oxide layer by controlling the temperature and time of thermal oxide.
In the above-mentioned formation conductor layer the step of, by known depositing technics, conductor layer is formed on the oxide layer.On
It is, for example, in electron beam evaporation (EBM), chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering to state depositing technics
One kind.By controlling the parameter of depositing technics, such as the concentration of vaporous precursors, deposition temperature and deposition time, can control
The thickness of conductor layer processed.
The oxide skin(coating) and conductor layer formed in above-mentioned steps for example covers the whole surface of semiconductor structure.
Resist layer is formed in above-mentioned patterned step, such as on the surface of conductor layer, using photoetching process anti-
Lose the pattern for being formed in oxidant layer and including opening.Using resist layer as mask, using selectivity etchant removal conductor layer and
The expose portion of oxide skin(coating).Due to the selectivity of etching, which can be in epitaxial layer 110, well region 112, sensitive resistance 113
Surface stop.After the etching, resist layer can be removed by being dissolved in ashing or solvent.
After a patterning steps, it is respectively formed on by 114 He of gate oxide on the surface of well region 112 and sensitive resistance 113
The gate stack that grid conductor 115 forms.In an example, gate oxide 114 is for example made of silica, and grid conductor is for example
It is made of the polysilicon adulterated.The thickness of gate oxide 114 is about 25 nanometers to 30 nanometers, and the thickness of grid conductor 115 is about
450 nanometers.
Although should be noted that the structure phase of the gate stack and the gate stack of 112 top of well region on sensitive resistance 113
Together, but the former is not intended as a part for transistor.In fact, the gate stack on sensitive resistance 113 and sensitive resistance 113
It is connected in series with, collectively constitutes resistive element, be located on current path.Resistive element can improve varistor using gate stack
Temperature coefficient.
In the above-mentioned formation source/drain region the step of, photoresist mask can be formed, opening in photoresist mask
The active area of mouth exposed transistor, also, photoresist mask blocks the remainder of semiconductor structure.With resist layer with
And grid conductor carries out ion implanting together as mask.After ion implantation, can by ashing or solvent dissolve come
Remove resist layer.
Presumptive area of the above-mentioned ion implanting in well region 112 forms doped region as source/drain region 116, the source/drain region
116 be for example self aligned with grid conductor 115.It is N-type mos field effect transistor (N- in transistor
MOSFET in the case of), source/drain region 116 is N-doped zone.The depth that the source/drain region 116 is extended downwardly from the surface of well region 112
Degree is 0.5 micron to 2 microns so that the source/drain region 116 is located in well region 112.
Then, in the active area of transistor, grid curb wall 117 is formed in the both sides of gate stack, and in grid conductor
115 surface forms silicide layer 118, as shown in Figure 8.
In the above-mentioned formation grid curb wall the step of, by above-mentioned known depositing technics, on the surface of semiconductor structure
It is upper to form conformal (conformal) nitride layer.In one example, which is about 5 nanometers to 30 nanometers of thickness
Silicon nitride layer.In the case of mask is not used, by anisotropic etch process (for example, reactive ion etching), go
Except the part of nitride layer being laterally extended so that the vertical component that nitride layer is located at grid conductor 115 retains, to be formed
Grid curb wall 117.
In the above-mentioned formation silicide layer the step of, by above-mentioned known depositing technics, on the surface of semiconductor structure
Form metal layer.One in the group that the metal layer is made of the alloy selected from Ni, W, Ti, Co and these elements and other elements
Kind composition.In one example, which is the Co layers by sputtering deposit.Then, thermal annealing is carried out, such as is taken the photograph 300
Family name's degree was to thermal annealing at a temperature of 500 degrees Celsius 1-10 seconds.
Thermal annealing makes metal layer carry out silicification reaction on the surface of grid conductor 115 to form silicide layer 118.Silication
Nitride layer 118 can reduce the contact resistance of grid conductor 115.By above-mentioned known dry etching and wet etching in silicide
Wet etching removes the unreacted part of metal layer.In a preferred embodiment, it can also be formed on the surface of source/drain region 116
Silicide layer 118.
Then, interlayer dielectric layer 119 is formed on the surface of semiconductor structure, and is formed in interlayer dielectric layer 119
To the opening of grid conductor 115 and source/drain region 116, and is formed on interlayer dielectric layer 119 and led via opening electrical connection grid
The interconnection 120 of body 115 and source/drain region 116, as shown in Figure 9.
In above-mentioned formation interlayer dielectric layer 119 the step of, such as pass through above-mentioned known depositing technics, it is preferable that adopt
With chemical vapor deposition, forms boron-phosphorosilicate glass (BPSG) on the surface of semiconductor structure or ethyl orthosilicate (TEOS) is used as layer
Between dielectric layer 119.
Resist layer is formed in the step of above-mentioned formation is open, such as on the surface of interlayer dielectric layer 119, using photoetching
Technique forms the pattern for including opening in resist layer.Using resist layer as mask, removed using the etchant of selectivity
The expose portion of insulating layer.Due to the selectivity of etching, which can stop on the surface of grid conductor 115 and source/drain region 116
Only.After the etching, resist layer can be removed by being dissolved in ashing or solvent.
Conductor layer, such as aluminium are formed in the step of above-mentioned formation interconnects, such as by sputtering.The conductor layer fills interlayer
Opening in dielectric layer 119, and also cover the surface of interlayer dielectric layer 119.Preferably, chemical machinery can further be used
The surface of (CMP) smooth conductor layer is planarized, and conductor layer is patterned to interconnection 120.
Above-mentioned interconnection 120 is not only provided to the electrical connection of the grid conductor 115 and source/drain region 116 of transistor, but also provides
Via the electrical connection of grid conductor 115 and gate oxide 114 to sensitive resistance 113.Silicide layer is formed on grid conductor 115
In the case of, interconnection 120 is electrically connected to grid conductor 115 via silicide layer 118.
In the case of MEMS sensor is piezoresistive transducer, above-mentioned interconnection 120 connects into four sensitive resistances 113
Wheatstone bridge.
Then, by above-mentioned known depositing technics, passivation layer 121 is formed in the whole surface of semiconductor structure, such as
Shown in Figure 10.In this embodiment, passivation layer is for example made of silicon oxide or silicon nitride, the internal junction for protecting MEMS device
Structure.
Figure 11 shows schematically cutting for a part of stage of MEMS device manufacturing method according to a second embodiment of the present invention
Face figure.Before step shown in Figure 11, the step shown in Fig. 1 to Fig. 4 has been executed, it, will after the step shown in Figure 11
Fig. 6 is continued to execute to step shown in Fig. 10.
As shown in figure 11, in a second embodiment, the second isolation structure 111 is replaced using third isolation structure 211.Third
Isolation structure 211 is shallow trench isolation (STI).
In the above-mentioned formation third isolation structure the step of, resist layer is formed on the surface of epitaxial layer 110, using light
Carving technology forms the pattern for including opening in resist layer.Using resist layer as mask, gone using the etchant of selectivity
The expose portion of epitaxial layers, to form shallow trench in the epitaxial layer.By controlling etching period, shallow trench can be controlled
Depth.After the etching, resist layer can be removed by being dissolved in ashing or solvent.
Then, by known depositing technics, insulating layer is formed on the surface of semiconductor structure, the thickness of the insulating layer
At least it is enough to fill shallow trench.Such as it by the surface of chemical-mechanical planarization (CMP) smooth semiconductor structure and removes exhausted
Edge layer is located at the part outside shallow trench, forms shallow trench isolation (STI).
Other aspects of MEMS device manufacturing method according to second embodiment and MEMS device according to first embodiment
Manufacturing method is identical, and this will not be detailed here.
In the MEMS device manufacturing method of above-described embodiment, by the transistor of signal processing circuit and MEMS sensor heap
The folded MEMS device for forming vertical structure, so as to which the two to be integrated in one single chip.The structure sheaf of MEMS sensor is used
In the well region for forming transistor.The thickness of epitaxial layer is, for example, 6 microns to 10 microns, preferably 8 microns.The source/drain of transistor
Area is only located in the range of 2 microns of the surface of epitaxial layer.Therefore, the response characteristic of MEMS sensor is not affected by the transistor of top
Structure significantly affects.
Further, the MEMS device manufacturing method and existing ic process compatibility, can be directly in integrated circuit
It is applied on production line, need not be that the making of MEMS sensor divides special making region.Further, since the present invention is set
The technological process of meter intersects technique using IC-MEMS-IC, that is, the photoetching, injection, etching of integrated circuit technology is utilized to make MEMS
Then the substrate and separation layer of sensor utilize MEMS electrochemical corrosive process to form the cavity structure of MEMS sensor, finally
It uses circuit technology to complete the integrated of MEMS sensor and transistor circuit part in vertical direction, realizes MEMS sensor
With the single-chip integration of signal processing circuit, specific MEMS or protection using integrated circuit layer need not be made, technological process is simplified.
Further, in the MEMS device, the transistor of signal processing circuit is located near MEMS sensor, vertical stacks
Folded mode makes actual die area reduce, and to reduce parasitic capacitance and distribution capacity, can improve the essence of MEMS device
Degree.The volume of integrated system reduces, lower power consumption.The number of pin of package assembling is reduced, to be conducive to reduce package assembling
Volume, reduce the external complexity connected up and improve reliability.In addition, the quantity of peripheral cell is reduced, so as to drop
Low circuit cost.
As described above according to the embodiment of the present invention, there is no all details of detailed descriptionthe for these embodiments, also not
Limit the specific embodiment that the invention is only described.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is in order to preferably explain the principle of the present invention and practical application, belonging to making
Technical field technical staff can utilize modification of the invention and on the basis of the present invention to use well.The protection model of the present invention
The range that the claims in the present invention are defined should be subject to by enclosing.
Claims (48)
1. a kind of MEMS device, including：
Substrate；
MEMS sensor on substrate, the MEMS sensor include cavity formed on a substrate and are located on cavity
Structure sheaf；And
Transistor in MEMS sensor,
Wherein, at least part of the transistor is formed in the structure sheaf of the MEMS sensor,
The MEMS sensor further includes：
The first seed layer on substrate forms the cavity in first seed layer；
Second of sublayer on the cavity,
Wherein, the structure sheaf includes second of sublayer and the table in first seed layer and second of sublayer
The epitaxial layer formed on face.
2. MEMS device according to claim 1, wherein the MEMS sensor further includes：
The first isolation structure in first seed layer, first isolation structure surrounds the cavity, for limiting
The active region of the MEMS sensor.
3. MEMS device according to claim 2, wherein first isolation structure is in first seed layer
Doped region,
First isolation structure is extended downwardly from the first described sub-layer surface, and junction depth is 5 microns or more.
4. MEMS device according to claim 1, wherein the transistor is CMOS transistor or bipolar transistor.
5. MEMS device according to claim 4, wherein the well region of the transistor is formed in the MEMS sensor
In structure sheaf, the transistor further includes the source/drain region being formed in well region and the first gate stack being formed on well region.
6. MEMS device according to claim 5, wherein the transistor further includes the grid positioned at the first gate stack both sides
Pole side wall, and the silicide layer in first grid stack surface.
7. MEMS device according to claim 5, further includes：
Interlayer dielectric layer；
The opening formed in interlayer dielectric layer；And
The interconnection that the source/drain region and first gate stack are reached via opening is formed on interlayer dielectric layer.
8. MEMS device according to claim 1, wherein further include：
Passivation layer on the transistor, the internal structure for protecting the MEMS device.
9. MEMS device according to claim 1, further includes：
Second isolation structure, the active area for limiting the transistor,
Wherein, second isolation structure is the oxide layer formed using silicon location oxidation of silicon process.
10. MEMS device according to claim 1, further includes：
Third isolation structure, the active area for limiting the transistor,
Wherein, the third isolation structure is shallow trench isolation.
11. according to any MEMS device of claim 1-10, wherein the MEMS sensor is piezoresistive transducer.
12. MEMS device according to claim 11, further includes：
Multiple sensitive resistances, the doped region being respectively located in the epitaxial layer,
Wherein, the multiple sensitive resistance is located at the outside of the active area of the transistor.
13. MEMS device according to claim 12, further includes：
Multiple second gate stacks, are located on the multiple sensitive resistance,
Wherein, one of the multiple second gate stack one corresponding in the multiple sensitive resistance separately constitutes resistance member
Part, the temperature coefficient for improving varistor.
14. MEMS device according to claim 13, wherein the number of the multiple sensitive resistance is four, described
MEMS device further includes：Interconnection, for four sensitive resistances to be connected into Wheatstone bridge.
15. according to any MEMS device of claim 1-10, wherein the MEMS sensor is capacitance type sensor.
16. MEMS device according to claim 15, further includes：
Contact zone, the contact zone are the doped region in the epitaxial layer,
Wherein, the contact zone is located at the outside of the active area of the transistor.
17. MEMS device according to claim 1, wherein the thickness of the structure sheaf is 6 microns to 10 microns.
18. MEMS device according to claim 1, wherein the thickness of first seed layer is 10 microns to 50 microns.
19. MEMS device according to claim 5, wherein it is micro- that the well region from the surface of the structure sheaf extends downwardly 2
Rice is to 4 microns.
20. MEMS device according to claim 19, wherein the source/drain region is extended downwardly from the surface of the well region
0.5 micron to 2 microns.
21. a kind of manufacturing method of MEMS device, including：
MEMS sensor is formed on substrate, and the MEMS sensor includes cavity formed on a substrate and is located on cavity
Structure sheaf；And
Transistor is formed in MEMS sensor,
Wherein, at least part of the transistor is formed in the structure sheaf of the MEMS sensor,
The step of forming the MEMS sensor include：
The first seed layer is formed on substrate；
The cavity is formed in first seed layer and second of sublayer is formed on the cavity,
Wherein, the step of formation structure sheaf includes：
Epitaxial layer is formed on the surface of first seed layer and second of sublayer.
22. according to the method for claim 21, wherein the step of forming the MEMS sensor include：
The first seed layer is formed on substrate；
The first isolation structure is formed in first seed layer, first isolation structure is for limiting the MEMS sensor
Active region；
Electrochemical corrosion is carried out in the active region that first isolation structure limits, to the shape in first seed layer
At the first porous layer and the second porous layer adjacent to each other, first porous layer is located at the lower section of second porous layer, and
And the porosity of first porous layer is higher than second porous layer；
It anneals so that first porous layer is transformed into the cavity and second porous layer is transformed into second
Sublayer.
23. according to the method for claim 22, wherein the thickness of first porous layer is 5.5 to 6.5 microns, described
The thickness of second porous layer is 0.5 to 1.5 micron.
24. according to the method for claim 22, wherein the porosity of first porous layer is 70%-90%, described the
The porosity of two porous layers is 10%-40%.
25. according to the method for claim 22, wherein first seed layer is P-type silicon layer, first isolation structure
For N-doped zone.
26. according to the method for claim 22, wherein in electrochemical corrosion, the first seed layer connection power supply
Positive electrode, the negative electrode of the substrate connection power supply.
27. according to the method for claim 26, wherein in the electrochemical corrosion, first after-applied first electric current and the
Two electric currents, wherein the current density of first electric current is less than the current density of second electric current.
28. according to the method for claim 27, wherein the current density of first electric current is 20 to 50 milliamperes every square
Centimetre, the current density of the second electric current is 50 to 100 milliamperes every square centimeter.
29. according to the method for claim 27, wherein use acid solution in the electrochemical corrosion.
30. according to the method for claim 22, wherein the temperature of the annealing is higher than 1050 degrees Celsius.
31. according to the method for claim 22, wherein in the step of forming the first isolation structure and carry out electrochemical corrosion
The step of between, further include：
Hard mask is formed in first seed layer,
Wherein, the hard mask is aligned with first isolation structure, and together with first isolation structure described in restriction
The active region of MEMS sensor.
32. according to the method for claim 31, wherein the hard mask is silicon nitride layer.
33. according to the method for claim 21, wherein the thickness of the structure sheaf is 6 microns to 10 microns.
34. according to the method for claim 21, wherein the transistor is CMOS transistor or bipolar transistor.
35. according to the method for claim 34, wherein the well region of the transistor is formed in the knot of the MEMS sensor
In structure layer, the transistor further includes the source/drain region being formed in well region and the first gate stack being formed on well region.
36. according to the method for claim 35, after the step of forming transistor, further including：
Interlayer dielectric layer is formed on the transistor；
Opening is formed in interlayer dielectric layer；And
The interconnection that the source/drain region and first gate stack are reached via opening is formed on interlayer dielectric layer.
37. according to the method for claim 21, after the step of forming transistor, further including：
Passivation layer is formed on the transistor, the internal structure for protecting the MEMS device.
38. according to the method for claim 22, wherein the thickness of first seed layer is 10 microns to 50 microns.
39. according to the method for claim 35, wherein the well region extends downwardly 2 microns from the surface of the structure sheaf
To 4 microns.
40. according to the method for claim 36, wherein it is micro- that the source/drain region from the surface of the well region extends downwardly 0.5
Rice is to 2 microns.
41. the step of according to the method for claim 21, forming transistor further includes：
The second isolation structure is formed, the active area for limiting the transistor,
Wherein, second isolation structure is the oxide layer formed using silicon location oxidation of silicon process.
42. the step of according to the method for claim 21, forming transistor further includes：
Formation third isolation structure, the active area for limiting the transistor,
Wherein, the third isolation structure is shallow trench isolation.
43. according to any methods of claim 21-42, wherein the MEMS sensor is piezoresistive transducer.
44. the step of according to the method for claim 43, forming MEMS sensor further includes：
Multiple sensitive resistances are formed in the epitaxial layer,
Wherein, the multiple sensitive resistance is respectively multiple doped regions of the outside of the active area positioned at the transistor.
45. according to the method for claim 44, after the step of forming multiple sensitive resistances, further including：
Multiple second gate stacks are formed on the multiple sensitive resistance,
Wherein, one of the multiple second gate stack one corresponding in the multiple sensitive resistance separately constitutes resistance member
Part, the temperature coefficient for improving varistor.
46. according to the method for claim 45, wherein the number of the sensitive resistance is four, and the method further includes,
Interconnection is formed, four sensitive resistances are connected into Wheatstone bridge by the interconnection.
47. according to any methods of claim 21-42, wherein the MEMS sensor is capacitance type sensor.
48. according to the method for claim 47, further including：
Contact zone is formed in the epitaxial layer,
Wherein, the contact zone is the doped region of the outside of the active area positioned at the transistor.
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| CN109384195B (en) * | 2017-08-14 | 2020-08-14 | 无锡华润上华科技有限公司 | Cavity forming method based on deep groove corrosion |
| CN108117034B (en) | 2017-12-29 | 2023-12-26 | 杭州士兰集成电路有限公司 | MEMS component and manufacturing method thereof |
| CN109665488A (en) * | 2018-12-29 | 2019-04-23 | 杭州士兰集成电路有限公司 | MEMS device and its manufacturing method |
| CN110223916B (en) * | 2019-05-06 | 2022-03-08 | 瑞声科技(新加坡)有限公司 | Processing method of silicon wafer |
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