CN103151297A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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CN103151297A
CN103151297A CN 201110400124 CN201110400124A CN103151297A CN 103151297 A CN103151297 A CN 103151297A CN 201110400124 CN201110400124 CN 201110400124 CN 201110400124 A CN201110400124 A CN 201110400124A CN 103151297 A CN103151297 A CN 103151297A
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layer
dielectric layer
formed
low
forming
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CN 201110400124
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Chinese (zh)
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韩秋华
隋运奇
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中芯国际集成电路制造(上海)有限公司
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Abstract

The invention provides a manufacturing method of a semiconductor device. The manufacturing method includes that a semiconductor substrate is provided; a low k dielectric layer is formed on the semiconductor substrate and copper metal interconnecting wires are formed in the low k dielectric layer. The low k dielectric layer is schematized; the graphical low k dielectric layer is etched so that a flute is formed between the copper metal interconnection wires. A sacrificial metal layer is formed so as to fill the flute and the sacrificial metal layer is grinded until the low k dielectric layer is exposed. A covering layer is formed on the semiconductor substrate. The covering layer is etched; a hole is formed in the covering layer so that the sacrificial metal layer is exposed. The sacrificial metal layer is eliminated, and a groove is formed. An interlamination dielectric layer is formed, and the interlamination dielectric layer seals the groove so that air gaps are formed. According to the manufacturing method of the semiconductor device, the size of the air gaps is controllable so that the air gaps with the same size are formed between the formed copper metal interconnection structures so that the property of the device is improved.

Description

一种半导体器件的制造方法 A method of manufacturing a semiconductor device

技术领域 FIELD

[0001] 本发明涉及半导体制造工艺,具体而言涉及一种形成气隙的方法。 [0001] The present invention relates to semiconductor manufacturing processes, particularly relates to a method for forming an air gap.

背景技术 Background technique

[0002] 随着半导体器件特征尺寸的缩小,极大规模集成电路(VLSI)芯片的性能越来越受互连电容的制约。 [0002] With the shrinking feature sizes of semiconductor devices, (VLSI) chip performance large scale integrated circuits become increasingly constrained by the interconnect capacitance. 为了减小所述互连电容的影响以降低RC延迟和功耗,在低k介质层/铜金属互连工艺中集成一形成气隙的工艺是一种非常有效的解决办法。 To reduce the impact of the interconnect capacitance and RC delay to reduce power consumption, an integrated process of forming an air gap is a very effective solution in the low-k dielectric layer / Cu metal interconnect process.

[0003] 传统的形成气隙的工艺步骤包括:首先,如图1A所示,提供半导体衬底100,在所述半导体衬底100上自下而上形成有层间介质层101和低k介质层102,在所述低k介质层102中形成有第一铜金属互连结构103,其中,所述第一铜金属互连结构103的顶部形成有覆盖层104,所述第一铜金属互连结构103由铜金属层和包围所述铜金属层的阻挡层所构成;接着,如图1B所示,在所述半导体衬底100上形成一金属层105,以覆盖所述铜金属互连结构103,然后,采用一光致抗蚀剂106图形化所述金属层105 ;接着,如图1C所示,采用干法蚀刻工艺蚀刻所述经图形化的金属层105,以在所述铜金属互连结构103之间形成一凹槽107 ;接着,如图1D所示,在所述半导体衬底上形成一层间介质层108,所述层间介质层108在所述凹槽107内具有较低的覆盖范围,从而在所述铜金属互连结构之间形成一气隙10 [0003] The conventional process of forming an air gap step comprises: First, as shown in FIG. 1A, a semiconductor substrate 100, a bottom-up on the semiconductor substrate 100 is formed with a low-k dielectric 101 and the interlayer dielectric layer layer 102, a first copper metal interconnect structure 103 is formed in the low-k dielectric layer 102, wherein the copper top of the first metal interconnect structure 103 is formed with a coating layer 104, the first copper intermetallic the interconnection structure 103 is made of a metal layer of copper and a copper layer surrounding the barrier metal layer; Subsequently, as shown in FIG 1B a metal layer 105 is formed on the semiconductor substrate 100 to cover the copper interconnect metal structure 103, and then, using a photoresist pattern 106 of the metal layer 105; Next, as shown in FIG. 1C, the metal layer 105 using the dry etch process of etching the via pattern to the copper a recess 107 is formed between the metal interconnect structure 103; Next, as shown in FIG. 1D, an interlayer dielectric layer 108 is formed on the semiconductor substrate, the interlayer dielectric layer 108 in the recess 107 with lower coverage, so as to form an air gap 10 between the Cu metal interconnect structure 9 ;接着,如图1E所示,在所述层间介质层108中形成第二铜金属互连结构110。 9; Subsequently, as shown in FIG, a second copper interconnect structure 110 1E in the interlayer dielectric layer 108.

[0004] 采用上述工艺过程所形成的气隙的尺寸随着所形成的铜金属互连结构之间的间距的不同而变化,由此造成所述互连电容的不同,从而影响半导体器件的性能。 [0004] The size of the air gap formed by the process described above with different spacings between the Cu metal interconnect structure formed varies, thereby resulting in the different interconnect capacitance, thereby affecting the performance of the semiconductor device .

[0005] 因此,需要提出一种方法,以解决上述问题。 [0005] Therefore, a need for a method to solve the problem.

发明内容 SUMMARY

[0006] 针对现有技术的不足,本发明提供一种半导体器件的制造方法,包括:提供半导体衬底,在所述半导体衬底上形成低k介质层,且在所述低k介质层中形成铜金属互连线;图形化所述低k介质层,并蚀刻经图形化的所述低k介质层,以在所述铜金属互连线之间形成一沟槽;形成一牺牲金属层,以填充所述沟槽,并研磨所述牺牲金属层,直至露出所述低k介质层;在所述半导体衬底上形成一覆盖层;蚀刻所述覆盖层,通过在所述覆盖层中形成一孔洞以露出所述牺牲金属层;去除所述牺牲金属层,形成一凹槽;形成一层间介质层,将所述凹槽封住以形成一气隙。 [0006] for the deficiencies of the prior art, the present invention provides a method of manufacturing a semiconductor device, comprising: providing a semiconductor substrate, forming a low-k dielectric layer on the semiconductor substrate, and the low-k dielectric layer forming a copper interconnect metal; patterning said low-k dielectric layer, and etching through the patterned low-k dielectric layer to form a trench between the copper interconnect metal; forming a sacrificial metal layer to fill the trenches, and grinding the sacrificial metal layer until exposing said low-k dielectric layer; forming a cover layer on the semiconductor substrate; etching the cover layer, the cover layer by a hole is formed to expose the sacrificial metal layer; removing the sacrificial metal layer, forming a recess; inter-layer dielectric layer is formed, the recess is sealed to form an air gap.

[0007] 进一步,在形成所述牺牲金属层之前,还包括形成一阻挡层的工艺步骤。 [0007] Further, before forming the sacrificial metal layer, the process further comprising the step of forming a barrier layer.

[0008] 进一步,所述阻挡层的材料为氮化钛。 [0008] Further, the material of the barrier layer is titanium nitride.

[0009] 进一步,所述牺牲金属层的材料为钨。 [0009] Further, the material of the sacrificial metal layer is tungsten.

[0010] 进一步,所述覆盖层的材料为碳氮化硅或正硅酸乙酯。 [0010] Further, the material of the cover layer is a carbon nitride or TEOS.

[0011 ] 进一步,采用化学气相沉积工艺或旋涂工艺形成所述覆盖层。 [0011] Further, the cover layer by a chemical vapor deposition process or spin coating processes.

[0012] 进一步,采用干法蚀刻工艺蚀刻所述覆盖层。 [0012] Further, a dry etching process etching the capping layer.

[0013] 进一步,所述孔洞的直径小于lOOnm。 [0013] Further, the bore diameter of less than lOOnm. [0014] 进一步,采用湿法蚀刻工艺去除所述牺牲金属层。 [0014] Further, the wet etching process to remove the sacrificial metal layers.

[0015] 进一步,所述湿法蚀刻工艺的腐蚀液为双氧水。 [0015] Further, the wet etching process for the etching solution of hydrogen peroxide.

[0016] 进一步,采用化学气相沉积工艺形成所述层间介质层。 [0016] Further, a chemical vapor deposition process for forming the interlayer dielectric layer.

[0017] 进一步,所述层间介质层的材料为碳氧化硅。 [0017] Further, the material of the interlayer dielectric layer is a silicon oxycarbide.

[0018] 进一步,所述低k介质层的材料为碳氧化硅。 [0018] Further, the low-k dielectric layer material is silicon oxycarbide.

[0019] 根据本发明,可以控制所形成的气隙的尺寸,以在所形成的铜金属互连结构之间形成具有均一尺寸的气隙。 [0019] According to the present invention, it can control the size of the air gap being formed between the copper metal interconnect structure to be formed is formed in the gap having a uniform size.

附图说明 BRIEF DESCRIPTION

[0020] 本发明的下列附图在此作为本发明的一部分用于理解本发明。 [0020] The following figures of the present invention is used herein as part of the present invention to understand the invention. 附图中示出了本发明的实施例及其描述,用来解释本发明的原理。 In the embodiment shown and described embodiments of the present invention are shown, serve to explain the principles of the invention.

[0021] 附图中: [0021] In the drawings:

图1A-图1E为传统的形成气隙的工艺的各步骤的示意性剖面图; FIG. 1A- 1E is a schematic sectional view of the steps of the conventional process of forming an air gap;

图2A-图2F为本发明提出的形成气隙的方法的各步骤的示意性剖面图; FIGS. 2A- 2F FIG schematic sectional view of the forming steps of the method of the present invention proposed an air gap;

图3为本发明提出的形成气隙的方法的流程图。 3 is a flowchart of a method of forming an air gap of the proposed invention.

具体实施方式 Detailed ways

[0022] 在下文的描述中,给出了大量具体的细节以便提供对本发明更为彻底的理解。 [0022] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. 然而,对于本领域技术人员而言显而易见的是,本发明可以无需一个或多个这些细节而得以实施。 However, those skilled in the art will be apparent that the present invention may be practiced without one or more of these details are implemented. 在其他的例子中,为了避免与本发明发生混淆,对于本领域公知的一些技术特征未进行描述。 In other examples, in order to avoid confusion with the present invention, known in the art for some of the technical features are not described.

[0023] 为了彻底理解本发明,将在下列的描述中提出详细的步骤,以便阐释本发明提出的形成气隙的方法。 [0023] For a thorough understanding of the invention will be set forth in detail in the following in the description, to explain the method of forming an air gap provided by the invention. 显然,本发明的施行并不限定于半导体领域的技术人员所熟习的特殊细节。 Obviously, the purposes of the present invention is not limited to the specific details of the semiconductor skilled in the art are familiar with. 本发明的较佳实施例详细描述如下,然而除了这些详细描述外,本发明还可以具有其他实施方式。 As described in detail preferred embodiments of the present invention, however, in addition to the detailed description, the present invention also may have other embodiments.

[0024] 应当理解的是,当在本说明书中使用术语“包含”和/或“包括”时,其指明存在所述特征、整体、步骤、操作、元件和/或组件,但不排除存在或附加一个或多个其他特征、整体、步骤、操作、元件、组件和/或它们的组合。 [0024] It should be appreciated that, when used in the present specification "comprises" and / or "including" when that specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0025] 下面,参照图2A-图2F和图3来描述本发明提出的形成气隙的方法的详细步骤。 [0025] Next, a detailed procedure of FIG. 2A- 2F and FIG. 3 will be described a method of forming an air gap provided by the invention are shown.

[0026] 参照图2A-图2F,其中示出了本发明提出的形成气隙的方法的各步骤的示意性剖面图。 [0026] Referring to FIGS. 2A- FIG. 2F, which shows a schematic cross-sectional views of steps of a method of forming an air gap provided by the invention.

[0027] 首先,如图2A所示,提供半导体衬底200,所述半导体衬底200的构成材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)等。 [0027] First, as shown in FIG. 2A, a semiconductor substrate 200, the material constituting the semiconductor substrate 200 may employ undoped silicon, doped with impurities of silicon, silicon on insulator (SOI )Wait. 作为示例,在本实施例中,所述半导体衬底200选用单晶硅材料构成。 By way of example, in the present embodiment, the semiconductor substrate 200 composed of single crystal silicon material chosen. 在所述半导体衬底200中形成有隔离槽,埋层,以及各种阱(well)结构,为了简化,图示中予以省略。 Formed in the semiconductor substrate 200 with an isolation groove, buried layer, and various well (Well) structure, for simplicity, the illustration is omitted.

[0028] 在所述半导体衬底200上,形成有各种元件,为了简化,图示中予以省略,这里仅不出一低k介质层201。 [0028] On the semiconductor substrate 200, various elements are formed, for simplicity, the illustration is omitted, where not only a low-k dielectric layer 201. 在本实施例中,所述低k介质层201的材料为碳氧化娃(SiOC)。 In the present embodiment, the low-k dielectric material layer 201 is Wa oxycarbide (SiOC). 所述低k介质层201中形成有用于填充金属互连线的沟槽。 The low-k dielectric layer 201 is formed in a trench fill metal interconnection line. 沉积一金属层,例如铜金属层,于所述低k介质层201上,并填满所述低k介质层201中的沟槽。 Depositing a metal layer, a metal layer such as copper, on the low-k dielectric layer 201, and the low-k dielectric trench fill layer 201. 采用化学机械研磨工艺去除多余的铜金属层,研磨到所述低k介质层201的表面终止,在所述低k介质层201中形成铜金属互连线202。 Chemical mechanical polishing processes remove excess copper metal layer, the polishing surface to the low-k dielectric layer 201 is terminated, a copper metal interconnect lines 202 of the low-k dielectric layer 201.

[0029] 接着,如图2B所示,图形化所述低k介质层201,并蚀刻经图形化的所述低k介质层201,以在所述铜金属互连线202之间形成一沟槽203。 [0029] Next, as shown in FIG 2B the patterned low-k dielectric layer 201, and etching through the patterned low-k dielectric layer 201 to form a groove between the copper metal interconnect 202 groove 203. 采用干法蚀刻工艺实施所述蚀刻,所使用的蚀刻气体包括含氟气体(CF4、CHF3> CH2F2等)、稀释气体(He、N2等)以及氧气。 A dry etching process using the etching embodiments, the etching gas used include fluorine-containing gas (CF4, CHF3> CH2F2 and the like), a diluent gas (He, N2, etc.) and oxygen.

[0030] 接着,如图2C所示,在所述半导体衬底200上形成一牺牲金属层204,以填充所述沟槽203。 [0030] Next, as shown in FIG. 2C, a sacrificial metal layer 204 is formed on the semiconductor substrate 200 to fill the trench 203. 所述牺牲金属层204的材料为钨,形成所述牺牲金属层204的工艺可以采用化学气相沉积工艺或物理气相沉积工艺。 The material of the sacrificial metal layer 204 is tungsten, process of forming the sacrificial metal layer 204 is a chemical vapor deposition process or a physical vapor deposition process may be employed. 然后,采用化学机械研磨工艺研磨所述牺牲金属层204,直至露出所述低k介质层201。 Then, a chemical mechanical polishing process of polishing the sacrificial metal layer 204, until exposing said low-k dielectric layer 201. 在形成所述牺牲金属层204之前,还需要先形成一阻挡层以阻止所述牺牲金属层204向所述低k介质层201中的扩散。 Before forming the sacrificial metal layer 204, first need to form a barrier layer to prevent diffusion of the metal of the sacrificial layers 204 to 201 in the low-k dielectric layer. 所述阻挡层的材料通常为氮化钛(TiN),形成所述阻挡层的工艺可以采用原子层沉积工艺或物理气相沉积工艺。 Material of the barrier layer is typically titanium nitride (TiN), the process of forming the barrier layer is a physical vapor deposition process or an atomic layer deposition process may be employed.

[0031] 接下来,在所述半导体衬底200上形成一覆盖层205。 [0031] Next, a capping layer 205 is formed on the semiconductor substrate 200. 所述覆盖层205的材料为碳氮化硅(SiCN)或正硅酸乙酯(TEOS),形成所述覆盖层205的工艺可以采用化学气相沉积工艺或旋涂工艺。 Material layer 205 is covered with the silicon carbon nitride (the SiCN) or tetraethylorthosilicate (TEOS), the process of forming the cover layer 205 is a chemical vapor deposition process or spin coating process may be employed.

[0032] 接着,如图2D所示,采用干法蚀刻工艺蚀刻所述覆盖层205,通过在所述覆盖层205中形成一孔洞206以露出所述牺牲金属层204。 [0032] Next, as shown in FIG dry etching process etching the 2D cover layer 205, a hole is formed through the covering layer 205 206 to expose the sacrificial metal layer 204. 所述孔洞206相对于所述牺牲金属层204的位置清楚地显示在图2D的AA视图图2D'中。 The bore 206 relative to the position of the sacrificial metal layer 204 is clearly shown in the view AA of FIG. 2D 2D 'in. 所述孔洞206的直径小于lOOnm。 The diameter of the hole 206 is less than lOOnm.

[0033] 接着,如图2E所示,采用湿法蚀刻工艺去除所述牺牲金属层204,形成一凹槽207。 [0033] Next, as shown in FIG. 2E, a wet etching process to remove the sacrificial metal layer 204, a recess 207 is formed. 所述湿法蚀刻工艺的腐蚀液为双氧水(H2O2)。 The wet etching process the etching solution is hydrogen peroxide (H2O2).

[0034] 接着,如图2F所示,在所述半导体衬底200上形成一层间介质层208。 [0034] Next, as shown in Figure 2F, an interlayer dielectric layer 208 is formed on the semiconductor substrate 200. 采用化学气相沉积工艺形成所述层间介质层208。 A chemical vapor deposition process for forming the interlayer dielectric layer 208. 所述层间介质层208在所述凹槽207中具有较低的覆盖率,因此其可以将所述凹槽207封住以形成一气隙209。 The interlayer dielectric layer 208 having a lower cover 207 in the recess, so that the recess 207 may be sealed to form an air gap 209. 本实施例中,所述层间介质层208的材料为碳氧化硅(SiOC)。 In this embodiment, the interlayer dielectric layer 208 material is a silicon oxycarbide (SiOC).

[0035] 至此,完成了根据本发明示例性实施例的方法实施的全部工艺步骤,接下来,可以通过后续工艺完成整个半导体器件的制作,所述后续工艺与传统的半导体器件加工工艺完全相同。 [0035] This completes the process all the method steps according to an exemplary embodiment of the present invention embodiment, next, making the entire semiconductor device can be completed by a subsequent process, the subsequent process of a semiconductor device with a conventional process identical. 根据本发明,可以控制所形成的气隙的尺寸,以在所形成的铜金属互连结构之间形成具有均一尺寸的气隙,从而改善器件的性能。 According to the present invention, it can control the size of the air gap being formed between the copper metal interconnect structure to be formed is formed in the gap having a uniform size, thereby improving the performance of the device.

[0036] 参照图3,其中示出了本发明提出的形成气隙的方法的流程图,用于简要示出整个制造工艺的流程。 [0036] Referring to Figure 3, there is shown a flowchart of a method of forming an air gap by the present invention for schematically showing a manufacturing process of the whole process.

[0037] 在步骤301中,提供半导体衬底,在所述半导体衬底上形成低k介质层,且在所述低k介质层中形成铜金属互连线; [0037] In step 301, a semiconductor substrate, forming a low-k dielectric layer on the semiconductor substrate, and forming a copper metal interconnect lines in said low-k dielectric layer;

在步骤302中,图形化所述低k介质层,并蚀刻经图形化的所述低k介质层,以在所述铜金属互连线之间形成一沟槽; In step 302, the patterned low-k dielectric layer, and etching the low-k dielectric layer was patterned to form a trench between the copper interconnect metal;

在步骤303中,形成一牺牲金属层,以填充所述沟槽,并研磨所述牺牲金属层,直至露出所述低k介质层; In step 303, a sacrificial metal layer is formed to fill the trench, and grinding the sacrificial metal layer until exposing said low-k dielectric layer;

在步骤304中,在所述半导体衬底上形成一覆盖层; In step 304, a capping layer is formed on the semiconductor substrate;

在步骤305中,蚀刻所述覆盖层,通过在所述覆盖层中形成一孔洞以露出所述牺牲金 In step 305, etching the covering layer is formed by a hole in the cover layer to expose the sacrificial gold

属层; A metal layer;

在步骤306中,去除所述牺牲金属层,形成一凹槽; 在步骤307中,形成一层间介质层,将所述凹槽封住以形成一气隙。 In step 306, removing the sacrificial metal layer, forming a recess; in step 307, an interlayer dielectric layer is, the seal groove to form an air gap.

[0038] 本发明已经通过上述实施例进行了说明,但应当理解的是,上述实施例只是用于举例和说明的目的,而非意在将本发明限制于所描述的实施例范围内。 [0038] The present invention has been described by the above embodiments, it should be understood that the above examples are only for purposes of illustration and description, and are not intended to limit the invention within the scope of the described embodiments. 此外本领域技术人员可以理解的是,本发明并不局限于上述实施例,根据本发明的教导还可以做出更多种的变型和修改,这些变型和修改均落在本发明所要求保护的范围以内。 Moreover, those skilled in the art will be appreciated that the present invention is not limited to the above embodiment, in accordance with the teachings of the present invention may be made more of the variations and modifications, all such variations and modifications fall within the invention as claimed within the range. 本发明的保护范围由附属的权利要求书及其等效范围所界定。 The scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (13)

  1. 1.一种半导体器件的制造方法,包括: 提供半导体衬底,在所述半导体衬底上形成低k介质层,且在所述低k介质层中形成铜金属互连线; 图形化所述低k介质层,并蚀刻经图形化的所述低k介质层,以在所述铜金属互连线之间形成一沟槽; 形成一牺牲金属层,以填充所述沟槽,并研磨所述牺牲金属层,直至露出所述低k介质层; 在所述半导体衬底上形成一覆盖层; 蚀刻所述覆盖层,通过在所述覆盖层中形成一孔洞以露出所述牺牲金属层; 去除所述牺牲金属层,形成一凹槽; 形成一层间介质层,将所述凹槽封住以形成一气隙。 1. A method of manufacturing a semiconductor device, comprising: providing a semiconductor substrate, forming a low-k dielectric layer on the semiconductor substrate, and forming a copper metal interconnect lines in said low-k dielectric layer; patterning said the low-k dielectric layer and patterned by etching the low-k dielectric layer to form a trench between the copper interconnect metal; forming a sacrificial metal layer to fill the trench, and the grinding said sacrificial metal layer until the exposed low-k dielectric layer; forming a cover layer on the semiconductor substrate; etching the covering layer is formed by a hole in the cover layer to expose the sacrificial metal layer; removing the sacrificial metal layer, forming a recess; inter-layer dielectric layer is formed, the recess is sealed to form an air gap.
  2. 2.根据权利要求1所述的方法,其特征在于,在形成所述牺牲金属层之前,还包括形成一阻挡层的工艺步骤。 2. The method according to claim 1, characterized in that, before forming the sacrificial metal layer, the process further comprising the step of forming a barrier layer.
  3. 3.根据权利要求2所述的方法,其特征在于,所述阻挡层的材料为氮化钛。 3. The method according to claim 2, characterized in that the material of the barrier layer is titanium nitride.
  4. 4.根据权利要求1所述的方法,其特征在于,所述牺牲金属层的材料为钨。 4. The method according to claim 1, wherein said sacrificial material of the metal layer is tungsten.
  5. 5.根据权利要求1所述的方法,其特征在于,所述覆盖层的材料为碳氮化硅或正硅酸乙酯。 5. The method according to claim 1, characterized in that the material of the covering layer is a carbon nitride or TEOS.
  6. 6.根据权利要求1所述的方法,其特征在于,采用化学气相沉积工艺或旋涂工艺形成所述覆盖层。 6. The method according to claim 1, wherein the chemical vapor deposition process or spin-coating process of forming the cover layer.
  7. 7.根据权利要求1所述的方法,其特征在于,采用干法蚀刻工艺蚀刻所述覆盖层。 7. The method according to claim 1, wherein the dry etching process of etching the capping layer.
  8. 8.根据权利要求1所述的方法,其特征在于,所述孔洞的直径小于lOOnm。 8. The method according to claim 1, characterized in that the bore diameter of less than lOOnm.
  9. 9.根据权利要求1所述的方法,其特征在于,采用湿法蚀刻工艺去除所述牺牲金属层。 9. The method according to claim 1, wherein the wet etching process to remove the sacrificial metal layers.
  10. 10.根据权利要求9所述的方法,其特征在于,所述湿法蚀刻工艺的腐蚀液为双氧水。 10. The method according to claim 9, wherein said wet etching process is an etching solution of hydrogen peroxide.
  11. 11.根据权利要求1所述的方法,其特征在于,采用化学气相沉积工艺形成所述层间介质层。 11. The method according to claim 1, wherein the chemical vapor deposition process for forming the interlayer dielectric layer.
  12. 12.根据权利要求1或11所述的方法,其特征在于,所述层间介质层的材料为碳氧化硅。 12. The method of claim 1 or claim 11, characterized in that the material of the interlayer dielectric layer is silicon oxycarbide.
  13. 13.根据权利要求1所述的方法,其特征在于,所述低k介质层的材料为碳氧化硅。 13. The method according to claim 1, wherein said low-k dielectric material is a layer of silicon oxycarbide.
CN 201110400124 2011-12-06 2011-12-06 Manufacturing method of semiconductor device CN103151297A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005041273A2 (en) * 2003-10-15 2005-05-06 Infineon Technologies Ag Method for reducing parasitic couplings in circuits
CN102163592A (en) * 2010-02-18 2011-08-24 台湾积体电路制造股份有限公司 Semiconductor structure having an air-gap region and a method of manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005041273A2 (en) * 2003-10-15 2005-05-06 Infineon Technologies Ag Method for reducing parasitic couplings in circuits
CN102163592A (en) * 2010-02-18 2011-08-24 台湾积体电路制造股份有限公司 Semiconductor structure having an air-gap region and a method of manufacturing the same

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