CN102344114B

CN102344114B - Preparation method for deep trench isolation channel

Info

Publication number: CN102344114B
Application number: CN201110347244.3A
Authority: CN
Inventors: 李晓莹; 李光涛; 乔大勇; 任森; 张艳飞; 康宝鹏
Original assignee: Northwestern Polytechnical University
Current assignee: Northwestern Polytechnical University
Priority date: 2011-11-04
Filing date: 2011-11-04
Publication date: 2014-03-12
Anticipated expiration: 2031-11-04
Also published as: CN102344114A

Abstract

The invention discloses a preparation method for a deep trench isolation channel, aiming at the requirements of mechanical connection but electrical insulation in MEMS (Micro Electro Mechanical System) technology. The method comprises the following steps of: polishing a silicon wafer; photo-etching; performing DRIE (Deep Reactive Ion Etching) to form a deep channel 2, wherein the deep channel 2 has an inverted isosceles trapezoid shape, and an included angle theta between a side wall of the channel and vertical direction is greater than or equal to 1 degree and is less than or equal to 5 degrees; cleaning with oxygen; generating a silicon dioxide insulating layer 3 on the surface of the side wall of the deep channel 2 and the surface of the silicon wafer; and filling a polycrystalline silicon layer 4. The preparation method has the beneficial effects that: the silicon wafer is etched into the inverted trapezoidal deep trench isolation channel by using DRIE; Notching phenomenon in isotropic etching is avoided; and the filling of the bottom of the deep channel can be guaranteed. Since the deep channel has the inverted trapezoid shape, an open part is still larger than the middle part of the channel, and the situation of a gap caused by blockage of the open part is also avoided during deposition of polycrystalline silicon. Since the included angle between the side wall of an oblique channel and the vertical direction is smaller, insulating characteristic and mechanical strength of the isolation channel are not influenced, and packaging air-tightness and insulation requirement can be met.

Description

A kind of preparation method of deep trench isolation channel

Affiliated field:

The present invention relates generally to MEMS (micro electro mechanical system) (MEMS) and micro-processing technology.

Background technology:

In MEMS technique, but often there is the sight that needs mechanical connection electric insulation.The deep trench isolation channel that existing method is rectangle by section is realized, and it is silicon dioxide that described deep trench isolation channel is used both sides, and centre is that the sandwich material of polysilicon is filled.But, because etching ion in etching process can rebound from bottom surface, so cause the secondarily etched aperture efficiency groove mid portion that easily causes of oppose side wall little, checking by experiment, the deep trench isolation channel that this section is rectangle easily produces gap in preparation process.The preparation method of this deep trench isolation channel is widely used, on can the encapsulation for device, also can be for needing in the structure of mechanical connection and electric insulation, in most of Aero-Space MEMS (micro electro mechanical system) (MEMS) device, there is relevant application, as accelerometer, gyro, resonator, grating, torsion mirror, micro mirror etc.

The Zhu Yong of Peking University, Yan Guizhen, Wang Chengwei, the people such as Wang Yangyuan are published in the lithographic technique research > > of the paper < < high-aspect-ratio deep isolation trench on 7/8 phase < < micro-nano electronic technology > > in 2003, a kind of method that changes deep trouth shape has been proposed, the method becomes large by the opening of deep trouth, is beneficial to the filling of polysilicon.Detailed process is: first adopt the thick photoresist of approximately 3 μ m to do mask, lithographic definition goes out the wide isolation channel figure of 2 μ m, then utilize the method for DRIE to carry out deep etching to silicon chip, etching the degree of depth is the silicon groove of 85 μ m, next by RIE method, opening part is adjusted, to reach the object that opening is increased, carry out again thermal oxidation or chemical vapour deposition (CVD) (LPCVD) silicon dioxide, at trenched side-wall, form silicon dioxide insulating layer, the method backfill polycrystalline silicon medium of finally using LPCVD, forms final isolation structure.

Yet the deep trench isolation channel preparation method that the people such as Microelectronics, Peking University research institute Zhu Yong propose, checking by experiment, use RIE method to adjust opening part, because isolation channel is darker, the effect size of RIE on depth direction is less, only can improve the gap occurring in filling process, cannot fundamentally solve gap problem.And, this method also can cause new problem: after the method for utilizing DRIE is carried out deep etching to silicon chip, by the method for RIE, opening part is adjusted, the passivation layer that in RIE process, etching gas runs into sidewall can move to groove depth place, can cause water chestnut (Notching) phenomenon because isotropic etching occurs, thereby cause bottom to be filled, easily occur bottom cavitation.

Summary of the invention:

The object of the invention is: in order to solve LPCVD polysilicon in prior art, occur gap, produce the problems such as water chestnut phenomenon, the present invention proposes a kind of preparation method of new deep trench isolation channel.

Technical scheme of the present invention is: a kind of preparation method of deep trench isolation channel, comprises the steps:

Step 1: single-sided polishing silicon chip 1, remove the native oxide on silicon chip 1 surface;

Step 2: photoetching, forms graphical window;

Step 3:DRIE, forms deep trench 2, and described deep trench 2 is isosceles inverted trapezoidal, and groove sidewall and vertical direction angle theta meet 1 °≤θ≤5 °;

Step 4: oxygen cleans, removes the photoresist of deep trench 2 sidewall surfaces passivation layers and silicon chip surface;

Step 5: oxidation, generates silicon dioxide insulating layer 3 in deep trench 2 sidewall surfaces and silicon chip surface;

Step 6: at the interior filling polysilicon layer 4 of deep trench 2.

The invention has the beneficial effects as follows:

Directly with DRIE, silicon chip erosion is become to the deep trench isolation channel of inverted trapezoidal, do not need by the method for RIE, opening part to be adjusted again, and then avoided Notching phenomenon in isotropic etching, can guarantee can fill up bottom deep trench.

Although because etching ion can rebound from bottom surface, cause the secondarily etched of oppose side wall, but due to the inverted trapezoidal that is shaped as of deep trench, opening part is still large than groove mid portion, the situation that also there will not be opening part to block thereby gap in the process of deposit spathic silicon.

Because tipper sidewall and vertical direction angle are less, so do not affect insulation characterisitic and the mechanical strength of isolation channel, can meet packaging air tightness and insulating requirements.

Accompanying drawing explanation:

Fig. 1 is in the preparation method of the deep trench isolation channel that proposes of the present invention, the schematic diagram after step 1 completes;

Fig. 2 is in the preparation method of the deep trench isolation channel that proposes of the present invention, the schematic diagram after step 2 completes;

Fig. 3 is in the preparation method of the deep trench isolation channel that proposes of the present invention, the schematic diagram after step 3 completes;

Fig. 4 is in the preparation method of the deep trench isolation channel that proposes of the present invention, the schematic diagram after step 4 completes;

Fig. 5 is in the preparation method of the deep trench isolation channel that proposes of the present invention, the schematic diagram after step 5 completes;

Fig. 6 is in the preparation method of the deep trench isolation channel that proposes of the present invention, the schematic diagram after step 6 completes;

Fig. 7 is the schematic diagram that embodiment 1 resonator uses the deep trench isolation channel preparation method of the present invention's proposition;

Fig. 8 is that embodiment 2 reverses the schematic diagram that mirror is used the deep trench isolation channel preparation method of the present invention's proposition.

In figure:

1. silicon chip 2. deep trench 3. silicon dioxide insulating layer 4. polysilicon layer 5. photoresist 6.SOI basalis 7.SOI oxide layer 8. structure 9. resonator 10. glass 11.SOI device layer 12. torsional micro-mirror face 1 13. torsional micro-mirror faces 2

Embodiment:

Embodiment 1:

Consulting Fig. 7, is the encapsulation of a resonator in the present embodiment, and total comprises SOI basalis 6, SOI oxide layer 7, structure 8, resonator 9, glass 10 and SOI device layer 11.Because SOI device layer 11 and peripheral shell link together, shell is exposed to outside, can contact with human body or other conductive bodies, need to be on structure 8 making alive, if structure sheaf 8 and SOI device layer 11 are on-insulated, the electric property of resonator 9 can be affected, so must carry out electric insulation to it.Therefore, structure 8 and SOI device layer 11 need to carry out mechanical connection and electric insulation, can adopt the deep trench isolation channel preparation method that the present invention proposes to realize.

Consult Fig. 1-6, the preparation method of the deep trench isolation channel in this embodiment, comprises the steps:

Step 1: concentration 40% hydrofluoric acid that single-sided polishing substrate silicon chip 1 is 1: 5 by volume ratio and the mixed solution of water are removed the native oxide of silicon chip surface, and soak time 30s, then dries up with nitrogen;

Step 2: photoetching, the photoresist 5 of use is S1818, the time for exposure is 9s, forms graphical window;

Step 3:DRIE, forms deep trench 2, and described deep trench 2 is isosceles inverted trapezoidal, and tipper sidewall and vertical direction angle are 2 °, described tipper runs through structure 8, groove width 2.5 μ m, and etching and passivation hocket, each cycle etch period is 8s, and passivation time is 5s, substrate bias power 12W.

Step 4: oxygen cleans 10min, removes the photoresist of deep trench 2 sidewall surfaces passivation layers and silicon chip surface;

Step 5: dry method thermal oxidation, the reaction time is 75 minutes, in deep trench 2 sidewall surfaces and silicon chip surface, generates silicon dioxide insulating layer 3;

Step 6: at the interior filling polysilicon layer 4 of deep trench 2, sedimentation time 3 hours.

By above-mentioned 6 steps, the preparation of deep trench isolation channel completes, subsequently, with cmp method by surperficial polysilicon layer 4 jettisonings.With wet etching method, sheet glass is etched to a groove, adopt anode linkage technology by sheet glass etched surface and SOI device layer burnishing surface bonding, complete the encapsulation of pressure sensor in the present embodiment.

Embodiment 2:

Consult Fig. 8, the present embodiment is a torsional micro-mirror, in the test of torsional micro-mirror before, connecting the anchor point of minute surface and the fixed anchor point at minute surface two ends adds after voltage, the rotational stability of torsional micro-mirror is not high, in order further to improve the stability of torsional micro-mirror, need to carry out torsional micro-mirror is carried out to FEEDBACK CONTROL, the method adopting is by deep trench isolation channel, whole minute surface to be divided into two, be respectively and power up minute surface and be isolated minute surface, in order to guarantee the rotation of whole minute surface, deep trench need to be filled to layer of silicon dioxide insulating barrier and polysilicon and play mechanical connection effect.Powering up minute surface is connection activity broach, forms drive end, and be isolated minute surface connection activity broach equally with corresponding fixed fingers, form test lead with corresponding fixed fingers, after drive end making alive, power up minute surface and rotate, drive is immediately isolated minute surface and rotates simultaneously.Test lead extracts signal drive end is carried out to FEEDBACK CONTROL, thereby torsional micro-mirror is controlled further to strengthen its stability better.

Step 1: concentration 40% hydrofluoric acid that single-sided polishing substrate silicon chip 1 is 1: 5 by volume ratio and the mixed solution of water are removed the native oxide of silicon chip surface, and soak time 40s, then dries up with nitrogen;

Step 2: photoetching, the photoresist 5 of use is EP533, the time for exposure is 9s, forms graphical window;

Step 3:DRIE, forms deep trench 2, and described deep trench 2 is isosceles inverted trapezoidal, and tipper sidewall and vertical direction angle are 5 °, and described tipper runs through described torsion mirror on depth direction, groove width 3 μ m.

Step 4: oxygen cleans 15min, removes the photoresist of deep trench 2 sidewall surfaces passivation layers and silicon chip surface;

Step 5: dry method thermal oxidation, the reaction time is 80 minutes, in deep trench 2 sidewall surfaces and silicon chip surface, generates silicon dioxide insulating layer 3;

Step 6: at the interior filling polysilicon layer 4 of deep trench 2, sedimentation time 2.5 hours.

Claims

1. a preparation method for deep trench isolation channel, comprises the steps:

Step 1: single-sided polishing silicon chip (1), remove the native oxide on silicon chip (1) surface;

Step 2: photoetching, forms graphical window;

Step 3:DRIE, forms deep trench (2), and described deep trench (2) is isosceles inverted trapezoidal, and groove sidewall and vertical direction angle theta meet 1 °≤θ≤5 °;

Step 4: oxygen cleans, removes the photoresist of deep trench (2) sidewall surfaces passivation layer and silicon chip surface;

Step 5: oxidation, generates silicon dioxide insulating layer (3) in deep trench (2) sidewall surfaces and silicon chip surface;

Step 6: fill polysilicon layer (4) in deep trench (2).