CN102344114B - Preparation method for deep trench isolation channel - Google Patents

Abstract

Aiming at the requirement of mechanical connection but electrical insulation in MEMS technology, the invention discloses a preparation method of a deep trench isolation groove. The method steps: polishing silicon wafer; photolithography; DRIE to form a deep groove 2, the deep groove 2 is an isosceles inverted trapezoid, and the angle θ between the side wall of the groove and the vertical direction satisfies 1°≤θ≤5°; oxygen Cleaning; forming a silicon dioxide insulating layer 3 on the side wall surface of the deep trench 2 and the surface of the silicon wafer; filling the polysilicon layer 4. The beneficial effect of the present invention is: directly using DRIE to etch the silicon chip into an inverted trapezoidal deep trench isolation trench, avoiding the Notching phenomenon in isotropic etching, and ensuring that the bottom of the deep trench can be filled. Since the shape of the deep trench is an inverted trapezoid, the opening is still larger than the middle part of the trench, and the opening will not be blocked during the process of depositing polysilicon to cause gaps. Because the angle between the side wall of the inclined groove and the vertical direction is small, the insulation property and mechanical strength of the isolation groove are not affected, and the airtightness and insulation requirements of the package can be met.

Description

A kind of preparation method of deep trench isolation groove

Field:

The present invention generally relates to microelectromechanical systems (MEMS) and micromachining techniques.

Background technique:

In MEMS technology, there are often scenarios that require mechanical connection but electrical isolation. The existing method is realized by a deep trench isolation trench with a rectangular cross section, and the deep trench isolation trench is filled with a sandwich material with silicon dioxide on both sides and polysilicon in the middle. However, since the etching ions will bounce back from the bottom surface during the etching process, resulting in secondary etching of the sidewall, it is easy to cause the opening to be smaller than the middle part of the trench. Experimental verification shows that this cross-section is a rectangular deep trench isolation. Grooves are prone to gaps during preparation. The preparation method of this deep trench isolation groove is widely used, can be used in the encapsulation of device, also can be used in the structure that needs mechanical connection and electric insulation, all has relevant in most aerospace microelectromechanical system (MEMS) devices Applications such as accelerometers, gyroscopes, resonators, gratings, torsion mirrors, micromirrors, etc.

Zhu Yong, Yan Guizhen, Wang Chengwei, Wang Yangyuan and others from Peking University published the paper "Research on Etching Technology of High Aspect Ratio and Deep Isolation Trench" in the July/8th issue of "Micro-Nano Electronic Technology" in 2003. The groove shape method, which enlarges the opening of the deep groove to facilitate the filling of polysilicon. The specific process is as follows: first, use a photoresist with a thickness of about 3 μm as a mask, define a 2 μm wide isolation groove pattern by photolithography, and then use the DRIE method to etch a deep groove on a silicon wafer to etch a silicon wafer with a depth of 85 μm. Groove, then use the RIE method to adjust the opening to achieve the purpose of increasing the opening, and then perform thermal oxidation or chemical vapor deposition (LPCVD) silicon dioxide to form a silicon dioxide insulating layer on the side wall of the trench, and finally The polysilicon dielectric is backfilled by LPCVD to form the final isolation structure.

However, the preparation method of the deep trench isolation trench proposed by Zhu Yong from the Institute of Microelectronics of Peking University has been verified by experiments, that is, the RIE method is used to adjust the opening. Since the isolation trench is deep, the effect size of RIE in the depth direction Smaller, it can only improve the gaps that appear during the filling process, but cannot fundamentally solve the problem of gaps. Moreover, this method will also cause new problems: after using the method of DRIE to etch the deep groove of the silicon wafer, the method of RIE is used to adjust the opening, and the etching gas encounters the passivation of the side wall during the RIE process. The layer will move to the depth of the groove, which will cause the phenomenon of horseshoe (Notching) due to isotropic etching, which will cause the bottom to not be filled and prone to bottom voids.

Invention content:

The purpose of the present invention is: in order to solve the problems of gaps and horseshoe phenomenon in LPCVD polysilicon in the prior art, the present invention proposes a new method for preparing deep trench isolation grooves.

The technical solution of the present invention is: a method for preparing a deep trench isolation trench, comprising the following steps:

Step 1: Polishing the silicon wafer 1 on one side to remove the native oxide layer on the surface of the silicon wafer 1;

Step 2: Photolithography to form a patterned window;

Step 3: DRIE, forming a deep groove 2, the deep groove 2 is an isosceles inverted trapezoid, and the angle θ between the side wall of the groove and the vertical direction satisfies 1°≤θ≤5°;

Step 4: Oxygen cleaning to remove the passivation layer on the sidewall surface of the deep trench 2 and the photoresist on the surface of the silicon wafer;

Step 5: Oxidation, forming a silicon dioxide insulating layer 3 on the side wall surface of the deep trench 2 and the surface of the silicon wafer;

Step 6: Filling the deep trench 2 with the polysilicon layer 4 .

The beneficial effects of the present invention are:

Directly use DRIE to etch the silicon wafer into an inverted trapezoidal deep trench isolation trench, and do not need to use the RIE method to adjust the opening, thus avoiding the Notching phenomenon in isotropic etching and ensuring that the bottom of the deep trench can be filled Full.

Although the etching ions will bounce back from the bottom surface, resulting in secondary etching of the sidewall, but because the shape of the deep trench is an inverted trapezoid, the opening is still larger than the middle part of the trench, and it will not be damaged during the deposition of polysilicon. There is a situation where the opening is blocked and a gap is created.

Because the angle between the side wall of the inclined groove and the vertical direction is small, the insulation property and mechanical strength of the isolation groove are not affected, and the airtightness and insulation requirements of the package can be met.

Description of drawings:

Fig. 1 is in the preparation method of the deep trench isolation groove that the present invention proposes, the schematic diagram after step 1 is completed;

Fig. 2 is a schematic diagram after step 2 is completed in the preparation method of the deep trench isolation trench proposed by the present invention;

Fig. 3 is a schematic diagram after step 3 is completed in the preparation method of the deep trench isolation trench proposed by the present invention;

Fig. 4 is a schematic diagram after step 4 is completed in the preparation method of the deep trench isolation trench proposed by the present invention;

Fig. 5 is a schematic diagram after step 5 is completed in the method for preparing a deep trench isolation trench proposed by the present invention;

Fig. 6 is a schematic diagram after step 6 is completed in the method for preparing a deep trench isolation trench proposed by the present invention;

Fig. 7 is a schematic diagram of the resonator of embodiment 1 using the deep trench isolation trench preparation method proposed by the present invention;

FIG. 8 is a schematic diagram of the twisted mirror of Embodiment 2 using the deep trench isolation trench preparation method proposed by the present invention.

In the picture:

1. Silicon wafer 2. Deep trench 3. Silicon dioxide insulating layer 4. Polysilicon layer 5. Photoresist 6. SOI base layer 7. SOI oxide layer 8. Structure 9. Resonator 10. Glass 11. SOI device Layer 12. Micro-Twisted Mirror 1 13. Micro-Twisted Mirror 2

Detailed ways:

Example 1:

Referring to FIG. 7 , this embodiment is a package of a resonator, and the entire structure includes an SOI base layer 6 , an SOI oxide layer 7 , a structure 8 , a resonator 9 , glass 10 and an SOI device layer 11 . Since the SOI device layer 11 and the peripheral shell are connected together, the shell is exposed to the outside and will be in contact with the human body or other conductive objects, and a voltage needs to be applied to the structure 8. If the structure layer 8 and the SOI device layer 11 are not insulated , will affect the electrical performance of the resonator 9, so it must be electrically insulated. Therefore, the structural body 8 and the SOI device layer 11 need to be mechanically connected and electrically insulated, which can be realized by using the deep trench isolation trench preparation method proposed by the present invention.

Referring to Fig. 1-6, the preparation method of the deep trench isolation trench in this embodiment comprises the following steps:

Step 1: Polish the substrate silicon wafer 1 on one side, remove the original oxide layer on the surface of the silicon wafer with a mixed solution of 40% hydrofluoric acid and water with a volume ratio of 1:5, soak for 30 seconds, and then blow dry with nitrogen;

Step 2: photolithography, the photoresist 5 used is S1818, and the exposure time is 9s to form a patterned window;

Step 3: DRIE, forming a deep groove 2, the deep groove 2 is an isosceles inverted trapezoid, the angle between the side wall of the inclined groove and the vertical direction is 2°, the inclined groove runs through the structure 8, and the groove width is 2.5 μm , etching and passivation are carried out alternately, the etching time of each cycle is 8s, the passivation time is 5s, and the bias power is 12W.

Step 4: Oxygen cleaning for 10 minutes to remove the passivation layer on the side wall surface of the deep trench 2 and the photoresist on the surface of the silicon wafer;

Step 5: dry thermal oxidation, the reaction time is 75 minutes, and a silicon dioxide insulating layer 3 is formed on the side wall surface of the deep trench 2 and the surface of the silicon wafer;

Step 6: Filling the deep trench 2 with a polysilicon layer 4 for a deposition time of 3 hours.

Through the above six steps, the preparation of the deep trench isolation trenches is completed, and then the polysilicon layer 4 on the surface is removed by chemical mechanical polishing. A groove is etched out of the glass sheet by wet etching, and the etched surface of the glass sheet is bonded to the polished surface of the SOI device layer by anodic bonding technology to complete the packaging of the pressure sensor in this embodiment.

Example 2:

Referring to Fig. 8, this embodiment is a micro-torsion mirror. In the previous test of the micro-torsion mirror, after the anchor point connecting the mirror surface and the fixed anchor points at both ends of the mirror surface were applied with voltage, the rotation stability of the micro-torsion mirror was not high. To further improve the stability of the micro-torsion mirror, it is necessary to carry out feedback control on the micro-torsion mirror. The method adopted is to divide the entire mirror into two parts through a deep trench isolation groove, which are respectively the powered mirror and the isolated mirror. In order to ensure that the entire The rotation of the mirror needs to fill the deep trench with a layer of silicon dioxide insulating layer and polysilicon for mechanical connection. The energized mirror is connected to the movable comb and forms the drive end with the corresponding fixed comb, while the isolated mirror is also connected to the movable comb and forms the test end with the corresponding fixed comb. After applying voltage to the drive end, the energized mirror Rotate, then drive the isolated mirror to rotate at the same time. The test end extracts the signal to perform feedback control on the drive end, so as to better control the micro-torsion mirror and further enhance its stability.

Referring to Fig. 1-6, the preparation method of the deep trench isolation trench in this embodiment comprises the following steps:

Step 1: Polish the substrate silicon wafer 1 on one side, remove the original oxide layer on the surface of the silicon wafer with a mixed solution of 40% hydrofluoric acid and water with a volume ratio of 1:5, soak for 40 seconds, and then blow dry with nitrogen;

Step 2: photolithography, the photoresist 5 used is EP533, and the exposure time is 9s to form a patterned window;

Step 3: DRIE, forming a deep groove 2, the deep groove 2 is an isosceles inverted trapezoid, the angle between the side wall of the inclined groove and the vertical direction is 5°, and the inclined groove runs through the twisted mirror in the depth direction , groove width 3μm.

Step 4: Oxygen cleaning for 15 minutes to remove the passivation layer on the side wall surface of the deep trench 2 and the photoresist on the surface of the silicon wafer;

Step 5: dry thermal oxidation, the reaction time is 80 minutes, and a silicon dioxide insulating layer 3 is formed on the side wall surface of the deep trench 2 and the surface of the silicon wafer;

Step 6: Fill the deep trench 2 with the polysilicon layer 4, and the deposition time is 2.5 hours.

Claims (1)

1. A method for preparing a deep trench isolation trench, comprising the steps of: Step 1: Polishing the silicon wafer (1) on one side to remove the native oxide layer on the surface of the silicon wafer (1); Step 2: Photolithography to form a patterned window; Step 3: DRIE, forming a deep groove (2), the deep groove (2) is an isosceles inverted trapezoid, and the angle θ between the groove side wall and the vertical direction satisfies 1°≤θ≤5°; Step 4: Oxygen cleaning to remove the passivation layer on the sidewall surface of the deep trench (2) and the photoresist on the surface of the silicon wafer; Step 5: Oxidation, forming a silicon dioxide insulating layer (3) on the side wall surface of the deep trench (2) and the surface of the silicon wafer; Step 6: Filling the deep trench (2) with a polysilicon layer (4).

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