CN1604302A

CN1604302A - Method for controlling super deep isolation trench opening shape and product

Info

Publication number: CN1604302A
Application number: CN 200410090620
Authority: CN
Inventors: 朱泳; 闫桂珍; 范杰; 王成伟; 王阳元
Original assignee: Peking University
Current assignee: Peking University
Priority date: 2004-11-09
Filing date: 2004-11-09
Publication date: 2005-04-06
Anticipated expiration: 2024-11-09
Also published as: CN1303666C

Abstract

This invention discloses a ultra-deep isolation flute opening shape control method and product of silicon integration MEMS technique, which has the technique project: first to form a SiO#-[2] sacrifice layer on the silicon surface; second to etch and define flute image and SiO#-[2] sacrifice layer; third to grow the Poly-silicon sacrifice layer; fourth to etch flute shape and Poly-silicon sacrifice layer and Si underlay to form deep flute; fifth to eliminate Poly-silicon and SiO#-[2] sacrifice layer; sixth to fill the deep flute with medium.

Description

A kind of control method of super deep isolation trench opening shape and product

Technical field

The present invention relates to microelectromechanical systems (MEMS) manufacture field, particularly about a kind of in body silicon integrated MEMS technology the control method and the product of super deep isolation trench opening shape.

Background technology

Microelectromechanical systems is a new and high technology of high speed development in recent years, adopt advanced semiconductor process techniques, whole mechanical structure is finished in chip piece, on volume, weight, price and power consumption, obvious advantages is arranged, obtained extensive use in Aero-Space, military affairs, biomedicine, automobile and other industries.

In MEMS designs and manufacturing technology, utilize the body silicon process technology to produce bigger mass and very high structure depth-to-width ratio, increased the sensitivity of transducer, but, the precision of MEMS transducer and the raising of reliability have therefore been limited owing to be difficult in processing and the interconnection that realizes body silicon MEMS structure and circuit part on the chip piece.Solving body silicon MEMS structure and the single chip integrated important channel of IC is the super deep isolation trench structure (dark 10～200 microns) that produces high-aspect-ratio, but the deep trouth 5 that etches with standard deep reaction ion etching (DRIE) technology, the middle part of aperture efficiency groove is little, can the mechanical strength of isolation channel and the reliability of body silicon integrated MEMS device have been reduced producing cavity 10 (shown in Fig. 1 a, Fig. 1 b, Fig. 1 c) in the isolation channel after the filling.The people such as W.A.Clark in California, USA university Berkeley branch school adopt joint shape isolation channel, the cavity at isolation channel middle part is filled from side direction, but this method can be introduced bigger cavity at the two ends of isolation channel simultaneously, increased difficulty (the W A.Clark of subsequent technique, T.N.Juneau andA.W Roessig, U.S.patent 6291875, Sep.18,2001).If can improve the deep trouth opening shape, make when filling and do not produce the cavity, can significantly improve the reliability and stability of transducer, will bring more wide prospect to the MEMS sensor application.

Summary of the invention

The control method and the product that the purpose of this invention is to provide a kind of super deep isolation trench opening shape, the inventive method can solve effectively in the super deep isolation trench preparation and fill inadequate problem, avoid the generation in cavity, increased the mechanical strength and the reliability of isolation channel.

Technical scheme of the present invention is as follows: a kind of control method of super deep isolation trench opening shape, it is characterized in that: at the polysilicon of 1～6 micron of silicon chip surface deposit as sacrifice layer, carry out deep etching again, after the etching sacrifice polysilicon layer is removed, fill with medium at last.

Concrete operations of the present invention may further comprise the steps:

1, forms SiO at silicon chip surface ₂Layer;

2, the SiO in the lithographic definition groove figure, BOE (buffer oxide etching agent) etching tank shape ₂Layer, a small amount of side direction undercutting;

3, growth Poly-silicon (polysilicon) sacrifice layer;

4, lithographic definition groove shape, DRIE etching Poly-silicon sacrifice layer and Si substrate form deep trouth;

5, remove Poly-silicon and SiO ₂Sacrifice layer;

6, with medium deep trouth is filled.

Described isolation channel determines that according to MEMS device architecture needs the silicon groove depth is 10～200 microns.

Described SiO as sacrifice layer ₂Adopt the preparation of high-temperature oxydation or LPCVD (low-pressure chemical vapor phase deposition) method, its thickness is 0.1～1 micron.

Described BOE corrosion SiO ₂The a small amount of side direction undercutting of sacrifice layer length is 0.5～1.5 micron.

Described polysilicon as sacrifice layer adopts the preparation of LPCVD method, and its thickness is 1～6 micron.

Described isolation channel adopts lithographic definition to go out the isolation channel figure, etches silicon trench with DRIE.

Described removal Poly-silicon adopts the DRIE method, removes SiO ₂Adopt BOE or RIE (reactive ion etching) method.

Described filling dielectric comprises polysilicon, the SiO of LPCVD growth ₂And Si ₃N ₄, and spacer medium such as other electricity, heat.

The chip that the control method of the above-mentioned super deep isolation trench opening shape of a kind of usefulness is made, the insulation isolation channel degree of depth on the chip is 10～200 microns, its inner space all is full of dielectric, does not have the cavity to occur.

The present invention is owing to take above technical scheme, it has the following advantages: 1, the inventive method since at first at the polysilicon of 1～6 micron of silicon chip surface deposit as sacrifice layer, after finishing, deep etching again the sacrifice polysilicon layer is removed, make deep trouth after the etching have the notch of broad, slot thereby solved with usual way effectively, the middle part of aperture efficiency groove is little, can produce the problem in cavity after the filling in isolation channel, has improved the reliability and stability of body silicon integrated MEMS transducer.2, the present invention utilizes deep etching and deep trouth LPCVD filling technique to produce the isolation deep groove structure of high-aspect-ratio, can realize the electric insulation of body silicon structure part and circuit part, the CMOS technology of combined standard, the technology of having finished integrated circuit and body silicon MEMS is integrated.3, the chip product of making of the inventive method is owing to avoided empty generation, therefore can produce structure capacitive than high-aspect-ratio with higher mechanical strength, realized the integrated of bulk silicon micro mechanic and cmos circuit simultaneously, significantly improve the precision and the stability of MEMS transducer, the present invention has frontier nature and important practical is worth.Technology of the present invention is simple, and good reproducibility is applicable in 10～200 microns deep etchings the finishing to opening.The present invention not only can be used for the electric isolation of body silicon integrated technology, but also can be used for other isolation such as calorifics of bulk silicon micro mechanic technology.

Description of drawings

Fig. 1 a is the super deep isolation trench schematic diagram that has the cavity of conventional method preparation

Fig. 1 b and Fig. 1 c are the super deep isolation trench electron microscope picture that has the cavity of conventional method preparation

Fig. 2 a～Fig. 2 d is embodiment 1 schematic diagram of polysilicon as sacrifice layer control opening shape

Fig. 3 a～Fig. 3 d is embodiment 2 schematic diagrames of polysilicon as sacrifice layer control opening shape

Fig. 4 a is the super deep isolation trench schematic diagram that does not have the cavity of the inventive method preparation

Fig. 4 b and Fig. 4 c are the super deep isolation trench scanning electron microscope diagram that does not have the cavity of the inventive method preparation

Embodiment:

Embodiment 1

Original material: twin polishing N type silicon chip, resistivity 5～8 Ω-cm,＜100〉crystal orientation, 400 microns of silicon wafer thicknesses.

1, the silicon chip 1 surface SiO of LPCVD deposit 1000 ₂Sacrifice layer 2 (shown in Fig. 2 a);

2, lithographic definition goes out isolation channel figure 3,2～3 microns of groove widths;

3, BOE corrosion SiO ₂Sacrifice layer 2, about 1 micron of side direction undercutting;

4, remove photoresist;

5, the Poly-silicon sacrifice layer 4 (shown in Fig. 2 b) of 4 microns of LPCVD deposits;

6, lithographic definition goes out isolation channel figure 3,2～3 microns of groove widths; Use DRIE etch silicon groove 5 again, dark 80 microns (determining the silicon groove depth), (shown in Fig. 2 c) according to MEMS device architecture needs;

7, remove photoresist;

8, with DRIE etching surface sacrifice polysilicon layer 4, expose SiO to the open air ₂Sacrifice layer 2;

9, BOE corrosion SiO ₂Sacrifice layer 2 exposes silicon chip 1 surface to the open air;

10, the thick SiO of LPCVD deposit 5000 ₂, insulating effect electrifies;

11, the polysilicon 6 of LPCVD deposit 2～2.5 micron thickness is filled silicon groove 5 (shown in Fig. 2 d);

Embodiment 2

Original material: twin polishing N type silicon chip 1, resistivity 5～8 Ω-cm,＜100〉crystal orientation, silicon chip 1 thickness is 400 microns.

1, the surface SiO of LPCVD deposit 1000 ₂ Sacrifice layer 2;

2, the Poly-silicon sacrifice layer 4 of 4 microns of LPCVD deposits;

3, lithographic definition goes out isolation channel figure 3,2～3 microns of groove widths (shown in Fig. 3 a); Use DRIE etch polysilicon groove again, 4 microns of groove depths expose SiO to the open air ₂Sacrifice layer 2;

4, BOE corrosion SiO ₂Sacrifice layer 2, about 1 micron of side direction undercutting (shown in Fig. 3 b);

5, continue etch silicon groove 5 with DRIE, dark 100 microns, (shown in Fig. 3 c) can determine silicon groove 5 degree of depth according to MEMS device architecture needs;

6, remove photoresist;

7, with DRIE etching surface sacrifice polysilicon layer 4, expose SiO to the open air ₂Sacrifice layer 2;

8, BOE corrosion SiO ₂Sacrifice layer 1 exposes silicon chip 1 surface to the open air;

9, the thick SiO of LPCVD deposit 5000 ₂(insulating effect electrifies);

10, the polysilicon 6 of LPCVD deposit 2～2.5 micron thickness is filled silicon groove 5 (shown in Fig. 3 d).

In the various embodiments described above, filled media can also be Si ₃N ₄, and spacer medium such as other electricity, heat.

With the chip product that said method is made, its insulation isolation channel degree of depth can be 10～200 microns, and is full of dielectric in the isolation channel, does not have the cavity to occur.

Claims

1, a kind of control method of super deep isolation trench opening shape, it is characterized in that: at first at the polysilicon of 1～6 micron of silicon chip surface deposit as sacrifice layer, carry out deep etching again, after the etching sacrifice polysilicon layer is removed, fill the good deep trouth of etching with medium at last.

2, the control method of a kind of super deep isolation trench opening shape according to claim 1 is characterized in that it may further comprise the steps:

(1) forms SiO at silicon chip surface ₂Sacrifice layer;

(2) SiO in the lithographic definition groove shape, BOE etching tank shape ₂Sacrifice layer, a small amount of side direction undercutting;

(3) growth Poly-silicon sacrifice layer:

(4) lithographic definition groove shape, DRIE etching Poly-silicon sacrifice layer and silicon substrate form deep trouth;

(5) remove Poly-silicon and SiO ₂Sacrifice layer;

(6) with medium deep trouth is filled.

3, the control method of a kind of super deep isolation trench opening shape according to claim 2 is characterized in that: 10～200 microns of the described isolation channel degree of depth.

4, the control method of a kind of super deep isolation trench opening shape according to claim 2 is characterized in that: described SiO as sacrifice layer ₂The preparation of employing high-temperature oxidation method, its thickness is 0.1～1 micron.

5, the control method of a kind of super deep isolation trench opening shape according to claim 2 is characterized in that: described SiO as sacrifice layer ₂Adopt the preparation of LPCVD method, its thickness is 0.1～1 micron.

6, the control method of a kind of super deep isolation trench opening shape according to claim 2 is characterized in that: described BOE corrosion SiO ₂0.5～1.5 micron of a small amount of side direction undercutting of sacrifice layer length.

7, the control method of a kind of super deep isolation trench opening shape according to claim 2 is characterized in that: described polysilicon as sacrifice layer adopts the preparation of LPCVD method, 1～6 micron of its thickness.

8, the control method of a kind of super deep isolation trench opening shape according to claim 2 is characterized in that: described removal Poly-silicon adopts the DRIE method, removes SiO ₂Adopt a kind of method among BOE and the RIE.

9, the control method of a kind of super deep isolation trench opening shape according to claim 2 is characterized in that: described filling dielectric comprises polysilicon, the SiO of LPCVD growth ₂And Si ₃N ₄

10, a kind of chip of making of the control method of claim 1～9 super deep isolation trench opening shape, it is characterized in that: the degree of depth of the insulation isolation channel on the chip is 10～200 microns, and its inner space all is full of dielectric.