CN1256759C - 低阻t－栅极mosfet器件及其制造方法 - Google Patents
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Abstract
本发明提供制备不出现任何多晶硅耗尽问题的低阻、亚-0.1μm沟道T-栅极MOSFET的方法。该方法利用镶嵌-栅极工艺步骤和化学氧化物去除刻蚀来制备这种MOSFET。化学氧化物去除可在含HF和NH3的蒸汽或含HF和NH3的等离子体中进行。
Description
技术领域
本发明涉及半导体器件，更特别涉及低阻、镶嵌T-栅极金属氧化物半导体场效应晶体管(MOSFET)器件。本发明也涉及使用镶嵌-栅极工艺及新型氧化物去除刻蚀来制造低阻、镶嵌T-栅极MOSFET的方法。
背景技术
过去二十五年左右中，VLSI(超大规模集成)的主要挑战是高产量和高可靠性的集成不断增加的MOSFET器件数目。这主要通过等比例缩小MOSFET栅极/沟道长度，减小栅极电介质厚度和增加沟道掺杂浓度来实现。
传统互补金属氧化物半导体(CMOS)工艺中，MOSFET的源极，漏极和栅极区域被注入，激活退火，然后形成硅化物来在衬底上产生低阻结区和具有低薄层电阻的多晶硅-栅极(poly-gate)线条。对高性能0.1μmCMOS器件，让多晶硅-栅极(poly-gate)形成硅化物的传统工艺导致下列问题：对宽度为0.25μm或更小的多晶硅-栅极(poly-gate)，硅化多晶硅即TiSi的晶核有限生长导致很高的薄层电阻，使器件性能降低。
根据上述关于高性能亚-0.1μmCMOS器件的传统CMOS工艺的缺点，仍需要研制能制备无高薄层电阻多晶硅的高性能亚-0.1μmCMOS器件的新型改进方法。也需要避免邻近栅极电介质的栅极区域内多晶硅耗尽(poly depletion)的方法。
发明内容
本发明提供了制备具有很低薄层电阻多晶硅-栅极(poly-gate)的亚-0.1μm沟道长度CMOS器件的方法。另外，本发明的方法能制备这样的亚-0.1μmCMOS器件，即在邻近栅极电介质的栅极区域内它未出现任何载流子的大量损失。即本发明的方法提供了未出现任何多晶硅耗尽(poly depletion)的亚-0.1μmCMOS器件。本发明的另一优点为本发明的方法能形成减小了栅极电阻的亚-0.1μmCMOS器件而不增加器件面积。
提供前述亚-0.1μmCMOS器件的本发明的方法利用了镶嵌-栅极工艺步骤和气相或等离子体相化学氧化物去除(COR)刻蚀。特别的是，本发明的方法包含步骤：
形成由含Si衬底，位于所述含Si衬底表面上的牺牲氧化物层，位于一部分所述牺牲氧化物层上的图形化多晶硅区域和毗邻所述图形化多晶硅区域的介电材料组成的平面结构；
去除所述图形化多晶硅区域来提供暴露一部分所述牺牲氧化物层的开口，注入离子至含Si衬底来形成器件沟道/体注入区，所述器件沟道/体注入区的长度小于0.1μm；
在所述介电材料的暴露的垂直侧壁上形成Si间隔件；
利用化学氧化去除刻蚀来暴露所述含Si衬底来去除牺牲氧化物层的所述暴露部分。
在所述含Si衬底的暴露表面形成栅极电介质并氧化所述Si间隔件；
在所述栅极电介质中形成凹入多晶硅-栅极(poly-gate)区域，所述凹入多晶硅-栅极(poly-gate)在其上表面有氧化层；
横向刻蚀所述氧化的Si间隔件和上述凹入多晶硅-栅极(poly-gate)的部分所述介电材料来提供比所述凹入多晶硅-栅极(poly-gate)宽的区域；
在所述区域形成栅极导体并去除残余介电材料；以及
在所述栅极导体下所述凹入多晶硅-栅极(poly-gate)的暴露的垂直侧壁上形成氮化物间隔件。
本发明也涉及利用上述方法形成的低阻T-栅极MOSFET器件。特别的是，本发明的低阻T-栅极MOSFET器件包括：
含Si衬底，它至少包括一分离漏极区域和源极区域的器件沟道/体注入区，所述至少一个器件沟道/体注入区长度小于约0.1μm；
至少位于所述器件沟道/体注入区，所述源极区域和所述漏极区域上面的栅极电介质；
位于一部分所述栅极电介质上面的T-栅极，所述T-栅极包括凹入底多晶硅区域和上栅极导体区域，所述上栅极导体区域的宽度比所述底多晶硅区域的宽度大。
位于所述底多晶硅区域的暴露的垂直侧壁上的氮化物间隔件，所述氮化物间隔件具有与上栅极导体区域的外缘对准的外缘。
附图说明
图1-13为描述本发明的基本工艺步骤的图示(通过截面图描述)。注意本发明的附图未根据比例尺描绘。
具体实施方式
本发明提供了制备低阻T-栅极MOSFET器件的方法，现在将参考本发明的附图更详细描述。
图1显示了本发明中采用的最初结构。特别的是，图1显示的最初结构包括具有形成其上的隔离区域12的含Si衬底10和位于含Si衬底10上的压点氧化层(pad oxide layer)14。本申请中术语“含Si”被用来指包含硅的材料。这种含Si衬底的例子包括，但不限于：Si，SiGe，SiGeC，SiC，Si/Si，Si/SiC，Si/SiGeC和绝缘体上硅(SOI)，在SOI中衬底10为SOI衬底的顶层含硅层。SOI衬底的情形中，SOI衬底将包括顶层含硅层下用于从底含Si层电隔离顶含硅层的埋层氧化物区域。衬底可根据所制备器件的类型，掺杂(n-或p-型)或不掺杂。
使用传统热生长工艺，压点氧化层14被形成于含硅衬底10上，或者，压点氧化层14能用传统淀积工艺形成，例如但不限于：化学气相淀积(CVD)，等离子体辅助CVD，溅射，蒸发和其它类似淀积工艺。压点氧化层14的厚度可调，但通常压点氧化层14的厚度为约5至约20nm。
在含Si衬底10表面上形成压点氧化层14后，隔离区域12被形成。隔离区域可为沟槽隔离区域，如图示，或LOCOS隔离区域。利用硅工艺的传统局部氧化形成LOCOS隔离区域，而沟槽隔离区域由光刻，刻蚀和淀积形成。特别的是，沟槽隔离区域通过先在压点氧化层上形成硬掩膜(未图示)，然后在硬掩膜上形成抗蚀剂来形成。然后抗蚀剂由传统光刻图形化，它包括步骤：曝光抗蚀剂为辐射图形，用传统的抗蚀剂显影仪显影抗蚀剂。通常为沟槽形状的图形通过刻蚀被转移到硬掩膜上。刻蚀步骤包括如反应离子刻蚀(RIE)，离子束刻蚀，等离子体刻蚀或激光切割的传统干刻步骤。图形被转移到硬掩膜上后，通常利用传统抗蚀剂剥离工艺去除抗蚀剂。
然后留下来的图形化硬掩膜被用来通过刻蚀压点氧化层14和部分衬底10转移沟槽图形至衬底上。注意SOI衬底的情形中，沟槽可通过顶部含Si层被部分刻蚀或可通过顶部含Si层被完全刻蚀至下面的埋层氧化层的上表面。本发明的方法在这里使用的刻蚀可与上述刻蚀步骤相同或不同。
沟槽被刻蚀后，可选的衬垫(未示出)可利用传统淀积工艺或本领域熟知的热生长技术被形成于含硅衬底10的裸露表面上。注意可选衬垫将形成于沟槽侧壁上和沟槽底壁。然后带或不带衬垫的沟槽被诸如四乙基正硅酸盐(TEOS)，SiO2或可流动氧化物的沟槽介电材料所填充。填充步骤包括如CVD的传统淀积工艺。某些实施方案中，例如使用TEOS时，在平坦化前可选用增浓步骤。
沟槽填充后，此结构经历终止于硬掩膜上表面顶部的传统平坦化工艺。然后硬掩膜通过刻蚀去除来提供如图1所示结构；去除硬掩膜时未与压点氧化层14共面的某些介电填充材料被去除。注意本发明的附图仅描述含硅衬底的一个区域，该区域中MOSFET器件将随后形成。衬底的其它区域可包括附加的MOSFET器件，或通常CMOS技术中存在的其它器件。
利用刻蚀工艺从此结构去除压点氧化层14，与Si或沟槽填充材料相比此工艺高选择性去除氧化物，其后牺牲氧化层16被形成于含硅衬底10的裸露表面来提供如图2所示的结构。牺牲氧化层16可利用形成压点氧化层使用的各种工艺之一来形成。牺牲氧化层的厚度可调，但通常牺牲氧化层厚度为约3至约15nm。
接着，图形化的多晶硅区域18在本发明方法中用作伪栅极区域，被形成于一部分牺牲氧化层顶上。图形化的多晶硅区域用覆盖淀积多晶硅至图2所示的结构上来形成，然后通过光刻和刻蚀来图形化多晶硅。图形化多晶硅区域的宽度决定所得MOSFET器件的沟长。
然后源/漏扩展注入20和未示出的可选边缘注入(haloimplant)利用传统源/漏扩展注入和传统边缘注入被形成至衬底中。各注入区域可利用相同或不同的激活退火工艺激活。退火条件可改变，为本领域所熟知。所得结构包括图形化的多晶硅区域18和源/漏扩展注入区域20，例如如图3所示。
然后诸如TEOS的介电材料22通过传统淀积工艺被淀积，此结构通过如化学机械抛光的传统平坦化工艺被平坦化来提供如图4所示的平坦结构。注意毗邻图形化多晶硅区域的介电材料的上表面与图形化的多晶硅区域的上表面共面。
然后图形化的多晶硅区域18被从图4所示的结构上去除来提供开口24，暴露一部分牺牲氧化层16。去除图形化的多晶硅区域后形成的结构如图5所示。图形化的多晶硅区域可利用化学顺向刻蚀去除或KOH湿刻工艺去除图形化的多晶硅区域。
图6描述了器件沟道/体注入时的结构。标记号26是指被注入衬底中来确定器件沟道/体区域28的离子。本发明的此注入步骤包括使用传统离子注入。器件沟道/体区域注入后，注入区域利用本领域已熟知的条件退火。本发明的优选实施方案中，器件沟道/体注入在Ar中1000℃下退火约5秒。
图7描述了Si间隔件30被形成于介电材料22的暴露垂直侧壁上后形成的结构。Si间隔件通过先在开口24中首先淀积一层Si，然后刻蚀Si层来提供位于介电材料22的暴露垂直侧壁上的Si间隔件来形成。Si间隔件30的厚度通常为约0.5至约5nm。
然后开口24中牺牲氧化层16的暴露部分被去除来提供如图8所示的结构。特别的是，牺牲氧化层的暴露部分通过化学氧化物去除(COR)刻蚀工艺来去除，其中气相或更优选的等离子体HF和NH3被用作刻蚀剂，使用低压(约6毫托或以下)。注意COR刻蚀在Si间隔件下提供一底切，它暴露了躺在器件沟道/体注入区域上的衬底的表面部分。
然后栅极电介质32利用传统热生长工艺被形成于器件沟道/体注入区域上的衬底暴露表面上。注意，当栅极电介质形成时，Si间隔件30被暴露形成氧化Si间隔件31。栅极电介质可由包含但不限于：SiO2，Al2O3，Ta2O3，TiO2和钙钛矿型氧化物的氧化物组成。依赖于热生长的氧化物类型，本发明的栅极介电材料可具有约3.0或更大的介电常数。
注意在某些实施方案中，栅极电介质被淀积，然后分离氧化工艺能用来转化Si间隔件为氧化的Si间隔件。无论采用何技术来形成栅极电介质，栅极电介质厚度为约1.0至约10nm。
然后多晶硅-栅极(poly-gate)34利用淀积一层多晶硅被形成于栅极电介质32上的开口中，然后平坦化这层多晶硅来与介电材料22的上水平面共面。注意淀积的多晶硅可被掺杂或不掺。当未掺杂的多晶硅被淀积，未掺杂的多晶硅层经历平坦化后的多晶硅-栅极(poly-gate)注入和退火。尽管退火条件可变，优选在Ar中1050℃下退火约5秒。所得结构包括栅极电介质32，氧化的Si间隔件31和多晶硅-栅极(poly-gate)34，例如如图9所示。
然后多晶硅-栅极(poly-gate)的上面部分被利用计时刻蚀工艺凹入。凹入的多晶硅-栅极(poly-gate)可选择地经历氧化工艺，在凹入多晶硅-栅极(poly-gate)的上表面上形成氧化层36。参看图10，注意，如需要，二次氧化确保Si间隔件的彻底氧化。
然后，用于T-栅极的区域通过去除部分氧化的Si间隔件和在如图11中箭头38所示横向方向上修整介电材料被形成于凹入多晶硅-栅极(poly-gate)上。特别的是，诸如上述提及的各向异性的COR工艺被用于形成T-栅极区域。注意T-栅极区域比以前形成的凹入多晶硅-栅极(poly-gate)的宽度更宽。
然后栅极导体40占优势地被淀积于图11中形成的T-栅极区域中，并被平坦化成介电材料22的上水平面来提供如图12所示的平面结构。栅极导体可为多晶硅；如Al，W，Cu，Ti和类似物的导体金属；如WSi，TiSi，或CoSi的硅化物；或它们的复合物。某些情形中，当多晶硅和导电的金属复合物被采用时，可选的阻挡衬垫通常被形成于两导电材料之间。如需要，阻挡衬垫也可被形成于凹入多晶硅-栅极(poly-gate)34和栅极导体40间。注意因为栅极具有上区域，即比低区域(即凹入的多晶硅-栅极(poly-gate)34)更宽的栅极导体40，因此栅极导体40和凹入多晶硅-栅极(poly-gate)34被一道称为T-栅极。用于栅极导体40的一优选导体材料包括形成于多晶硅上的W的导体叠层。
接着，毗邻T-栅极的介电材料利用从此结构高选择性去除介电材料22的刻蚀工艺被去除。然后氮化物间隔件42被形成于凹入多晶硅-栅极(poly-gate)的暴露部分来使得氮化物间隔件的外垂直边缘与栅极导体40的外边缘对准。氮化物间隔件以高共形的淀积工艺被形成。参看图13。
然后源/漏区域44能以传统离子注入和激活退火被邻近T-栅极形成于衬底上。参看图13。尽管各种激活退火条件被采用，优选退火源/漏离子注入于Ar中1000℃下约5秒。某些实施方案中，特别当衬底10为SOI晶片的薄含Si层时，接着氮化物区42形成升高的源/漏区(为示出)。
图13所示的结构可经历传统硅化工艺来形成硅化物区于源/漏区和T-栅极上，然后是本领域技术人员已熟知和已描述的传统CMOS工艺步骤，例如参见R.Colclaser，“微电子工艺和器件设计”，第10章，266-269页，John-Wiley和Sons出版社，1980。
上述本发明方法利用了镶嵌栅极工艺和COR刻蚀来制备亚-0.1μm沟长带T-栅极结构的MOSFET。所得器件具有低-栅极薄层电阻，能发挥亚-0.1μmCMOS技术的很高器件性能。T-栅极在传统栅极器件中形成源极和漏极间隔件的相同空间中形成。因此，这里描述的新T-栅极技术产生高-性能的MOSFET而不影响器件封装密度。还注意到本发明产生不出现任何传统多Si-栅极器件中通常存在的多晶硅耗尽问题的亚-0.1μm沟长MOSFET。
当本发明根据其优选实施方案被具体示出和描述时，本领域的技术人员应理解到可作前述和其它形式和细节的改变而不偏离本发明的精髓和范围。因此，本发明不限于所描述和示出的精确形式和细节，而落入附带的权利要求的范围内。
Claims (17)
1.一种形成亚-0.1μm沟道长度MOSFET的方法，包括步骤：
形成一平面结构，它包括含有Si的衬底，位于所述含Si衬底表面上的牺牲氧化层，位于一部分所述牺牲氧化层上的图形化的多晶硅区域，以及毗邻所述图形化多晶硅区域的介电材料；
去除所述图形化多晶硅区域来提供一个开口，暴露一部分所述牺牲氧化层，并且注入离子进入含Si衬底来形成器件沟道或体注入区域，所述器件沟道或体注入区域的长度小于0.1μm；
在所述介电材料的暴露的垂直侧壁上形成Si间隔件；
利用化学氧化物去除刻蚀来去除牺牲氧化层的所述暴露部分以便暴露所述含Si衬底的表面；
在所述含Si衬底的暴露表面上形成栅极电介质，并氧化所述Si间隔件；
在所述栅极电介质中形成凹入多晶硅-栅极区域，所述凹入多晶硅-栅极在其上表面上具有氧化层；
横向刻蚀所述氧化的硅间隔件和位于所述凹入多晶硅-栅极之上的部分所述介电材料来提供一个比所述凹入多晶硅-栅极宽的区域；
在所述区域中形成栅极导体并去除剩余的介电材料；以及
在所述栅极导体之下的所述凹入多晶硅-栅极的暴露的垂直侧壁上形成氮化物间隔件。
2.如权利要求1所述的方法，其中用化学顺向刻蚀或KOH刻蚀工艺去除所述图形化多晶硅区域。
3.如权利要求1所述的方法，其中用淀积和刻蚀形成所述Si间隔件。
4.如权利要求1所述的方法，其中所述化学氧化物去除刻蚀在含HF和NH3的蒸汽存在下进行。
5.如权利要求1所述的方法，其中所述化学氧化物去除刻蚀在含HF和NH3的等离子体下进行。
6.如权利要求1所述的方法，其中所述栅极电介质为由热生长工艺形成的氧化物。
7.如权利要求1所述的方法，其中所述Si间隔件在形成所述栅极电介质时被氧化。
8.如权利要求1所述的方法，其中所述横向刻蚀利用化学氧化物去除刻蚀进行。
9.如权利要求8所述的方法，其中所述化学氧化物去除刻蚀在含HF和NH3的蒸汽存在下进行。
10.如权利要求8所述的方法，其中所述化学氧化物去除刻蚀在含HF和NH3的等离子体中进行。
11.一种低阻T-栅极MOSFET，包括：
含Si衬底，该衬底至少包括将源极区域与漏极区域分开的一个器件沟道或体注入区域，所述至少一个器件沟道或体注入区域长度小于约0.1μm；
至少位于所述器件沟道或体注入区域、所述源极区域和漏极区域上的栅极电介质；
位于一部分所述栅极电介质上的T-栅极，所述T-栅极包括凹入的底多晶硅区域和上栅极导体区域，所述上栅极导体区域的宽度大于所述底多晶硅区域的宽度；以及
位于所述底多晶硅区域的暴露的垂直侧壁上的氮化物间隔件，所述氮化物间隔件的外边缘与上栅极导体区域的外边缘对准。
12.如权利要求11所述的低阻T-栅极MOSFET，其中所述栅极电介质为介电常数为3.0或更大的氧化物。
13.如权利要求11所述的低阻T-栅极MOSFET，其中所述含Si衬底为绝缘体上硅晶片构成的部件。
14.如权利要求11所述的低阻T-栅极MOSFET，其中所述上栅极导体由多晶硅、导电金属、硅化物或它们的复合物构成。
15.如权利要求14所述的低阻T-栅极MOSFET，其中所述上栅极导体由导电金属构成。
16.如权利要求11所述的低阻T-栅极MOSFET，其中所述上栅极导体由W构成。
17.如权利要求11所述的低阻T-栅极MOSFET，其中所述上栅极导体由包括位于多晶硅上的W的导电叠层构成。
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| US5162884A (en) * | 1991-03-27 | 1992-11-10 | Sgs-Thomson Microelectronics, Inc. | Insulated gate field-effect transistor with gate-drain overlap and method of making the same |
| US5282925A (en) | 1992-11-09 | 1994-02-01 | International Business Machines Corporation | Device and method for accurate etching and removal of thin film |
| US6063677A (en) | 1996-10-28 | 2000-05-16 | Texas Instruments Incorporated | Method of forming a MOSFET using a disposable gate and raised source and drain |
| US5766971A (en) | 1996-12-13 | 1998-06-16 | International Business Machines Corporation | Oxide strip that improves planarity |
| US6261887B1 (en) * | 1997-08-28 | 2001-07-17 | Texas Instruments Incorporated | Transistors with independently formed gate structures and method |
| US6436746B1 (en) * | 1998-01-12 | 2002-08-20 | Texas Instruments Incorporated | Transistor having an improved gate structure and method of construction |
| CN1219328C (zh) | 1998-02-19 | 2005-09-14 | 国际商业机器公司 | 具有改善了注入剂的场效应晶体管及其制造方法 |
| US6040214A (en) | 1998-02-19 | 2000-03-21 | International Business Machines Corporation | Method for making field effect transistors having sub-lithographic gates with vertical side walls |
| US6271094B1 (en) * | 2000-02-14 | 2001-08-07 | International Business Machines Corporation | Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance |
| US7008832B1 (en) * | 2000-07-20 | 2006-03-07 | Advanced Micro Devices, Inc. | Damascene process for a T-shaped gate electrode |
| US6500743B1 (en) * | 2000-08-30 | 2002-12-31 | Advanced Micro Devices, Inc. | Method of copper-polysilicon T-gate formation |
| DE10114778A1 (de) * | 2001-03-26 | 2002-10-17 | Infineon Technologies Ag | Verfahren zur Herstellung eines MOSFETs mit sehr kleiner Kanallänge |
-
2002
- 2002-11-08 US US10/291,353 patent/US6656824B1/en not_active Expired - Fee Related
-
2003
- 2003-09-11 US US10/659,949 patent/US7176534B2/en not_active Expired - Fee Related
- 2003-11-07 CN CNB200310114892XA patent/CN1256759C/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US6656824B1 (en) | 2003-12-02 |
| US7176534B2 (en) | 2007-02-13 |
| US20050170659A1 (en) | 2005-08-04 |
| CN1499588A (zh) | 2004-05-26 |
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