CN1244140C - 在半导体基板上形成电介质薄膜的方法 - Google Patents

在半导体基板上形成电介质薄膜的方法 Download PDF

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CN1244140C
CN1244140C CNB01814828XA CN01814828A CN1244140C CN 1244140 C CN1244140 C CN 1244140C CN B01814828X A CNB01814828X A CN B01814828XA CN 01814828 A CN01814828 A CN 01814828A CN 1244140 C CN1244140 C CN 1244140C
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A·S·凯勒
M·D·怀特曼
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Abstract

一种具有良好沉积后的填隙特性以及良好的活动离子吸杂性能的前金属电介质薄膜的形成方法。该方法包括以下的步骤：首先，将通过使用具有高臭氧/TEOS容积比的气体混合物而产生的高臭氧非掺杂的二氧化硅薄膜层(20)沉积在一半导体基板(12)上。然后，使一低臭氧的经掺杂的BPSG薄膜层(30)沉积在所述高臭氧非掺杂的二氧化硅层(20)上。对薄膜层(20，30)进行热处理使薄膜稠化，然后利用公知的平面化技术使所述上层(30)平面化，达到可供足够活动离子吸杂的厚度。

Description

在半导体基板上形成电介质薄膜的方法
技术领域
本发明涉及半导体加工，更具体地说，涉及一种在半导体基底或基板上形成一电介质薄膜的方法以及涉及一种形成具有这种电介质薄膜的半导体器件的方法。
背景技术
在形成半导体集成电路器件中，惯常的平面制程是在一硅基板表面上形成表层下扩散层和多晶硅导体。一层或多层电介质薄膜沉积在硅基板表面上，金属配线导体形成在电介质薄膜上或内，使硅基板表面上形成的各种元件互连以制成所希望的集成电路。
最好是在金属化处理之前沉积在基板上的电介质薄膜具有良好的活动离子吸杂性能，以及良好的再流动或填隙性能。一种在现有技术中曾广泛使用的绝缘薄膜是一单硼磷硅玻璃(BPSG)层。请参见图5，在现有技术中，通常首先将一薄的非掺杂的氧化衬垫58沉积在具有多个多晶硅导体54的硅基板表面52上。一般，该薄的非掺杂的氧化衬垫58是由硅甲烷(SiH4)与氧进行反应而形成的，然后，该层继之以是一掺杂的玻璃层，例如前述的一BPSG层56。该薄的非掺杂的氧化衬垫58的用途是防止在BPSG薄膜56中所含的磷(亚磷)或硼扩散到基板52的扩散层中。
使用BPSG薄膜作为层间电介质薄膜的目的是基于吸杂性能以及基于再流性能。电介质薄膜具有良好的吸杂性能是很重要的，因为希望它能够有效地吸杂以去除在晶片制程中引入的任何杂质。电介质薄膜具有良好的再流性能也是很重要的，可使得硅基板表面上凸起的多晶硅导体之间的间隙被完全填满。这种性质有时被称之为具有良好的“填隙”或良好的“阶梯覆盖”。
在现有技术中，BPSG薄膜层一般是通过在膦(PH3)和乙硼烷(B2H6)存在下原硅酸四乙酯或四乙基硅酸盐(TEOS)与臭氧(O3)进行反应而形成的。在本文中，我们将臭氧和TEOS反应物称为“臭氧/TEOS”或“臭氧和TEOS”。掺杂的BPSG薄膜中的硼约为4％至6％，磷的重量百分数约为4％至8％。SiO2的软化点可以通过添加上述优质硼和磷来减小至大约875-900℃。然后，在诸如875-900℃的高温下，使用再流工序来软化掺杂玻璃并使之流入基板中的空隙和间隙内以形成一具有良好填隙质量的前金属电介质薄膜。然而，应注意到，含高掺杂的BPSG薄膜不具有良好的沉积后填隙质量。只是在比其软化点高的温度下再流后，它才完全填满多晶硅导体之间的间隙。
然而，当器件的几何形状在尺寸上连续减小时，由于硅基板中的n-和p-型掺杂物的增强扩散，而不再要求高温再流。这种扩散可导致该器件的电学参数不希望的变化，诸如在临界电压和饱和电流上的变化。然而，在没有高温再流的情况下，含高掺杂的BPSG薄膜就不能充分地填隙。掺杂物料(硼和亚磷)使玻璃的软化点降低，使得在较低温度下不能充分地填满间隙。如图5所示，孔隙60会在多晶硅导体54之间的BPSG薄膜56中扩大。当接点被蚀刻穿过电介质薄膜并在随后的金属化处理期间填充钨时，通过化学气相沉积法沉积的钨填入孔隙中，导致剩余金属或“纵梁”(stringers)形成在相邻接点之间。这将会导致相邻接点间出现不必要的短路，而使该半导体器件损坏。因此，这就需要一种具有良好填满特性而不要求高温再流的前金属化的电介质薄膜。
在现有技术中，早先曾试图生产一种具有良好填隙质量的层间电介质薄膜，包括Murao的美国专利号5,518,962，该专利揭示了一种在基板表面区形成的半导体器件，所述基板表面区包覆有一非掺杂的CVD氧化硅薄膜，以及一形成在氧化硅薄膜上的层间绝缘薄膜，该层间绝缘薄膜由一第一臭氧-TEOS非掺杂的硅玻璃(NSG)薄膜、一BPSG薄膜层和一第二臭氧-TEOS NSG薄膜组成。另外，Becker等人的美国专利号5,869,403和5,994,237描述了一种半导体加工方法，该方法是形成一对要制成电连接的基板接点区域相邻的基板敞开的接点。在较佳实施例中，一由TEOS分解而成的第一氧化层形成在基板上包覆至少一部分接点区域，一由BPSG制成的第二氧化层形成在第一氧化层上面。Lee等人的美国专利号5,166,101和5,354,387还揭示了一种组合BPSG绝缘和表面平整层，它是采用一两阶段法形成在一半导体晶片的台阶式表面上。该两阶段沉积法包括：第一阶段，利用亚磷和硼掺杂物的气态源以及TEOS作为硅的来源，通过一CVD沉积形成一无孔隙BPSG层；第二阶段，形成一BPSG的封端层。
本发明的一个目的是提供一种前金属层间电介质薄膜的形成方法，该薄膜具有良好的活动离子吸杂性能以及良好的填隙特性。
本发明的另一个目的是提供一种前金属层间电介质薄膜的形成方法，该薄膜具有的良好沉积后填满特性而不取决于高温再流处理。
发明内容
本发明的目的是这样达成的：提供一种具有良好的沉积后填隙特性以及良好吸杂性能的前金属电介质薄膜的形成方法。该方法包括以下步骤：首先沉积一具有无孔隙填满特性的高臭氧非掺杂的二氧化硅薄膜层，然后沉积一具有吸杂能力的低臭氧的经掺杂的BPSG薄膜层。所述两层绝缘薄膜能够在不损活动离子良好吸杂性能的情况下充分地填满小缝或窄缝间的间隙。现有技术的绝缘薄膜既不能良好地填满间隙，又不能良好地吸杂，或是现有技术的薄膜需要好几层才能达到所要求的性能。
非掺杂的二氧化硅薄膜是从臭氧和TEOS的气体混合物中形成，所述混合物的高臭氧/TEOS容积比至少为15∶1，而现有技术中掺杂的BPSG薄膜一般具有低的臭氧/TEOS比率，例如10∶1。通过形成一具高臭氧/TEOS比率的薄膜，TEOS-二聚体的表面活动性会增加，使薄膜具有较好的流动特性。反应物可快速地在表面扩散，因此可找到能量最低的区域。这产生了一无孔隙电介质薄膜表面。
然后进行热处理使薄膜稠化，而不是像现有技术那样使薄膜软化和流动。该热处理可在较低温度下进行，从而防止了上述在较小器件的几何形状内与高温热处理相关的扩散问题。最后，利用化学机械平面化技术使第二BPSG层上面制成平面。本发明的方法可用于半导体器件的成形，而且也可用于需要良好填隙或阶梯覆盖的其他结构的成形，诸如多晶硅总线结构的成形。
附图说明
图1为一具有多个多晶硅导体的半导体基板的剖视图。
图2至4为剖视图，表示按照本发明的方法在图1所示的半导体基板上形成一电介质薄膜的步骤。
图5为剖视图，表示在现有技术的已知的半导体基板上施加一典型的电介质薄膜。
具体实施方式
请参见图1，一硅基板12具有多个形成在其上表面的多晶硅导体14。应该理解，硅基板12在本发明的方法之前已经历了不同步骤的晶片制备制程，目的是在基板上形成各种二极管、晶体管、电阻以及其他元件。这是通过将掺杂物以本领域普通技术人员公知的方式加入到纯硅中制成的。多晶硅导体14也以本领域普通技术人员公知的方式形成在基板的上表面。每一多晶硅导体14之间有间隙16，该间隙必须填满电绝缘的电介质薄膜。
请参见图2，一层高臭氧非掺杂的二氧化硅薄膜20沉积在半导体基板12和多晶硅导体14上面。该高臭氧非掺杂的二氧化硅薄膜覆盖多晶硅导体14并填满多晶硅导体14之间的间隙16。第一薄膜层20的厚度不小于100纳米，但不超过400纳米。第一薄膜层20的臭氧浓度不小于120克/立方米，但不超过140克/立方米。第一薄膜层20不用硼或磷掺杂，以使得沉积时的填隙过程达到最好。第一薄膜层20的一个特征是通过使用具有高的臭氧/TEOS容积比的臭氧和TEOS的气体混合物来形成。在现有技术中，通常使用的气体混合物的臭氧/TEOS的比率大约为10∶1。而在本发明中，臭氧/TEOS的比率为15∶1，最好是17∶1。较高的臭氧/TEOS比率促使形成二聚体，该二聚体是由两个具有高表面活动性的单体的组合。这种高表面活动性可形成全面的表面反应，而不仅仅是气相反应。因为完整的表面反应形成后，离子是在表面活动的，从而找到最小能量的位置。这将导致表面活动性增高且薄膜具有流动状特征。因为反应物可以快速地扩散在表面上，薄膜以高的纵横尺寸比充分完全地填满多晶硅导体之间的间隙，而不会留下任何孔隙或细缝。
请参见图3，一层低臭氧的经掺杂的BPSG薄膜30沉积在二氧化硅薄膜20上。第二薄膜层30的厚度不小于500纳米。BPSG薄膜要足够厚是很重要的，以使得接着的平面化之后整个器件上面有足够厚度的BPSG薄膜。平面化之后BPSG薄膜的最佳厚度至少为200纳米。因此，电介质薄膜的厚度一般由不超过30％非掺杂的二氧化硅薄膜20的第一薄膜层和至少70％的BPSG薄膜30的第二薄膜层组成。BPSG薄膜30的臭氧浓度不小于70克/立方米，但不超过100克/立方米。BPSG薄膜中的硼重量百分数的典型范围为0至4％，而该薄膜的磷重量百分不超过6％，典型的范围为4至6％。BPSG薄膜30具有半导体器件所需的活动离子吸杂性能。
然后，基板12上面形成的两薄膜层20和30将在不超过850℃的温度下进行热处理。热处理的温度约为700℃较理想，以使足够高的温度可以产生足够均匀的再流动，但当器件的几何形状或尺寸较小时，足够低的温度并不影响该器件的特性。如上所述，由二氧化硅薄膜层20和BPSG薄膜层30组成的电介质薄膜由于具有良好的沉积后填隙特性，该薄膜可不需在高温下退火。进行热退火是使薄膜稠化，而不是使薄膜软化和流动。在本发明中，在700℃和800℃之间的温度下进行退火以获得足够稠密的金属前的电介质薄膜，该薄膜对可制造的接点蚀刻外形和蚀刻速率是必要的。
请参见图4，上电介质薄膜层30利用任何公知的包括化学机械平面化的平面化技术制成平面。如上所述，平面化后的BPSG层上面的厚度应该至少为200纳米，以考虑到足够活动离子吸杂。制成的硅基板现随时可进行金属化处理，在此处理中将金属通过该电介质层沉积以形成金属配线导体，该导体使硅基板上形成的元件互连于在集成电路晶片上以获得所要求的电路。形成一电介质薄膜层的上述方法的应用不限于用在半导体上，薄膜层也不限于用在一半导体基板上，而且还可用于在一基板上形成的两个或更多多晶硅总线上形成一绝缘层，或是任何情况下提供一绝缘层，其中，对该绝缘层而言，具有良好的填隙质量是关键的。

Claims (7)

1.一种在半导体基板上形成电介质薄膜的方法，其特征在于，该方法包括以下步骤：
在具有多个多晶硅导体的半导体基板上沉积第一薄膜层，所述第一薄膜层是使用臭氧和TEOS的气体混合物而形成的非掺杂薄膜，而所述气体混合物中臭氧和TEOS的容积比至少为15∶1；
在所述第一薄膜层上面沉积一第二薄膜层，所述第二薄膜层由经掺杂的臭氧BPSG薄膜形成，其中所述BPSG薄膜的臭氧浓度的范围为70至100克/立方米；
对所述第一和第二薄膜层进行热处理；以及
使所述第二薄膜层平面化，以使覆盖在所述多晶硅导体上的第二薄膜层的厚度至少为200纳米。
2.如权利要求1所述的方法，其特征在于，所述第一薄膜层的厚度范围为100至400纳米。
3.如权利要求1所述的方法，其特征在于，所述第二薄膜层的厚度至少为500纳米。
4.如权利要求1所述的方法，其特征在于，所述加热处理是在至少700℃的温度下进行。
5.如权利要求1所述的方法，其特征在于，所述第二薄膜层的硼的重量百分数范围为0至4％。
6.如权利要求1所述的方法，其特征在于，所述第二薄膜层的磷的重量百分数不超过6％。
7.如权利要求1所述的方法，其特征在于，所述第一薄膜层的臭氧浓度范围为120克/立方米至140克/立方米。
CNB01814828XA 2000-08-29 2001-07-18 在半导体基板上形成电介质薄膜的方法 Expired - Fee Related CN1244140C (zh)

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