CN1219323C - 一种互连结构及其制作方法 - Google Patents
一种互连结构及其制作方法 Download PDFInfo
- Publication number
- CN1219323C CN1219323C CNB021052964A CN02105296A CN1219323C CN 1219323 C CN1219323 C CN 1219323C CN B021052964 A CNB021052964 A CN B021052964A CN 02105296 A CN02105296 A CN 02105296A CN 1219323 C CN1219323 C CN 1219323C
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- Prior art keywords
- layer
- dielectric
- low
- spinning
- dielectrics
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- FWDBOZPQNFPOLF-UHFFFAOYSA-N ethenyl(triethoxy)silane Chemical compound CCO[Si](OCC)(OCC)C=C FWDBOZPQNFPOLF-UHFFFAOYSA-N 0.000 claims description 4
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims 3
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01—ELECTRIC ELEMENTS
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
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- H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
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- H01L21/02107—Forming insulating materials on a substrate
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- H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/312—Organic layers, e.g. photoresist
- H01L21/3121—Layers comprising organo-silicon compounds
- H01L21/3122—Layers comprising organo-silicon compounds layers comprising polysiloxane compounds
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
Claims (63)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/795,430 US6710450B2 (en) | 2001-02-28 | 2001-02-28 | Interconnect structure with precise conductor resistance and method to form same |
US09/795,430 | 2001-02-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1373512A CN1373512A (zh) | 2002-10-09 |
CN1219323C true CN1219323C (zh) | 2005-09-14 |
Family
ID=25165493
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB021052964A Expired - Fee Related CN1219323C (zh) | 2001-02-28 | 2002-02-26 | 一种互连结构及其制作方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6710450B2 (zh) |
JP (1) | JP4177582B2 (zh) |
KR (1) | KR100454793B1 (zh) |
CN (1) | CN1219323C (zh) |
TW (1) | TW548744B (zh) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6949456B2 (en) * | 2002-10-31 | 2005-09-27 | Asm Japan K.K. | Method for manufacturing semiconductor device having porous structure with air-gaps |
US6917108B2 (en) * | 2002-11-14 | 2005-07-12 | International Business Machines Corporation | Reliable low-k interconnect structure with hybrid dielectric |
US20040152239A1 (en) * | 2003-01-21 | 2004-08-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interface improvement by electron beam process |
CN100428453C (zh) * | 2003-01-29 | 2008-10-22 | 国际商业机器公司 | 含有低k介电阻挡膜的互连结构及其制造方法 |
US6940173B2 (en) * | 2003-01-29 | 2005-09-06 | International Business Machines Corporation | Interconnect structures incorporating low-k dielectric barrier films |
US20040191417A1 (en) * | 2003-03-28 | 2004-09-30 | Dorie Yontz | Method of integrating a porous dielectric in an integrated circuit device |
DE10332567A1 (de) * | 2003-07-11 | 2005-02-17 | Infineon Technologies Ag | Verbindung für die Bildung einer Schicht auf einem Substrat, Verfahren zur Herstellung einer Schicht auf einem Substrat und Halbleiterbauelement |
US7071539B2 (en) * | 2003-07-28 | 2006-07-04 | International Business Machines Corporation | Chemical planarization performance for copper/low-k interconnect structures |
US7018560B2 (en) * | 2003-08-05 | 2006-03-28 | Rohm And Haas Electronic Materials Cmp Holdings, Inc. | Composition for polishing semiconductor layers |
US7057287B2 (en) * | 2003-08-21 | 2006-06-06 | International Business Machines Corporation | Dual damascene integration of ultra low dielectric constant porous materials |
JP4160489B2 (ja) * | 2003-10-31 | 2008-10-01 | 株式会社東芝 | 半導体装置の製造方法 |
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JP2868167B2 (ja) * | 1991-08-05 | 1999-03-10 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 多重レベル高密度相互接続構造体及び高密度相互接続構造体 |
US5962581A (en) * | 1995-04-28 | 1999-10-05 | Kabushiki Kaisha Toshiba | Silicone polymer composition, method of forming a pattern and method of forming an insulating film |
US6340435B1 (en) * | 1998-02-11 | 2002-01-22 | Applied Materials, Inc. | Integrated low K dielectrics and etch stops |
JP3175691B2 (ja) * | 1998-05-08 | 2001-06-11 | 日本電気株式会社 | 多層配線半導体装置の製造方法 |
US6265780B1 (en) * | 1998-12-01 | 2001-07-24 | United Microelectronics Corp. | Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit |
US6184284B1 (en) * | 1998-08-24 | 2001-02-06 | The Dow Chemical Company | Adhesion promoter and self-priming resin compositions and articles made therefrom |
US6071809A (en) | 1998-09-25 | 2000-06-06 | Rockwell Semiconductor Systems, Inc. | Methods for forming high-performing dual-damascene interconnect structures |
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KR100454793B1 (ko) | 2004-11-05 |
KR20020070631A (ko) | 2002-09-10 |
JP2002319621A (ja) | 2002-10-31 |
JP4177582B2 (ja) | 2008-11-05 |
TW548744B (en) | 2003-08-21 |
CN1373512A (zh) | 2002-10-09 |
US6710450B2 (en) | 2004-03-23 |
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