CN121866521A - 双向逻辑元件、运算装置及运算方法 - Google Patents
双向逻辑元件、运算装置及运算方法Info
- Publication number
- CN121866521A CN121866521A CN202480058293.0A CN202480058293A CN121866521A CN 121866521 A CN121866521 A CN 121866521A CN 202480058293 A CN202480058293 A CN 202480058293A CN 121866521 A CN121866521 A CN 121866521A
- Authority
- CN
- China
- Prior art keywords
- bidirectional
- input
- function
- output
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2024027754 | 2024-02-27 | ||
| JP2024-027754 | 2024-02-27 | ||
| PCT/JP2024/039519 WO2025182149A1 (ja) | 2024-02-27 | 2024-11-06 | 双方向論理素子、演算装置、及び演算方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN121866521A true CN121866521A (zh) | 2026-04-14 |
Family
ID=96920979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202480058293.0A Pending CN121866521A (zh) | 2024-02-27 | 2024-11-06 | 双向逻辑元件、运算装置及运算方法 |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP7802253B1 (https=) |
| CN (1) | CN121866521A (https=) |
| WO (1) | WO2025182149A1 (https=) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4593346B2 (ja) * | 2005-04-20 | 2010-12-08 | 博幸 荻野 | 汎用論理モジュール及びそれを有する回路 |
| JP5918568B2 (ja) * | 2012-02-29 | 2016-05-18 | 株式会社日立情報通信エンジニアリング | 論理モジュール |
-
2024
- 2024-11-06 JP JP2025556015A patent/JP7802253B1/ja active Active
- 2024-11-06 CN CN202480058293.0A patent/CN121866521A/zh active Pending
- 2024-11-06 WO PCT/JP2024/039519 patent/WO2025182149A1/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2025182149A1 (https=) | 2025-09-04 |
| JP7802253B1 (ja) | 2026-01-19 |
| WO2025182149A1 (ja) | 2025-09-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1271474B1 (en) | Function block | |
| US7971172B1 (en) | IC that efficiently replicates a function to save logic and routing resources | |
| US4215416A (en) | Integrated multiplier-accumulator circuit with preloadable accumulator register | |
| Saxena et al. | Analysis of low power, area-efficient and high speed fast adder | |
| Sarkar et al. | Comparison of various adders and their VLSI implementation | |
| US4878192A (en) | Arithmetic processor and divider using redundant signed digit arithmetic | |
| Makino et al. | A 8.8-ns 54/spl times/54-bit multiplier using new redundant binary architecture | |
| US5010511A (en) | Digit-serial linear combining apparatus useful in dividers | |
| JP3436994B2 (ja) | シフト装置 | |
| JP3225043B2 (ja) | 絶対値算術演算ユニット及び差動マルチプレクサ | |
| Ganguly et al. | A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits | |
| JP3604518B2 (ja) | 除算装置 | |
| US4866655A (en) | Arithmetic processor and divider using redundant signed digit | |
| JP7802253B1 (ja) | 双方向論理素子、演算装置、及び演算方法 | |
| US4873660A (en) | Arithmetic processor using redundant signed digit arithmetic | |
| KR100975086B1 (ko) | 초소형 저전력 1비트 전가산기 | |
| US5084834A (en) | Digit-serial linear combining apparatus | |
| US4866657A (en) | Adder circuitry utilizing redundant signed digit operands | |
| US6484193B1 (en) | Fully pipelined parallel multiplier with a fast clock cycle | |
| US3588483A (en) | Variable digital processor including a register for shifting and rotating bits in either direction | |
| US4935892A (en) | Divider and arithmetic processing units using signed digit operands | |
| CN117971157A (zh) | 进位逻辑电路 | |
| US5978826A (en) | Adder with even/odd 1-bit adder cells | |
| Lin | Shift switching and novel arithmetic schemes | |
| Joe et al. | Design of low power high speed hybrid adder |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination |