Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/02—Digital function generators
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components

Definitions

• the present invention relates to a bidirectional logic element, an arithmetic unit, and an arithmetic method.
• Branch-type logic elements that use electrical/electronic components include relays
• gate-type logic elements include DTL, TTL, ECL, MOS, and other elements (Non-Patent Documents 1 and 2).
• Another branch-type bidirectional logic element was a bidirectional logic element using Esaki diodes. This element was a two-terminal logic element using an Esaki diode pair and a delay element. Its features included a small number of components and the ability to perform high-speed bidirectional calculations by setting appropriate delay operating conditions through excitation. This element required delicate condition setting and has not yet been widely adopted, but current integration technology has made it possible for it to become widespread (Non-Patent Documents 3 and 4). Another method involves looking up a table of memory elements using a combination of inputs corresponding to these calculations. Furthermore, there are bidirectional elements using ferroelectric capacitors. This method can also be implemented by replacing it with a Jopsephson effect element (Patent Documents 2 and 3).
• branch-type switching elements such as HEMTs, spin Esaki diodes, superconducting elements, and quantum bit elements have become available, and these can also be used to construct bidirectional logic elements (Patent Documents 4, 5, and 6; Non-Patent Documents 5, 6, and 7).
• integrated logic elements did not include bidirectional logic elements that could transfer information or perform calculations in both directions. Furthermore, there were no adder/subtractors or multiplier/dividers, which are typical devices constructed from such elements.
• the above multiplication/division uses AND elements, but mathematically, multiplication/division is not a perfect inverse function.
• Non-Patent Document 12 In order to address the inconsistency in the implementation of an array multiplier/divider, the above combination is treated as "0" according to mathematical definitions. However, if even one of the multi-digit multiplicands in each row is not “0", it is treated as "1". This resolves the inconsistency in the arithmetic operation (Non-Patent Document 12).
• addition/subtraction and multiplication/division are implemented using gate-type technology. This means that calculations, control, or information processing are configured to proceed in one direction, from input to output. Therefore, the inverse functions of multiplication/division do not hold, and in principle, it was necessary to configure and arrange adders, multipliers, subtractors, and dividers separately. This required a large number of components, a large area, and power consumption.
• addition/subtraction a method has been realized in which addition/subtraction is combined into one operation using an adder that adds complements. Subtraction and division cells that use complements have also been realized (Non-Patent Document 13).
• Non-Patent Documents 13, 14, 15 Various configurations and algorithms have been devised to achieve higher speeds and higher integration.
• Patent Documents 13, 14, 15 Various configurations and algorithms have been devised to achieve higher speeds and higher integration.
• Patent Documents 13, 14, 15 a redundant binary arithmetic algorithm has been proposed as a high-speed arithmetic algorithm (Patent Document 5, Non-Patent Document 16).
• Patent Documents 17, 18 a 64-bit floating-point arithmetic unit based on this has been put into practical use.
• Non-Patent Document 19 Non-Patent Document 19
• the present method is also compatible with the IEEE 754 format, and when arithmetic operations are frequently used in AI, for example, in the case of multiplication/division, the bidirectional multiplier/divider of the present invention can be applied to the multiplication/division part of the mantissa, and the bidirectional adder/subtractor of the present invention can be applied to the exponent part in floating-point multiplication/division.
• Another method is to repeat multiplications and converge to the quotient by trial and error. The present method does not require trial and error selection for division.
• Tanaka Electrical tuning of the band alignment and magnetic conductance in an n-type fer romagnetic semiconductor (In, Fe) As based spin-Esaki diode, Applied Physics Letters 2018 M. TANAKA, K. TAKAGI, N. TAKAGI: High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential an d Logarithm Computation Using the Radix-2 Signed Digit Representation, IEICE TRANS. ELECTRON. 2016 RCA: CMOS/MOS Integrated Circuits Manual 1972 MOTOROLA: McMOS HANDBOOK 1974 C. Mead L. Conway: INTRODUCTION TO VLSI SYSTEMS ADDISON-WESLEY 1980 Neil H. E.
• the gist and configuration of the present invention are as follows.
• a function/inverse function control unit that controls the direction of operation of the logic element to switch between a function, which is a forward operation, and an inverse function, which is a reverse operation;
• a forward input unit for inputting data in the case of a forward operation;
• a forward information transfer unit that transfers the input from the forward input unit;
• a reverse direction input unit for inputting data in the case of a reverse operation;
• a backward information transfer unit that transfers the input from the backward input unit;
• a bidirectional function operation unit that performs a forward logical operation using an input from the forward information transfer unit as an input signal in the case of a forward operation, and performs a backward logical operation using an input from the backward information transfer unit as an input signal in the case of a backward operation;
• a forward function transfer unit that transfers an output from the bidirectional function operation unit as a forward output in the case of a forward operation;
• the bidirectional function calculation unit includes two or more of the bidirectional function calculation units, The bidirectional logic element according to (1) or (2), wherein two or more of the bidirectional function operation units are connected in parallel or in series to function as one or more operation units that perform bidirectional operation.
• An arithmetic device including an adder and subtractor, and/or a multiplier and divider, in which the bidirectional logic elements described in (1) or (2) are connected in parallel or series.
• the arithmetic device including the multiplier and divider;
• the arithmetic device further comprising a zero divide processing unit that performs zero divide processing in division by setting the value to 1 if any of the dividends is 1, setting the value to 0 if all of the dividends are 0, and setting the divisor to 1 if the dividend is 1.
• the present invention provides a bidirectional logic element capable of performing calculations in both directions, as well as a calculation device and calculation method using the bidirectional logic element.
• FIG. 1 is a typical configuration diagram for explaining a bidirectional logic element according to an embodiment of the present invention.
• FIG. 1B is a diagram illustrating an example in which a pull-down element is added to the configuration of FIG. 1A.
• FIG. 10 is a diagram showing a list of representative operations of the bidirectional function operation unit.
• FIG. 10 is a diagram showing a list of representative operations of the bidirectional function operation unit.
• FIG. 10 is a diagram illustrating a configuration example of a transmission gate that realizes a bidirectional switch.
• 1 is a symbolic diagram of an Exclusive-OR (XOR) logic element.
• FIG. 1 is a circuit diagram of an Exclusive-OR (XOR) logic element.
• FIG. 1 is a more detailed circuit diagram of an Exclusive-OR (XOR) logic element.
• FIG. XOR Exclusive-OR
• FIG. 4 is a diagram showing an example in which a pull-down element is added to FIGS. 3B and 3C.
• FIG. 1 is a symbolic diagram of an AND logic element.
• FIG. 2 is a circuit diagram of an AND logic element.
• FIG. 1 is a symbolic diagram of a half adder/subtractor.
• FIG. 1 is a circuit diagram of a half adder/subtractor.
• FIG. 1 is a symbolic diagram of a full adder/subtractor.
• FIG. 1 is a circuit diagram of a full adder/subtractor.
• FIG. 1 is a symbolic diagram of an n-digit adder/subtractor.
• FIG. 1 is a circuit diagram of an n-digit adder/subtractor.
• FIG. 1 is a circuit diagram of an n-digit adder/subtractor.
• FIG. 1 is a symbolic diagram of a multiplier/divider.
• FIG. 1 is a symbolic diagram of a multiplier/divider.
• FIG. 1 is a circuit diagram of a multiplier/divider.
• FIG. 1 is a diagram illustrating the configuration concept of an n-digit multiplier/divider.
• FIG. 10 is a flow diagram of state allocation for a multiplier/divider.
• 8B is a diagram showing an example of a partial product of an n-digit multiplier/divider configured using the multiplier/divider shown in FIG. 8A.
• FIG. FIG. 1 is a conceptual diagram of an n-digit parallel multiplier/divider.
• FIG. 1 is a symbolic diagram of a redundant binary adder/subtractor.
• FIG. 10 is a diagram showing a truth table of a two-way XOR.
• FIG. 10 is a diagram showing a truth table of a two-way AND.
• FIG. 10 is a diagram showing a truth table of a bidirectional half adder/subtractor.
• FIG. 1 is a diagram showing a truth table of a bidirectional full adder/subtractor.
• FIG. 10 is a diagram illustrating a truth table of a multiplier/divider.
• FIG. 10 is a diagram showing a truth table of a three-state buffer.
• ⁇ Bidirectional logic element> 1A is a typical configuration diagram for explaining a bidirectional logic element according to one embodiment of the present invention.
• the bidirectional logic element of this embodiment includes function/inverse function control units 1 and 1', a forward input unit 2, a forward information transfer unit 3, a backward input unit 5, a backward information transfer unit 3', a bidirectional function calculation unit 4, a forward function transfer unit 7, and a backward function transfer unit 6.
• the function/inverse function control units 1, 1' are configured to control the direction of operation of the logic elements, switching between functions, which are forward operations, and inverse functions, which are reverse operations.
• the forward input unit 2 is configured to perform input for forward calculations.
• the forward information transmission unit 3 is configured to transmit input from the forward input unit 2 (to the bidirectional function calculation unit 4 in the example of Figure 1A).
• the bidirectional function calculation unit 4 is configured to perform forward logical calculations using the input from the forward information transmission unit 3 as the input signal in the case of forward calculations.
• the reverse direction input unit 5 is configured to perform input for reverse calculations.
• the bidirectional function calculation unit 4 is also configured to perform reverse logical calculations using the input from the reverse information transmission unit 3' as the input signal in the case of reverse calculations.
• the reverse direction function transfer unit 6 is configured to transfer the output from the bidirectional function calculation unit 4 in the reverse direction as a reverse direction output.
• 1B is a diagram showing an example in which pull-down elements are added to the configuration of FIG. 1A.
• pull-down elements 31 and 31' are respectively arranged between the forward information transfer unit 3 and the bidirectional function operation unit 4, and between the backward information transfer unit 3' and the bidirectional function operation unit 4.
• These pull-down elements 31 and 31' can ground an open path generated in the bidirectional function operation unit 4 at the output unit, thereby reducing stray capacitance.
• the bidirectional function calculation unit 4 further includes zero-divide processing units 41 and 41'. The zero-divide processing units will be described later.
• FIGS. 2A and 2B show a list of representative operations of the bidirectional function calculation unit.
• the logical operations of the bidirectional function calculation unit 4 can be, for example, AND, NAND, OR, NOR, XOR, XNOR, and NOT, but are not limited to these examples.
• the bidirectional function calculation unit 4 is controlled to switch between a function, which is a forward operation, and an inverse function, which is a reverse operation. Symbols are shown in general except for "In/Out.”
• FIGS. 2A and 2B shows a truth table, but both the function and the inverse function are the same as a standard truth table.
• the fourth column of FIGS. 2A and 2B shows an example of a circuit diagram capable of executing each logic for a function (or inverse function).
• the fifth column of FIGS. 2A and 2B shows a circuit diagram expanded from the circuit diagram in the fourth column to have bidirectional functionality.
• the configuration is a bidirectional logic element, but it is also possible to configure and implement a unidirectional logic element so that it can be selected in both directions.
• the dashed lines in the third to fifth columns when the input B, which is the operand, is a value of "0," the path of the operand A may become open.
• Figure 2C shows an example configuration of a transmission gate that realizes a bidirectional switch.
• the bidirectional switch is configured using pMOS enhancement transistors and nMOS enhancement transistors.
• control signals are input to the gates of the pMOS enhancement transistor and nMOS enhancement transistor.
• the sources and drains of the pMOS enhancement transistor and nMOS enhancement transistor are connected to each other. This enables logical operations such as those shown in the truth table.
• 3A is a symbolic diagram of an Exclusive-OR (XOR) logic element.
• XOR Exclusive-OR
• FIG. 3B is a circuit diagram of an Exclusive-OR (XOR) logic element
• FIG. 3C is a more detailed circuit diagram of the Exclusive-OR (XOR) logic element.
• this logic element includes function/inverse function control units 1, 1', a forward input unit 2, a forward (inverse) logic information transfer unit 3 (3'), a bidirectional function calculation unit 4, a forward function transfer unit 7, a backward input unit 5, and a backward function transfer unit 6.
• the function/inverse function control sections 1, 1 control the direction of operation of the logic elements to switch between the function function and the inverse function function.
• the function/inverse function control unit 1 has a three-state buffer that controls the forward direction (on the lower left side of the figure) and a three-state buffer that controls the reverse direction (on the upper left side of the figure).
• the control signal is Normal (High)
• the three-state buffer that controls the forward direction is turned on (signal transmission state) and the three-state buffer that controls the reverse direction is turned off (disconnection state Z: High Impedance), causing signal A to be input to the forward direction input unit 2.
• the forward direction three-state buffer is turned off and the reverse direction three-state buffer is turned on, causing signal A to be output to the left of the figure.
• the function/inverse function control unit 1' has a forward tri-state buffer (on the upper right side of the figure) and a reverse tri-state buffer (on the lower right side of the figure).
• the control signal is Normal (High)
• the forward tri-state buffer is turned on and the reverse tri-state buffer is turned off, so that a signal is output from the forward function transfer unit 7 to the right of the figure as signal S.
• the forward tri-state buffer is turned off and the reverse tri-state buffer is turned on, so that signal S is input to the reverse input unit 5.
• the direction of operation of the logic element can be switched.
• the function/inverse function control units 1, 1' are not output as bus coupling to control the forward and reverse outputs, they are coupled with high impedance to avoid the influence of the function/inverse function selection.
• the forward function transfer unit 7 transfers the outputs S1 , S2 from the bidirectional function operation unit 4 as a forward output S (in this example, two wires are combined into one wire).
• the truth table is shown in FIG. 10.
• the forward function transfer unit 7 is configured by an OR circuit, as shown in FIG. 3B.
• FIG. 3C shows details of an OR circuit for converting two-wire logic to single-wire logic, and as an example, the OR circuit can be configured by a circuit as shown.
• the backward function transfer unit 6 transfers the outputs A R 1 and A R 2 from the bidirectional function operation unit 4 as the backward output A R (in this example, combining the two wires into one wire) when a Reverse (Low) control signal is input to the function/inverse function control units 1 and 1 ' and the direction of operation of the logic element is reversed.
• the truth table can be obtained by replacing the input A in the truth table shown in FIG. 10 with S and the output S with A R.
• the backward function transfer unit 6 is configured with an OR circuit, as shown in FIG. 3B.
• FIG. 3C shows details of an OR circuit for converting two-wire logic to single-wire logic, and as an example, the OR circuit can be configured with a circuit as shown.
• 3E is a symbolic diagram of an AND logic element.
• N/R has been added to indicate switching between forward and reverse operations
• N stands for “Normal,” which indicates the forward direction
• R stands for "Reverse,” which indicates the reverse direction
• inputs are represented by “A” and “B”
• output is represented by "P”
• PR inputs
• AR output is represented by " AR .”
• Figure 3F is a circuit diagram of an AND logic element. As shown in Figure 3F, this logic element includes function/inverse function control units 1, 1', a forward input unit 2, information transmission units 3, 3', a bidirectional function calculation unit 4, a forward function transmission unit 7, a backward input unit 5, and a backward function transmission unit 6.
• the function/inverse function control units 1, 1', forward input unit 2, forward function transfer unit 7, backward input unit 5, and backward function transfer unit 6 are the same as in the XOR example, so a repeated explanation will be omitted and only the information transfer units 3, 3' and bidirectional function calculation unit 4 will be explained.
• FIG. 11 shows a truth table of AND in the bidirectional function calculation unit 4.
• the gate of the first transmission gate is turned off and the gate of the second transmission gate is also turned off, so that the output S becomes "0".
• the gate of the first transmission gate is turned off and the gate of the second transmission gate is turned on, so that the output S is "0".
• the gate of the first transmission gate is turned on and the gate of the second transmission gate is turned off, so that the output S is "0”.
• the gate of the first transmission gate is turned on and the gate of the second transmission gate is also turned on, so that the output S becomes "1".
• the bidirectional function operation unit 4 has an AND logical operation function.
• the gate of the first transmission gate is turned off and the gate of the second transmission gate is also turned off, so that the output AR is "0".
• the gate of the first transmission gate is turned off and the gate of the second transmission gate is turned on, so that the output AR is "0".
• the gate of the first transmission gate is turned on and the gate of the second transmission gate is turned off, so that the output AR is "0".
• the gate of the first transmission gate is turned on and the gate of the second transmission gate is also turned on, so that the output AR becomes "1". In this way, even in the case of the reverse direction, the bidirectional function operation unit 4 has an AND logical operation function.
• the bidirectional function calculation unit 4 is preferably configured using branch-type logic elements. In particular, it is preferable that the bidirectional function calculation unit 4 be configured using transmission gates.
• the bidirectional function calculation unit 4 preferably uses two-rail logic. However, in the present disclosure, the bidirectional function calculation unit 4 may also use one-rail logic. In the present disclosure, it is also preferable that the bidirectional logic element has two or more bidirectional function calculation units 4, and that the two or more bidirectional function calculation units 4 are connected in parallel or in series to function as one or more calculation units that perform bidirectional calculations.
• FIG. 4A is a symbolic diagram of a half adder/subtractor (half adder and subtractor). Similar to a typical half adder/subtractor, it is basically configured with a parallel connection of an XOR that receives two inputs A and B and outputs an output S (sum), and an AND circuit that receives two inputs A and B and outputs an output Cout (carry). Because the XOR uses the bidirectional XOR logic element described above, “N/R” is added to indicate switching between forward and reverse operation. Here, “N” stands for “Normal,” indicating the forward direction, and “R” stands for "Reverse,” indicating the reverse direction. Here, the forward direction represents addition, and the reverse direction represents subtraction. The inputs for the forward direction are represented by “A” and “B,” and the outputs by “S” and “Cout.” The inputs for the reverse direction are represented by “S R “ and “B,” and the outputs by "A R “ and “Cout.”
• Figure 4B is a circuit diagram of a half adder/subtractor.
• the half adder/subtractor shown in Figure 4B differs from Figure 3A in that, as can be seen from the difference in symbols between Figure 3A and Figure 4A, an AND circuit is provided in parallel to the bidirectional XOR circuit shown in Figure 3B.
• inputs A and B are also input to the AND circuit.
• the output of the AND circuit is Cout, which corresponds to the carry output.
• the parts common to the circuit in Figure 3B have already been explained, so a repeated explanation will be omitted.
• FIG. 12 shows the truth table for a bidirectional half adder/subtractor.
• (Forward direction) When input A is 0 and input B is 0, output S of the XOR circuit is 0, as in Fig. 3B. Also, output Cout of the AND circuit is 0. 3B.
• output S of the XOR circuit When input A is 0 and input B is 1, output S of the XOR circuit is 1, as in FIG. 3B.
• output S of the XOR circuit is 1, as in FIG.
• output S of the XOR circuit is 0, as in Fig. 3B.
• output Cout of the AND circuit is 1.
• the bidirectional half adder/subtractor has the logic operation function of a half adder/subtractor.
• the logic element shown in Figure 4B uses a bidirectional function calculation unit to switch between forward and reverse calculations, making it possible to perform a specified calculation (half addition/subtraction) in both directions.
• FIG. 5A is a symbolic diagram of a full adder/subtractor (full adder and subtractor). Like a normal full adder/subtractor, it can be constructed using two half adders/subtractors and an OR circuit (connected in the same way as a normal full adder/subtractor is constructed). This differs from a normal full adder/subtractor in that the two half adders/subtractors are bidirectional half adders/subtractors using the bidirectional XOR described above. For this reason, "N/R” has been added to indicate switching between forward and reverse operations.
• N stands for “Normal,” indicating the forward direction
• R stands for "Reverse,” indicating the reverse direction.
• the forward direction represents addition
• the reverse direction represents subtraction.
• the inputs for the forward direction are represented by “A” and “B,” and the outputs are represented by the sum “S” and carry “Cout.”
• the inputs for the reverse direction are represented by “ SR “ and “B,” and the outputs are represented by " AR " and "Cout.”
• FIG. 13 shows the truth table for a bidirectional full adder/subtractor. (Forward direction) When input A is 0, input B is 0, and input Ci is 0, the output of the preceding XOR circuit and the output of the succeeding XOR circuit are both 0, so S is 0. Furthermore, the output of the preceding AND circuit is 0, and the output of the succeeding AND circuit is also 0, so Cout is 0. When input A is 0, input B is 0, and input Ci is 1, the output of the preceding XOR circuit is 0 and the output of the succeeding XOR circuit is 1, so S becomes 1. Also, the output of the preceding AND circuit is 0 and the output of the succeeding AND circuit is also 0, so Cout becomes 0.
• the output of the AND circuit in the previous stage is 0 and the output of the AND circuit in the next stage is also 0, so Cout is 0.
• input S R is 1, input Ci is 0, and input B is 1, the output of the front-stage XOR circuit is 1 and the output of the rear-stage XOR is 0, so A R becomes 0.
• the output of the front-stage AND circuit is 0 and the output of the rear-stage AND circuit is 0, so Cout becomes 0.
• input S R is 0, input Ci is 1, and input B is 1, the output of the XOR circuit in the previous stage is 1 and the output of the XOR circuit in the next stage is 0, so A R is 0.
• the output of the AND circuit in the previous stage is 0 and the output of the AND circuit in the next stage is 1, so Cout is 1.
• the logic element shown in Figure 5B uses a bidirectional function calculation unit to switch between forward and reverse calculations, making it possible to perform a specified calculation (full addition/subtraction) in both directions.
• Figure 6A is a symbolic diagram of an n-digit adder/subtractor.
• Figure 6B is a circuit diagram of an n-digit adder/subtractor.
• the control of the addition (Add)/subtraction (Subtract) can be switched in relation to the forward (N)/reverse (R) control of Figure 1A, just like a full adder.
• An example of the configuration of an n-digit adder/subtractor using the bidirectional logic elements disclosed herein can be achieved by connecting in the same way as when implementing a normal n-digit full adder/subtractor.
• Various carry methods, such as the look-ahead carry method are available for high-speed carry execution, and these can be applied.
• Figure 7A is a symbolic diagram of a multiplier/divider (multiplication and division circuit).
• Figure 7B is a circuit diagram of a multiplier/divider. As shown in Figure 7A, the multiplier/divider can be implemented using the bidirectional AND element described above.
• Figure 14 shows the truth table for the multiplier/divider. Information loss in the AND circuit is corrected by precharging it to "1" in Figure 8A.
• FIG. 8A is a diagram showing the configuration concept of an n-digit multiplier/divider.
• "M/D” in the diagram indicates switching between multiplication and division.
• the "M/D" portion in the diagram corresponds to switching between the zero-divide processing units 41 and 41' in FIG. 1B, and its control can be switched in relation to the forward (N)/reverse control (R) in FIG. 1B. Since the least significant digit does not have a carry, multiplication can be calculated using only AND elements. For division, the operand a0 is obtained from this, and arithmetic operations are performed based on this, and the most significant digits are calculated in parallel to obtain the quotients b0 to bn . However, by mathematical definition, zero-divide processing is required when the dividend a0 or divisor b0 is "0.” Furthermore, it is also possible to confirm that the carry in multiplication and that in division are the same.
• Figure 8C is a diagram showing an example of a partial product of an n-digit multiplier/divider configured using the multiplier/divider shown in Figure 8A.
• Figure 8D is a conceptual diagram of an n-digit parallel multiplier/divider. The area surrounded by the two-dot chain line in the figure is where the aforementioned divide-by-0 processing is performed.
• Figure 9 is a symbolic diagram of a redundant binary adder/subtractor (redundant binary adder and subtractor).
• redundant binary the operands are coded, making the inverse operation complicated.
• calculations can be performed as easily as with a general bidirectional arithmetic element.
• the configuration of the addition/subtraction elements is shown symbolically, but multiplication/division can be configured using AND elements and half adders, so the bidirectional addition/subtraction or multiplication/division techniques described above can be implemented in the same way by substituting these elements.
• the arithmetic unit of the present disclosure may include adders and subtractors and/or multipliers and dividers in which the bidirectional logic elements described above are connected in parallel or in series.
• the arithmetic device of the present disclosure preferably includes the above-mentioned multiplier and divider, and further includes a zero divide processing unit that performs zero divide processing in division by setting the value to 0 if any of the dividends is 0, setting the value to 1 if all of the dividends are 1, and setting the divisor to 1 if the dividend is 1.
• the computing method of the present disclosure uses the bidirectional logic elements described above to perform bidirectional computations.
• the bidirectional logic element comprises a bidirectional function calculation unit that is constructed using transmission gates and two-rail logic.
• the method disclosed herein is a realistic, optimal, and effective method for realizing two-variable functions/inverse functions. Furthermore, by combining these with multiple variables or multiple stages, it is possible to synthesize functions equivalent to those of widely used gate-type logic elements, and in addition, it is possible to realize inverse function calculations.
• a bidirectional function calculation unit can be configured using dual-rail logic; for example, a full adder can be configured by connecting two half adders.
• a parallel multiplier/divider can save area when the second digit is integrated by combining a multiplier/divider unit with a full adder. Furthermore, this can also detect errors in calculations or inverse calculations.
• the present disclosure can also be applied to floating-point operations and redundant binary operations, enabling faster operations with a smaller area.
• the disclosed method can particularly utilize the relationship between function and inverse function to combine addition/subtraction and multiplication/division into a single operation. Multiplication/division, which require parallel processing for high speed, can be performed at high speeds, with significant reductions in integrated area, number of elements, and power consumption.
• the bidirectional logic element disclosed herein is suitable for arithmetic operations.
• arithmetic operations derive a result from two values: the operand and the operand.
• it is compatible with bidirectional logic elements and can be implemented efficiently, quickly, and simply.
• it can also be applied to high-speed algorithms or redundant binary notation, such as high-speed carry, which are already in practical use.
• Number representations used in computer calculations include fixed-point and floating-point representations, and operations in floating-point format consist of a mantissa and an exponent, with the mantissa being calculated by multiplication/division and the exponent being calculated by addition/subtraction.
• This disclosure can also be performed by combining similar operations.
• bidirectional logic elements can perform general logic function calculations, and can also perform inverse calculations of one variable.
• the four arithmetic operations of addition/subtraction and multiplication/division are in a relationship of calculation/inverse operation, respectively, and can be realized with approximately half the integrated area and power consumption.
• the inverse function can be obtained directly, a simple calculation method can be provided without the need for complex hardware algorithms. Furthermore, this method can also be applied to conventional hardware algorithms.
• each unit is configured to be bidirectional, and one or more of these are combined to perform bidirectional calculations as a whole device. Furthermore, in a configuration where multiple units are combined in parallel or series, each unit other than the combined bidirectional calculation unit can be configured as a single unit as a whole device.
• the technique disclosed herein can also be realized by using two sets of conventional elements to make it bidirectional.
• the disclosed method does not require a trial-and-error approach to division when there are no partial products in multiplication.

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