CN120418955A - 布线电路基板、电气要素安装基板、电子设备、布线电路基板的制造方法、以及电气要素安装基板的制造方法 - Google Patents

布线电路基板、电气要素安装基板、电子设备、布线电路基板的制造方法、以及电气要素安装基板的制造方法

Info

Publication number
CN120418955A
CN120418955A CN202380088894.1A CN202380088894A CN120418955A CN 120418955 A CN120418955 A CN 120418955A CN 202380088894 A CN202380088894 A CN 202380088894A CN 120418955 A CN120418955 A CN 120418955A
Authority
CN
China
Prior art keywords
circuit board
wired circuit
insulating layer
layer
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202380088894.1A
Other languages
English (en)
Chinese (zh)
Inventor
石井淳
藤林征宏
榎木雅人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Publication of CN120418955A publication Critical patent/CN120418955A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H05K3/4655—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern by using a laminate characterized by the insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
CN202380088894.1A 2022-12-28 2023-12-28 布线电路基板、电气要素安装基板、电子设备、布线电路基板的制造方法、以及电气要素安装基板的制造方法 Pending CN120418955A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2022211280A JP2024094620A (ja) 2022-12-28 2022-12-28 配線回路基板、電気的要素実装基板、配線回路基板の製造方法および電気的要素実装基板の製造方法
JP2022-211280 2022-12-28
PCT/JP2023/047178 WO2024143520A1 (ja) 2022-12-28 2023-12-28 配線回路基板、電気的要素実装基板、電子機器、配線回路基板の製造方法および電気的要素実装基板の製造方法

Publications (1)

Publication Number Publication Date
CN120418955A true CN120418955A (zh) 2025-08-01

Family

ID=91717949

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202380088894.1A Pending CN120418955A (zh) 2022-12-28 2023-12-28 布线电路基板、电气要素安装基板、电子设备、布线电路基板的制造方法、以及电气要素安装基板的制造方法

Country Status (5)

Country Link
JP (1) JP2024094620A (https=)
KR (1) KR20250130328A (https=)
CN (1) CN120418955A (https=)
TW (1) TW202435372A (https=)
WO (1) WO2024143520A1 (https=)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3287310B2 (ja) * 1998-06-30 2002-06-04 カシオ計算機株式会社 半導体装置及びその製造方法
JP2000349198A (ja) * 1999-04-02 2000-12-15 Nitto Denko Corp チップサイズパッケージ用インターポーザ及びその製造方法と中間部材
JP2002223050A (ja) * 2001-01-29 2002-08-09 Hitachi Metals Ltd 複合金属板、ビルドアップコア基板、ビルドアップ配線基板、及びその製造方法
JP2006186321A (ja) * 2004-12-01 2006-07-13 Shinko Electric Ind Co Ltd 回路基板の製造方法及び電子部品実装構造体の製造方法
JP2016039285A (ja) * 2014-08-08 2016-03-22 イビデン株式会社 プリント配線板の製造方法
JP7357436B2 (ja) * 2017-04-10 2023-10-06 日東電工株式会社 撮像素子実装基板、その製造方法、および、実装基板集合体
JP2018207082A (ja) * 2017-06-09 2018-12-27 イビデン株式会社 リジッドフレキシブル配線板およびその製造方法

Also Published As

Publication number Publication date
JP2024094620A (ja) 2024-07-10
TW202435372A (zh) 2024-09-01
KR20250130328A (ko) 2025-09-01
WO2024143520A1 (ja) 2024-07-04

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