CN1203455A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN1203455A
CN1203455A CN98105169A CN98105169A CN1203455A CN 1203455 A CN1203455 A CN 1203455A CN 98105169 A CN98105169 A CN 98105169A CN 98105169 A CN98105169 A CN 98105169A CN 1203455 A CN1203455 A CN 1203455A
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lead
semiconductor device
semiconductor element
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福永英树
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Mitsubishi Electric Corp
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Abstract

获得能够大幅度地减小安装面积,提高稳定性及可靠性,在制造方面合格率高的半导体装置。把功能不同的矩形半导体元件A1及半导体元件B2装于电分离的管芯底座3及4上,用树脂将其密封而成为单一的封装体6。把悬挂引线5a及5b设置在封装体6的长边一侧及短边一侧上,把管芯底座3及4在至少3个边的方向上悬挂起来。

Description

半导体装置
本发明涉及树脂密封式半导体装置，特别是，涉及把多个半导体元件装于1个封装体中的半导体装置。
迄今，把功能不同的两种半导体元件(例如，SRAM和快速存储器(flash memory))分别装于不同的IC封装体中，从半导体制造商发货。因此，最终产品，例如携带电话等小型电子设备的制造商分别购入这些封装体，将其分别安装到产品的母板上。
近年来，伴随着电子设备的小型化，提出了不少用于谋求减小半导体封装体安装面积的提案。例如，在特开平1-308058号公报、特开平4-119640号公报等中，提出了把多个半导体元件装于1个封装体中的半导体装置。图4为示出特开平1-308058号公报中现有的树脂密封式DIP.IC的横剖面图。图4中，10为DIP.IC(电子装置)，11表示第1片状器件(pellet)，12表示第2片状器件，13表示键合线，14表示树脂密封式封装体，15A、15B表示悬挂座片(tab)的引线，16A、16B表示座片，17表示引线，17a表示内部引线，17b表示外部引线，17c表示共用内部引线，18表示键合层。配置在封装体中央部上的悬挂座片的引线15A及15B的前端各以直线状连接到形成了长方形平板的座片16A及16B，将其分别成为整体地悬挂起来。在本现有例中，具备内部制成了发挥所需功能的电子电路的多个片状器件11及12，在将其分别键合到座片16A及16B的状态下把这些片状器件以树脂密封方式封装到单一的封装体中，构成作为把多功能一体化了的系统的电子装置。
如上所述，迄今在把现有功能不同的两种半导体元件安装为一组的情况下，因为必须分别安装两个封装体，所以，安装面积必须大，存在不能对应携带电话等电子设备中要求小型化的问题。
还有，在把多个半导体元件装于一个封装体上的半导体装置中，虽然可以谋求缩小安装面积，但由于在制造封装体时所使用的引线框架具有多个管芯底座(die pad)(座片)，存在着管芯底座倾斜等制造方面的不合格品增多的问题。在上述特开平1-308058号公报中提出了的半导体装置中，因为悬挂引线框架的座片16A及16B的座片悬挂引线15A及15B分别只设置在座片一个边的方向上，所以，可以认为，在座片的稳定性方面存在问题。还有，在特开平4-119640号公报中，提出了在引线框架上形成两个岛、用绝缘电路基板将这些岛连系起来、把半导体元件装于各自的岛上的结构，但是，把岛以二点方式支撑在外框上，存在倾斜的可能性。
本发明是为了消除上述那样的问题而提出的，其目的在于获得能够大幅度地减小安装面积，提高稳定性及可靠性，在制造方面合格率高的半导体装置。
与本发明有关的半导体装置包括：功能不同的两个矩形半导体元件；分别装有这些半导体元件的电分离的两个管芯底座；连接到该管芯底座上并悬挂小片结合的悬挂引线和把半导体元件与外部连接端子连接起来的引线；用树脂把半导体元件、管芯底座、悬挂引线及引线的一部分密封起来作为单一封装体的半导体装置中，把悬挂引线设置在封装体长边一侧及短边一侧上，把管芯底座在至少3个边的方向上悬挂起来。
还有，在封装体的全部4个边上至少设置两条以上的悬挂引线。
还有，悬挂引线在封装体内迂回延伸。
进而，把悬挂引线连接到不需要与半导体元件进行电连接的外部连接端子。
还有，作为半导体元件采用快速存储器及SRAM。
图1为示出作为本发明实施例1的半导体装置的平面图；
图2为示出作为本发明实施例1的半导体装置的最终产品中的安装面积削减效果的图；
图3为示出作为本发明实施例2的半导体装置的平面图；
图4为示出现有半导体装置的横剖面图。
实施例1
下面，就附图说明本发明的实施例1。图1(a)及1(b)为示出作为本发明实施例1的半导体装置TSOP(Thin Small-OutlinePackage薄的小外形封装)(II)及TSOP(I)的平面图。图中，6为本实施例的半导体装置、即半导体封装体，1及2分别为功能不同的矩形半导体元件A及B。3及4为分别装有半导体元件A1及半导体元件B2的管芯底座，这些管芯底座3及4是电分离的。5为利用键合线把半导体元件A1与半导体元件B2连接起来以后把半导体元件A1及半导体元件B2与外部连接端子连接起来的引线；5a表示与管芯底座3及4中某一个连接起来以后在半导体封装体6的长边一侧延伸的悬挂引线；5b表示与管芯底座3及4中某一个连接起来以后在半导体封装体6的短边一侧延伸的悬挂引线。本实施例半导体封装体6的特征在于，把悬挂引线5a及5b设置在封装体长边一侧及短边一侧上，把装有半导体元件A1及半导体元件B2的管芯底座3及4在至少3个边的方向上悬挂起来。
图2示出本实施例半导体封装体6中减小安装面积的效果。图2示出在本发明实施例1的半导体封装体6中，作为半导体元件A1装了快速存储器，作为半导体元件B2装了SRAM。图2(a)示出在利用现有方法的两个不同封装体进行安装的情况，分别需要160mm2及240mm2，共计需要安装面积400mm2。图2(b)示出在通过本实施例利用1个封装体的情况下，其安装面积为223mm2，与以往相比，可谋求减小44％左右的安装面积。通过使用本实施例的半导体封装体，因为最终产品的制造商能够减小安装面积，可以使产品小型化，进而，因为只安装1个封装体即可，所以，可以缩短工序及降低成本，提高生产性。
如上所述，根据本实施例，把悬挂引线5a及5b分别设置在半导体封装体6的长边一侧及短边一侧上，以便把装有矩形半导体元件A1及半导体元件B2的管芯底座3及4在至少3个边的方向上悬挂起来，因此，能够抑制在组装工序时管芯底座的移动，能够稳定地进行制造。还有，如果增加悬挂引线5a及5b条数的话，就更有效。即，通过在半导体封装体6的全部4个边上至少设置两条以上的悬挂引线5a及5b，可以获得制造方面安全性及可靠性高的半导体封装体6。
实施例2
图3为本发明实施例2、即半导体装置的平面图。图中，对同一或相当部分标以同一符号，省略其说明。在本实施例中，使悬挂引线5c从管芯底座3及4向封装体6的短边一侧引出后，在封装体6内迂回延伸，连接到封装体6长边一侧。图3中，把悬挂引线5c连接到不需要来自半导体元件A1及B2的电信号的外部端子(未图示)上。即，使用不需要与半导体元件A1及半导体元件B2进行电连接的引线5作为悬挂引线5c。
根据本实施例，通过使悬挂引线5c在封装体内迂回延伸，设置在制造半导体封装体6时使被使用的模塑树脂流动的间隙，从而提高组装的模塑工序时的树脂流动性。还有，通过把悬挂引线5c连接到不需要来自半导体元件A1及半导体元件B2的电信号的外部连接端子上，能更加有效且更加稳定地进行组装。
如上所述，根据本发明，把功能不同的两个半导体元件作成单一的封装体，把悬挂引线设置在封装体的长边一侧及短边一侧上，以便把装有半导体元件的管芯底座在至少3个边的方向上悬挂起来，因此，可以获得制造方面不合格率低的稳定的半导体装置，在使用了这种半导体装置的产品中，能够大幅度地削减安装面积，可以谋求产品的小型化，可以进一步缩短工序及实现低成本化，提高生产性。

Claims (5)

1.一种半导体装置，包括：
功能不同的两个矩形半导体元件；
分别装有所述半导体元件的、电分离的两个管芯底座；
连接到所述管芯底座上来悬挂所述管芯底座的悬挂引线；以及
把所述半导体元件与外部连接端子连接起来的引线，
该装置中用树脂把所述半导体元件、所述管芯底座、所述悬挂引线及所述引线的一部分密封起来而成为单一封装体，
其特征在于：
把所述悬挂引线设置在所述封装体长边一侧及短边一侧上，所述悬挂引线悬挂所述管芯底座的至少3个边的方向。
2.根据权利要求1中所述的半导体装置，其特征在于：在所述封装体的全部4个边上，至少设置两条以上的所述悬挂引线。
3.根据权利要求1或2中所述的半导体装置，其特征在于：所述悬挂引线在所述封装体内迂回延伸。
4.根据权利要求1或2中所述的半导体装置，其特征在于：把所述悬挂引线连接到不需要与所述半导体元件进行电连接的外部连接端子上。
5.根据权利要求1或2中所述的半导体装置，其特征在于：所述半导体元件为快速存储器及SRAM。
CN98105169A 1997-06-19 1998-03-30 半导体装置 Pending CN1203455A (zh)

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JP9162641A JPH1117100A (ja) 1997-06-19 1997-06-19 半導体装置

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CN106298723A (zh) * 2015-05-13 2017-01-04 无锡华润安盛科技有限公司 一种双岛引线框框架

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US7800205B2 (en) * 2005-09-01 2010-09-21 Avago Technologies General Ip (Singapore) Pte. Ltd. Quad flat pack (QFP) package and flexible power distribution method therefor
US7902655B1 (en) 2006-08-15 2011-03-08 Marvell International Ltd. Multichip package leadframe including electrical bussing
US7791191B2 (en) * 2006-12-28 2010-09-07 Sandisk Corporation Semiconductor device having multiple die redistribution layer
US7560304B2 (en) * 2006-12-28 2009-07-14 Sandisk Corporation Method of making a semiconductor device having multiple die redistribution layer
US8067825B2 (en) * 2007-09-28 2011-11-29 Stats Chippac Ltd. Integrated circuit package system with multiple die
JP5634033B2 (ja) 2008-08-29 2014-12-03 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 樹脂封止型半導体装置とその製造方法
JP6143726B2 (ja) * 2008-08-29 2017-06-07 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 樹脂封止型半導体装置とその製造方法、リードフレーム

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JPH01308058A (ja) 1988-06-06 1989-12-12 Hitachi Ltd 電子装置
JP2928611B2 (ja) 1990-09-11 1999-08-03 株式会社東芝 樹脂封止半導体装置
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JP3011510B2 (ja) * 1990-12-20 2000-02-21 株式会社東芝 相互連結回路基板を有する半導体装置およびその製造方法
JPH06151685A (ja) 1992-11-04 1994-05-31 Mitsubishi Electric Corp Ｍｃｐ半導体装置
JPH07142673A (ja) * 1993-11-15 1995-06-02 Matsushita Electric Ind Co Ltd 集積回路装置
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CN101369564B (zh) * 2007-08-15 2012-03-07 松下电器产业株式会社 半导体器件
CN106298723A (zh) * 2015-05-13 2017-01-04 无锡华润安盛科技有限公司 一种双岛引线框框架

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TW356595B (en) 1999-04-21
JPH1117100A (ja) 1999-01-22
KR100270756B1 (ko) 2000-11-01
US6483189B1 (en) 2002-11-19
KR19990006275A (ko) 1999-01-25

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