CN1201525A

CN1201525A - Ultrasonic testing (UT) system signal processing

Info

Publication number: CN1201525A
Application number: CN 96198153
Authority: CN
Inventors: R·L·迪克尔曼; M·A·卡梅尔林; S·L·克莱恩; M·圣·马丁; D·S·勒奥纳尔德
Original assignee: Combustion Engineering Inc
Current assignee: ABB CE Nuclear Power Inc
Priority date: 1995-09-18
Filing date: 1996-09-17
Publication date: 1998-12-09
Anticipated expiration: 2016-09-17
Also published as: CN1113237C; JP2002502492A; WO1997011364A1; AU7073196A; CA2231274A1

Abstract

An ultrasonic testing system can receive data from at least two ultrasonic transducers and process the data in parallel to each other. The testing system can compress the data by a fixed ratio by storing the value of the sample having the highest amplitude out of a group of samples. The testing system can also provide threshold-based run-length encoding by compressing data by only storing samples which exceed a user-defined threshold value as well as a user-defined range of samples surrounding said samples. The ultrasonic testing system also provides a hardware gate for storing a peak amplitude and associated time-of-flight for a user-defined interval and a gate for storing the time-of-flight for the first excursion of the data through a user-defined threshold and interval. The operation of these gates or the storage of waveform data may be delayed by a constant delay or until the data exceeds a user-selectable threshold during a user-selectable time interval. The system also provides a multi-channel design allowing simultaneous waveform and/or hardware gate acquisition of data on more than one channel and permitting the parallel processing of data.

Description

The signal Processing of Ultrasonic Detection (UT) system

The present invention generally relates to ultrasonic testing system, more particularly, relates to and is used for the ultrasonic testing system that noninvasive imaging detects, and this noninvasive imaging detects and adopted the A/D conversion that the sonac signal is converted into digital signal.

Known Noninvasive ultrasonic testing system has numerous purposes, for example, and the detection in crack and about the integrality of structure.Typical ultrasonic testing system has an independent analog data acquisition passage and has data-handling capacity.The simulated data that is received is converted to digital form and handled the simulated data that is received before being shown as image.Because sweep speed is preferably fast as much as possible, and because large-area scanning, a large amount of numerical datas will be stored and handle to ultrasonic testing system.But, crack and fault of construction only account for the sub-fraction of ultrasonic inspection probe scanning area usually, therefore, also just only account for the sub-fraction of all storage datas.Because data volume is very big, traditional ultrasonic testing system requires big storage capacity and strong processing power, and only is for minimum relevant data.

Except requiring big storage capacity and strong processing power, storage and deal with data amount are very big, make to be difficult to usefulness general calculation machine and software fast processing data.Therefore, a problem of the prior art is exactly to want sweep unit fast, and this just needs lot of data, when particularly needing certain data compression.

Although some ultrasonic testing system can hold more than one passage, these systems typically are transferred to the signal time-division multiplex of different passages together.These systems still require big storage area, and, because additional channel capacity is bigger usually, heavier and more expensive.But, the multi-channel detection system still is slow, and this is that Here it is, and they generally once only are converted to digital signal with a passage, and require general calculation machine hardware and software to handle a large amount of raw data owing to such fact.

The purpose of this invention is to provide a kind of ultrasonic testing system, this ultrasonic testing system can provide the realtime graphic of scanning area with the ratio of performance to price of excellence.

Another object of the present invention provides a kind of ultrasonic testing system that can compress the data in the ultrasonic transducer signal that is received.

Another object of the present invention provides a kind of ultrasonic testing system, and this ultrasonic testing system can compress the data in the ultrasonic transducer signal that is received, and can only store in the above skew of a certain threshold value near the maybe data of this skew.

Further purpose of the present invention provides a kind of ultrasonic detector, and this ultrasonic detector provides a kind of digital hardware gate circuit.

It is exactly data with upper channel of fast processing that the present invention also has a further purpose.

Other purpose of the present invention, advantage and novel characteristic will be described in the following description, and, when those of ordinary skills have read this explanation or implement when of the present invention, described these purposes, advantage and novel characteristic just can become obvious at once.Can realize and reach objects and advantages of the present invention by appending claims.

Reach aforementioned and other purpose, according to the present invention, as concrete and explained in general herein, a Ultrasonic Detection circuit has a pulsing circuit, and this pulsing circuit is with voltage signal excitation ultrasonic transducer and be used for from this transducer reception analog data signal.Analog to digital converter receives simulating signal, and is digital signal with this analog signal conversion.A timing circuit is determined to postpone and sampling interval.A counter circuit is determined the group number of digitalized data sampling, and is preferably 2 to 16, perhaps more.After the delay of appointment, a peak detector circuit obtains a peak value to each group digital data sampling.Then, store the peak value of each group, thus, Wave data is compressed, and preferably, is compressed into 2 to 16 times or higher.

According to another aspect of the present invention, sampling interval is defined as: during the scouting interval that the user determines, and the zero-time before the skew of the digitalized data more than the threshold value of determining by the user and such a period of time of concluding time afterwards.Ultrasonic testing system provide by this way numerical data based on threshold value, the inclined to one side sign indicating number of run length, with additional multiplying power packed data up to 128: 1.

And according to another aspect of the present invention, ultrasonic testing system provides the digital hardware gate circuit for storing some data.The hardware gate circuit can search for the ultrasonic transducer signal that received and for one by the amplitude of the determined interval storage of user peak value and polarity and travel-time relevant with this peak value at interval.Can be selectively, but hardware gate circuit search signal, and be stored in one by in the determined interval of user, corresponding to by one by travel-time of first skew of the signal of the determined threshold value of user at interval.Can postpone these gate circuits by the user in the determined time cycle at one, perhaps, but the delay waveform storage surpasses one by the determined threshold value of user up to transducer signal.

According to another aspect of the present invention, a ultrasonic testing system receives more than one simulating signal from each ultrasonic transducer.Data are converted to numerical data, the data from a transducer are delayed with respect at least one other transducer.By this way, can when carrying out other signal Processing, handle more than one data-signal, and can be fast, display result in real time.

By the detailed description of this instructions, and with accompanying drawing and the description taken in conjunction wherein write together, these and other some characteristic of the present invention will be clearly.

The description of drawings of an appended formation instructions part embodiments of the invention, and be used for illustrating principle of the present invention with instructions.

In the accompanying drawings:

Fig. 1 (comprising Figure 1A, 1B and 1C) is the block scheme of the ultrasonic testing system of the preferred embodiments of the present invention;

Fig. 2 (comprising Fig. 2 A, 2B, 2C, 2D, 2E and 2F) is the block scheme of A/D converter shown in Figure 1;

Fig. 3 (comprising Fig. 3 A, 3B, 3C, 3D, 3E and 3F) is the block scheme of a field programmable gate array (FPGA) shown in Figure 2;

Fig. 4 is the synoptic diagram of rectification circuit;

Fig. 5 (comprising Fig. 5 A, 5B, 5C and 5D) is the block scheme of video circuit shown in Figure 3;

Fig. 6 (comprising Fig. 6 A, 6B, 6C, 6D, 6E and 6F) is a block scheme of RLL circuit shown in Figure 3;

Fig. 7 (comprising Fig. 7 A, 7B, 7C, 7D, 7E and 7F) is a block scheme of FIFO WRIT circuit shown in Figure 3;

Fig. 8 (comprising Fig. 8 A, 8B, 8C and 8D) is a block scheme of PRESTORE circuit shown in Figure 7;

Fig. 9 (comprising Fig. 9 A, 9B, 9C, 9D, 9E and 9F) is the block scheme of comparer FPGA shown in Figure 2;

Figure 10 (comprising Figure 10 A, 10B, 10C, 10D, 10E and 10F) is a block scheme of travel-time COMPTOF circuit at interval relatively shown in Figure 9;

Figure 11 (comprising Figure 11 A, 11B, 11C and 11D) is the block scheme of timer FPGA shown in Figure 2;

Figure 12 (comprising Figure 12 A, 12B, 12C and 12D) is a block scheme of timer circuit shown in Figure 11;

Figure 13 (comprising Figure 13 A, 13B, 13C and 13D) is a block scheme of travel-time interval T OF circuit shown in Figure 12;

Figure 14 (comprising Figure 14 A and 14B) is a block scheme of ISA circuit shown in Figure 9;

Figure 15 (comprising Figure 15 A, 15B, 15C, 15D and 15E) is a block scheme of ISAOUT circuit shown in Figure 4;

Figure 16 (comprising Figure 16 A, 16B, 16C and 16D) is a block scheme of EVENCNT circuit shown in Figure 12;

Figure 17 (comprising Figure 17 A, 17B, 17C and 17D) is a block scheme of MC circuit shown in Figure 11;

Figure 18 (comprising Figure 18 A, 18B, 18C, 18D, 18E and 18F) is a block scheme of MCMASTER circuit shown in Figure 17; And

Figure 19 (comprising 19A, 19B, 19C and 19D) is block scheme of MCSLAVE circuit shown in Figure 17;

DETAILED DESCRIPTION OF THE PREFERRED

Describe the preferred embodiments of the present invention now in detail, an example of the preferred embodiment has been shown in the accompanying drawing.

With reference to Fig. 1, ultrasonic testing system 10 of the present invention comprises a CPU (central processing unit) (CPU) 9 that can be connected with many plug-in cards.Although there are 8 plug-in cards in the exemplary system 10 of Fig. 1, should understand, system 10 can have the plug-in card of more or less quantity.Every plug-in card comprises a pair of pulse producer and pre-amplification

circuit

12 and 14, and each of this paired pulses generator and pre-amplification circuit directly is connected with ultrasonic transducer 7.Each of pulse producer and pre-amplification

circuit

12 and 14 all has one can be with the pulsing circuit of high-voltage pulse excitation ultrasound transducer 7, and has one and can amplify from the pre-amplification circuit of ultrasonic transducer 7 resulting return signals.Pulse producer 12 and pre-amplification

circuit

12 and 14 produce the RF output signal, and this RF output signal is entered two-stage amplifier 16 by multiplication, and two-stage amplifier 16 has the output terminal that is connected with an A/D converter 18.Every plug-in card in the ultrasonic testing system 10 also comprises a grid control circuit 11, an isa bus interface circuit 13 and a power supply 15.System 10 also comprises a display 5 that is used for the reading scan result, although do not illustrate, also comprises any such as keyboard or the such suitable input media of Genius mouse.

Fig. 2 shows the more detailed figure of A/D converter 18.With reference to Fig. 2, make input signal RF IN pass through an operational amplifier 20 from amplifier 16, the level phase shift of this operational amplifier 20 is also amplified the RF input signal.The output of operational amplifier 20 is supplied with two analog input ends of an A/D converter 21.A/D converter 21 is A/D converters of 8 monolithic 50MS/s of a binary channels.When only using an A partly to export, A/D converter 21 has 50MS/s or lower sampling rate.Obtain the sampling rate of 100MS/s, just adopt the output on part and B part.The A of A/D converter 21 and B part all receive the sampling clock of 50MHz, and make the sampling clock pulse daley 10ns of B part with analog delay circuit 21 and 23.As a result, the B of A/D converter 21 part is sampled to RF input signal RF IN at the mid point of double sampling between the time of the A of A/D converter 21 part.By two 8 bit data streams of combination, can form the data stream of a 100MS/s from A and B part.In A/D converter 21, two part A and B have the transport property of coupling, and adopt 2 volts identical reference voltage.

Offering a field programmable gate array (FPGA) 25 from two the 8 bit data stream DA (0: 7) of A/D converter 21 and the output of DB (0: 7).At ripple FPGA25 place, according to data DA and DB carry out video filtrate and based on threshold value, run length coding, RLC (TRLE).A pair of advanced person-go out earlier (FIFO) storer 26 and 27 is in advance for to store some data based on the run length coding, RLC of threshold value, and a circuit 28 injects data stream to " 00h " control coding, is used for the run length coding, RLC based on threshold value.The second pair of

FIF0 storer

29 and 30 is used for the high speed storing Wave data, and after finishing the waveform storage, read by isa bus interface circuit 13.

Comparer FPGA32 and ripple FPGA25 receive simultaneously from the DA data stream that is not delayed of A/D converter 21 and the DB data stream that has been delayed.Comparer FPGA32 is output stream not, but determines the data stream DA that received from A/D converter 21 and the peak value the DB.Can read this peak value by FPDP DATA (0: 7) by CPU9.Comparer FPGA32 returns a timer FPGA33 control signal is provided, with the control travel-time at interval storage of (TOF) relevant with above-mentioned peak value.

Except storage travel-time interval, timer FPGA33 also has several other purposes.The system clock pulse of 50MHz is inswept continuously, can be by producing the pulse of a sampling enabling signal (SAMPLEN) selectively, change the speed of sampling and processing ultrasonic signal, can only store and handle in the one-period in N clock period so that make.Timer FPGA33 also is used for being connected with 36 with the static RAM (SRAM) 35 of two 8K * 8, be used for determining the scouting interval of a waveform acquisition interval and a hardware gate circuit, will illustrate in greater detail this waveform acquisition interval and and hardware gate circuit search interval below.Timer FPGA33 comprises a hardware gate circuit travel-time interval counter, some travel-time interval register and hyperchannel control circuit system, and these all will do more full and clear explanation below.

The video rectifier of ripple FPGA circuit 25 and filter segment can compress from the data that ultrasonic transducer received by the fixed proportion up to 16: 1.Have the sampled value of crest amplitude in the FPGA circuit 25 storage eight bit registers, represent amplitude for low 7, and the symbol of most significant digit representative data.The comparable analog form of ripple FPGA25 is recovered quickly, and this is because next " binit " do not covered by the discharge tail of common peak detctor.

With reference to Fig. 3, ripple FPGA25 comprises a pair of

register

41 and 42, makes the A/D data DA that is not delayed by register 41, and makes the data DB that is delayed by register 42.Make data from two

registers

41 and 42 input detecting circuits 43, afterwards, these data are defeated by rectifier and buffering LD device circuit RECTBUFF44, at circuit RECTBUFF44 place, to above-mentioned data rectification.

A/D converter 21 provides data DA and DB with the binary form of a kind of compensation, thereby makes 00h and those the most negative inputs of 01h representative, the centre of 80h representative data scope, and FEh and the most positive input of Ffh representative.

Fig. 4 shows an example of the rectification circuit of a position that is used for data-signal DA and DB.With reference to Fig. 4, the first order of rectifier is the complementary full wave rectifier of one 1 ' s and comprises logic gates D, E, F and N.If by the determined incoming symbol of data bit D7 is low, show that sampling is a negative, a traffic pilot N selects a kind of complementary type of input data.On the other hand, if be high by the determined incoming symbol of data bit D7, show that sampling is a positive number, traffic pilot N selects the input data that are not corrected.

The second level of rectifier makes can carry out positive half-wave or negative half-wave rectification and just full-wave rectification.This second level comprises a traffic pilot 0, is used for always selecting the output of traffic pilot M.Make the input end in the same way that feeds back to AND circuit B and C from the output of traffic pilot 0.AND circuit B and C also receive control signal INEGHALF and IPOSHALF respectively.When control signal INEG HALF and two of IPOSHALF are zero, the data of full-wave rectification do not change the second level by rectifier.On the other hand, if control signal INEGHALF equals 1, and control signal IPOSHALF equals 0, so, when input sample when negative, just with the zero data bit that replaces.Otherwise if control signal IPOSHALF equals 1, and control signal INEGHALF equals zero, and so, when input sample is timing, just replaces data bit with zero.Can finish the rectification of the plus or minus half-wave of input signal by this way.By means of the sign bit that comes retention data by most significant digit in the original input sample, that be called D7.Make those data stream and clock signal clk synchronous by d type flip flop formula register.

In rectifier and buffering LD device 44 by rectification after, two 8 bit data streams flow into video circuits 45.As illustrating in greater detail among Fig. 5, video circuit 45 comprises a counter 60, is used to count programmable a large amount of sampling period, so that determine a video start-up period (VIDEOEN).The video start-up period is the interval of the rectified signal of a search peak swing.

During operation, the first input data sampling or sampling binit in a video start-up period always are stored among the eight bit register PEAKREG61.Because when ultrasonic testing system 10 is worked with the sampling rate of 100MS/s, video circuit receives two data samplings 45 each clock cycle, relatively postpone and the size of delayed data samples not with middle comparator 64, middle comparator 64 signals for traffic pilot 66, select two samplings which be used for storage.

When second time of video start-up period and follow-up sampling thereof, respectively will be for the second time with

comparator circuit

63 and 65 or follow-up not delay and delay sampling and current peak value sampling compare.If delayed data or delayed data is not greater than the data that are stored in the peak value register 61, comparer 63 or 65 signals just for respectively peak value register PEAKREG61, so that the corresponding sampling of storage.When postponing and delayed data is not all greater than the data that are stored in the peak value storer 61, comparer 64 signals just for traffic pilot 66, so that bigger that in two samplings is provided for peak value register 61.Continue relatively to be stored in data sampling in the peak value register 61 and this process of data sampling of input, when sampling the first time in next video start-up period, at this moment, value from peak value register 61 is transferred to FIFOWRIT circuit 46 from video circuit 45, thereby makes this value can be used as the part of processed waveform and note.

As a result, ripple FPGA circuit 25 exportable data stream, the data rate of this data stream has reduced N doubly than input data rate, and here, N equals the ratio in video start-up period and whole sampling period.Therefore, the resolution of the time of surveying becomes has dredged N doubly, and this is to specify a sampling period binit arbitrarily owing to start peak value for each video, and has kept peak amplitude simultaneously.Ripple FPGA circuit 25 is finished above-mentioned logic function by carrying data with streamline, utilize some short crucial paths, adopting parallel logic optionally to cushion with essential speed.

Obtain higher resolution, the temporal information of a byte that can be by storing each waveform sampling or the part of a byte keeps the accurate travel-time at interval.Described temporal information is actually by an extra travel-time spacing bias that counter produced, and the counting sampling during each video starts the VIDEOEN cycle of this extra counter starts the SAMPLEN cycle.Travel-time interval T OF skew is inserted into data stream with peak-data.

As mentioned above, ripple FPGA circuit 25 also be used for based on threshold value, run length coding, RLC, and this compression ratio of data that ratio that can be different compression is received from ultrasonic transducer 7 is up to 128: 1, is generally 5: 1 to 20: 1.The data that ripple FPGA25 has an a certain amplitude by storage only finish based on threshold value, run length coding, RLC, this amplitude respectively down on and before top to bottm the threshold crossings and afterwards, with the selectable number of samples of user, surpass the selectable threshold value of user.By control coding 00h and LTT counting are directly injected data stream, will send as signal less than the gap length of threshold value (LTT) data.

With reference to Fig. 3, RLL circuit 47 receives the data of rectification from rectifier and buffering LD device circuit, and finishes the specific steering logic of major part based on the run length coding, RLC of threshold value.Do not contain the 00h value from rectifier and buffering LD device circuit data stream 44, rectification, and any 00h value of Lock-in is removed by testing circuit 43 in data stream, and replaces with 01h.Value 00h is kept as a kind of control coding, will arrive so that send the counting that signal indicating is lower than threshold value.

Fig. 6 understands RLL circuit 47 in more detail.In this figure, signal WAVEACT has reflected the desired waveform acquisition of user at interval.When signal WAVEACT equals 1, sample for waveform data by ripple FPGA circuit 25 records and/or compression.More particularly, in signal WAVEACT equals time interval of 1, the size and the programmable threshold value THRESHRLL of user of the waveform sampling of the rectification that is relatively received from rectifier and buffering LD device circuit 44 by a pair of comparer 70 and 71.If the amplitude of sampling is less than specified threshold value THRESHRLL, so Jue Dabufen sampling is not stored in waveform fifo circuit 29 and 30.73 pairs in a counter that is lower than threshold value is not counted by

fifo circuit

29 and 30 numbers of samples of being stored.When amplitude of wave form surpasses THRESHRLL, show that control coding 00h and a counting byte LTTCNT who is lower than threshold value of having how many samplings below threshold value can not go on record are injected into data stream, and the storage of beginning waveform.

But by the pre-stored-Jia-storage back counter 74 of a repeated trigger, setting will be stored in the minimum number of a waveform sampling in the group.In those interims that are lower than threshold value, and after storing after finishing, the output of counter 74 is 00h.In case recover the waveform storage, add the data value of PREPLUSPOST (0: 4) immediately with regard to the output of giving counter 74, and, before-Jia-counting PPPCNT (0: 7) beginning afterwards reduces counting towards 00h.If counter 74 arrives 00h, before a RLLORNOR circuit 75 causes-Jia-counting is waited until next skew more than threshold value afterwards.On the other hand, if before arriving 00h, detect skew more than threshold value, just give the counter 74 PREPLUSPOST counting of reloading immediately.As long as the output of counter 74 is not equal to 00h, the value of signal IRLLWAVEEN just equals 0, and makes waveform can be stored in waveform fifo circuit 29 and 30.Like this, generally speaking, ripple FPGA circuit 25 will be stored the waveform sampling of a certain quantity in

fifo circuit

29 and 30, described quantity be equal to or greater than each before the skew more than the determined threshold value THRESHRLL by the user-Jia-count afterwards PPCPNT.

With reference to Fig. 3, a control signal bus WRITELTT (0: 2) signal offers FIFOWRIT circuit 46 by RLL circuit 47, and those 0hh control codings that this control signal bus WRITELTT (0: 2) signal controlling among the counting LTTCNT that is lower than threshold value write in waveform fifo circuit 29 and 30.The unmodified Wave data of signal IRLLWAVEEN control writes in

waveform fifo circuit

29 and 30, simultaneously, makes this Wave data by FIFOWRIT circuit 46 before Wave data is input to shift register fifo circuit 26 and 27.As mentioned above, when signal WAVEAC equaled 1, Wave data flow through pre-stored fifo circuit 26 and 27 continuously.Illustrate in greater detail FIFOWRIT circuit 46 among Fig. 7, further show a pre-stored circuit 80 among Fig. 8 particularly and be positioned at FIFOWRIT circuit 46.Pre-stored circuit 80 produces some outputs, these outputs controlling pre-stored fifo circuit 26 and 27 those read to enable-write enable line, thereby data are write

fifo circuit

29 and 30, and this writing is that four to 16 sampling times before reading described data by

waveform fifo circuit

29 and 30 are to carrying out.By before reading of data right data storage of a large amount of sampling times in shift register fifo circuit 26 and 27,

waveform fifo circuit

29 and 30 just can be stored those data older with respect to the time of threshold crossings, pre-stored data thus.

81 pairs of character code sums of being stored during the single waveform of collection of WAVE LENG circuit shown in Figure 7 are counted.Gathering the character code sum of being stored during the single waveform is necessary, and this is owing to store the definite character that the exact magnitude of the character code of

waveform fifo circuit

29 and 30 depends on handled ultrasonic signal to a great extent into.Adopt this counting to the character code sum, the CPU9 in the ultrasonic testing system 10 just can determine will read how many character codes and have how many character codes to be caused by various passages.

As discussed above, ultrasonic testing system 10 can be used as a kind of video rectifier and wave filter and a kind of based on threshold value, the run length coding, RLC device comes work.In addition, ultrasonic testing system 10 can combine video rectifier and wave filter and based on function threshold value, the run length coding, RLC device, so that obtain some ratio of compression, these ratio of compression are approximately the product of the ratio of compression of simple function.Will be in conjunction with these functions, will make the function that to finish video rectifier and wave filter, afterwards, each all is equipped with the copy of video enabling signal VIDEOEN among RLL circuit 47, FIFOWRIT circuit 46 and the pre-stored circuit PRESTORE80, thereby these circuit are not be used in each sampling start-up period handle a new waveform sampling, and in each video start-up period, only handle a new once sampling.

Comparer FPGA32 has the peak value and travel-time interval (P+TOF) defective gate circuit that have symbol, be used to search for the ultrasonic transducer signal that is received, and one by the user determined search time at interval in, store independent peak value of this signal and polarity and for corresponding to travel-time of that peak value at interval.Comparer FPGA32 can be compressed into lucky 3 bytes to the key message that is present in the waveform, and this is the situation that does not need the actual waveform record for those.

With reference to Fig. 9, Fig. 9 is the more detailed figure of of comparer FPGA32, and by a pair of input register 91 and 92 numerical datas that send from A/D converter 21, register 91 receives not delayed data, and register 92 receive delay data.Data from register 91 and 92 are offered testing circuit TEST93, afterwards, offer a rectifier and buffering LD device circuit RECTBUFF94, RECTBUFF94 works to be similar to rectifier shown in Figure 3 and buffering LD device circuit RECTBUFF44.Rectifier and buffering LD device circuit RECTBUFF94 offer its output a comparer/travel-time interval circuit COMPTOF95 and offer a comparer/travel-time interval circuit

COMPTOF96.COMPTOF circuit

95 and 96 is finished peak value and the travel-time logical operation at interval that the overwhelming majority is used for the specified data

signal.COMPTOF circuit

95 and 96 is output as a data-signal PEAKx (0: 7) to the peak value of data-signal, when ultrasonic testing system 10 is worked with the speed of 100MS/s, export a signal BITOTOFGx who is used to select the odd or even sampling time, and exporting a signal STOFGx, this signal STOFGx is used to send signal indicating should store the travel-time at interval.

A MODE circuit 97 produces one group of signal with general format of GxACT, and the general format of described GxACT is determined the needed hardware gate circuit search of user at interval.When GxACT equals 1, search peak in Wave data just.With reference to Figure 10, setting traffic pilot 102 is to select undelayed rectification data from rectifier and buffering LD device 94.Signal GxACT is transformed at 1 o'clock from 0 at every turn, has determined to indicate the peak value and the travel-time beginning of (P+TOF) at interval of symbol, and ARM circuit 103 is stored in first waveform sampling to be included in the peak value register in the traffic pilot 102.

The size of the waveform sampling of thing followed rectification be stored in the traffic pilot 102 existing peakedness ratio, finish this comparison by a pair of comparer 104 and 106.Whether comparer 104 is used for determining new data greater than the peak value that is stored in the traffic pilot 102, and comparer 106 is used for determining that whether new delayed data is greater than the peak value that is stored in the traffic pilot 102.When sampling rate is lower than 100MS/s, only use the comparer 104 of top.If new delayed data and not the amplitude of delayed data so just do not take any action all less than present peak value.On the other hand, if delayed data or delayed data is not greater than the peak value that is stored in the traffic pilot 102, so current waveform sampling just covers in the traffic pilot 102 peak value of storage.Because delayed data and delayed data can be greater than the peak value that is stored in the traffic pilot 102, comparer 105 relatively delayed datas and the not size of delayed data, and send signal to traffic pilot 102, choose two data.Bigger that is used for storage in the sampling.During the end of each scouting interval, be stored in peak value in the traffic pilot 102 and be recorded among in several eight bit registers in the ISAIN circuit shown in Figure 4 one, this record carries out according to gate circuit number and port number.Can utilize isa bus interface circuit 13 by CPU9, read and show these registers.By means of most significant digit (D7), preserve the sign bit of each peak value by original input sample.

As shown in Figure 2, comparer FPGA32 sends STOFGx signal and BITOTOFGx signal for the timer FPGA33 that comprises some travel-time interval counters.Figure 11 provides the more detailed figure of timer 33, and Figure 12 provides the more detailed figure of a timer circuit 110 shown in Figure 11.Figure 13 has also shown travel-time interval circuit 120 shown in Figure 12.As shown in figure 13, travel-time interval counter 130 is counters of one 16, is used for the quantity of the sampling start-up period after " main bang " is counted.Main bang is meant the high-voltage pulse that causes from the initial output pulse of the ultrasonic energy of ultrasonic transducer 7.No matter when receive an at interval STOFx pulse of storage travel-time, the present travel-time at interval just according to the type stores of port number, gate circuit number and gate circuit in 16 a suitable travel-time interval register REG16BOB.For the sampling rate of 100MS/s, owing to receive two data samplings in the clock cycle of each 50MHz, signal BITOTOFGx just is used for TOFGxy (0), and TOF (0: 14) is used for TOFGxy (1: 15), and gives up TOF (15).Can read travel-time interval register TOFGxy by CPU9 by isa bus interface circuit 13.

Except the storage travel-time interval relevant with peak value, ultrasonic testing system 10 can also be searched for the signal that ultrasound wave causes, and one by the user determined search time at interval in, by one by the selected threshold value of user, storage corresponding to travel-time of skew first time of above-mentioned signal at interval.With reference to Figure 10, when signal GxACT equals 1, the size of the waveform sampling of rectification with two

comparers

104 and 106 and threshold value THRESH (0: 6) compare, when sampling rate is lower than 100MS/s, have only comparer 104 work of top.If the amplitude of data sampling is lower than specified threshold value THRESH, so, just do not take any action.On the other hand, if the amplitude of sampling greater than threshold value THRESH, is just issued timer FPGA33 to storage travel-time blank signal STOF.

Therefore,

comparer

95 and 96 order timers 33 are to be similar to above-mentioned signed peak value and travel-time mode at interval, according to the skew first time, the storage travel-time interval of signal passing threshold THRESH.But, the reference value that difference is to be used for comparison is not the existing peak value of sampled data, but a threshold value THRESH who chooses by the user.As a result, data-signal PEAK (0: 6) is a static symbol and equals the selected threshold value THRESH of user.Another difference is and the nonessential institute's stored propagation time spacing pulse (STOF) that sends when each defective gate pulse begins.In addition, in case another difference is to send independent storage travel-time (STOF) at interval, in gate pulse interim, institute's stored propagation time spacing pulse (STOF) just can not appear again.

Ultrasonic testing system 10 can also a kind of interface gate pulse mode be worked, wherein, search of defective gate pulse and/or waveform storing process can be delayed by interim search time that the user chooses at one, surpass the threshold value that can be chosen by the user up to the ultrasonic transducer signal that is received.With reference to Fig. 9, the comparer/travel-time interval circuit COMPTOF95 that is used for defective gate pulse 1 also plays the function of interface gate circuit.Interface gate pulse search is defined as at interval first of two GlACT at interval, equals 1 INTERFACEACT signal by one and sends described interface gate pulse search signal at interval.Produce the INTERFACEACT signal by MODE circuit 97.Can adopt an independent threshold value for the interface gate circuit, described interface gate circuit is chosen by a traffic pilot 151 shown in Figure 15, and traffic pilot 151 is in the ISAOUT circuit 140 shown in Figure 14.Traffic pilot 151 is chosen and is equaled 1 independent threshold value based on the INTERFACEACT signal.When making ultrasonic testing system 10 be in the interface gate pulse mode, timer FPGA33 also is in the interface gate pulse mode, and this interface gate pulse mode just finishes the first interface gate pulse search at interval when causing the first travel-time spacing pulse STOF that timer FPGA33 stores receiving immediately.The ENDIGATEx signal causes the transition of interface gate recurrent interval GlACT, and as shown in figure 13, the travel-time is the described ENDIGATEx signal of (TOF) circuit 120 generations at interval.

In many different application, can make ultrasonic testing system 10 be in the interface gate pulse mode.For example, when the water tank surface institute submergence by an alterable height is partly scanned, interface gate pulse search end at interval after threshold crossings can be used to the storage of delay waveform data, up to ultrasound wave permeate water and till running into the front surface of above-mentioned submergence part.Like this, be in the interface gate pulse mode, just can remove the unnecessary water route of storage data from by making ultrasonic testing system 10.The interface gate pulse propagation time that is write down (TOF) at interval also can be used to draw the surface elevation of the above-mentioned part that is submerged.

As mentioned above, the use that combines of the SRAM circuit 35 and 36 of timer FPGA33 and two 8K * 8 is so that determine that waveform acquisition at interval and hardware gate circuit search interval.With reference to Figure 16, counter 160 countdowns that Figure 16 has shown 122, one 8 in EVENTCNT circuit are by state-event or number at interval, and, in general, for the static RAM (SRAM) circuit 35 and 36 of interval mode provides the address.One 13 digit counter 161 makes event counter 160 each state be kept a period of time of expectation.More particularly, as the output INTQ (0: 12) of counter 161 when equaling 0, just start event counter 160.Static RAM (SRAM) circuit 35 and 36 has 13 positions to be used for memory gap length, and this interval length separates the intervalometer 161 of packing into when beginning at each.Static RAM (SRAM) circuit 35 and 36 also has some to be used at random programming to ultrasonic testing system 10 with a kind of of 8 kinds of patterns, and these 8 kinds of patterns start may making up of GlEN and gate pulse 2 startup G2EN corresponding to waveform storage startup WAVEEN, gate pulse 1.Static RAM (SRAM) circuit 35 and these 3 positions of 36 are that comparer FPGA32 and ripple FPGA33 have determined that waveform acquisition at interval and hardware gate circuit search interval.By determining inoperative those delay intervals for the signal programming in some intervals, for described those intervals, some or all of WAVEEN, G1EN and G2EN signal wire are all inoperative.

In when work, before main bang, load suitable interval counting must for static RAM (SRAM)

circuit

35 and 36 to 15 and load suitable, corresponding gate pulse mode at 0 to 2.Just before each main bang,, load onto initial count EVENTS (0: 6) and initial gap INTERVAL (0: 12) for event counter 160 and intervalometer 161 by resetting signal PREBANGRS and PREBANGINIT.Sampling enabling signal SAMPLEN one works, and event counter 160 just reduces its reading, and intervalometer 161 just begins countdown.When interval counter 161 arrives 0, just the currency of INTERVAL (0: 12) from static RAM (SRAM)

circuit

35 and 36 intervalometer 161 of packing into, and event counter 160 countings reduce counting, produce a new address for static RAM (SRAM)

circuit

35 and 36 thus.Continue this process, all arrive 0 up to counter 160 and 161, this hour counter 160 and 161 all stops.During counter 160 and 161 countdowns, determine that by the logic level that the output (0: 2) that appears at

SRAM circuit

35 and 36 is located gate pulse at interval.

As mentioned above, 3 of SRAM positions (0: 2) are used for placing a kind of in eight kinds of patterns of ultrasonic testing system 10.More particularly, position 0 is made as height so that start the waveform storage, and is made as position 0 low so that forbid the waveform storage.Start hardware gate circuit 1 search, position 1 is set as height, and will forbid 1 search of hardware gate circuit, and it is low that position 1 just is made as, remaining position, and ascending the throne 2 is set as height, so that start 2 search of hardware gate circuit, and position 2 is set as the low hardware gate circuit 2 of will forbidding and searches for.These pattern positions (0: 2) couple together with the gap digit (3: 12) at corresponding follow-up interval.

In order to make logic gates counting and transmission delay minimum, the event counter carry-out bit is connected with the input end of an octadic OR circuit, second input end of this octadic OR circuit is connected with the complement code of ISA interface IMSRAM address register.As a result, during checking must be set to FFh to address register, and, must event counter 160 be resetted by CPU9.

For

SRAM circuit

35 and 36 the programming examples be based on following these conditions: FS=50MS/s, the interface gate circuit is activated, scouting interval postpones=3 μ s, width=4 μ s, waveform gate circuit delay=1 μ s at interval, width=10 μ s, the delay of 1 scouting interval of hardware gate circuit=3 μ s, width=3 μ s, and 2 scouting intervals of hardware gate circuit be under an embargo.Waveform and hardware GATEl signal refer to the end of interface gate circuit.About theing contents are as follows of isa bus signal SRAM:

Table 1 address signal sexadecimal at interval, the binary to decimal pattern, binary mode F8h 7 4A8h 0,000,010,010,101 149 000 false start F9h 6 638h 0,000,011,000,111 199 000 interval delay FAh 5 152h 0,000,000,101,010 42 010 IV interval FBh 4 350h 0,000,001,101,010 106 000 a-gate circuits prolong

FCh 3 4A9h 0,000,010,010,101 149 001 a-gate circuits are transported late

Row FDh 2 7CBh 0,000,011,111,001 249 011 a-gate circuits, half

Ripple gate circuit FEh 1 51h 0,000,000,001,010 10 001 a-gate circuit FFh 0 0h 0,000,000,000,000 0 000 progressively finishes

Like this, ultrasonic testing system 10 can produce a plurality of gate pulses at interval, and wherein, these can link together at interval, perhaps, also can not link together.Can bring the quantity of expansion gate pulse by portal vein of each bit width of timer storer.For the gate pulse of greater number, the device with a common delay timer and a width timer of each gate circuit can expend much more power and logical circuit.

Ultrasonic testing system 10 has a hyperchannel (MC) control bus, and this hyperchannel control bus is one and passes through a multichannel buffer LD device circuit 37 to timer FPGA33, three signal buss.The hyperchannel control bus is connected with every UT system board in the ultrasonic testing system.The hyperchannel control logic circuit is among the timer FPGA33.Figure 17 is the block scheme of a MC circuit shown in Figure 11, and Figure 18 and 19 has shown a MCMASTER circuit 171 and the MCSLAVE circuit 172 shown in Figure 17 respectively.

With reference to Figure 17 to 19, have only a plate to be started as the hyperchannel main leaf of working in those hyperchannel plates in the ultrasonic testing system 10 by CPU9, perhaps simple main leaf, and, have only main leaf 171 to drive hyperchannel control bus and computer bus interrupt request (IRQ) line.But, all plates all have the hyperchannel slave unit 172 of working.Three lines that comprise the hyperchannel control bus are a MCSTANDBY signal wire, a MCDECBANGCNT signal wire and a MCSTARTBANG signal wire, and these lines are connected to each slave unit 172 effectively from main leaf 171.Main leaf 171 is handled these lines, makes " slave unit main bang counter " 193 countdowns on every block of plate.Each slave unit on each plate is electric current main bang counting and its main bang assignment relatively, so that whether decision will obtain data during the electric current main bang.As top defined, main bang is to cause from transducer 7 and the high-voltage pulse of the initial output pulse of the ultrasonic energy that comes.

More particularly, when energising work, CPU9 is initialized as all plates the plate 172 of slave unit automatically.Next, CPU9 only is initialized as mainboard 172 with one of them plate, and gives the number of pulses and the time programming preface between two pulse IBANGDELAY (5: 12) of each grid cross pulse (0: 3).Each slave unit 172 carried out initialization when CPU9 utilized the number of pulses of each grid cross pulse (0: 3) and their pulse assignment BASSIGNMENT (0: 3).When the triggering hyperchannel control signal TRIGGERMC that with value is 1 triggered mainboard 171, mainboard 171 reduced to zero to the MCSTANDBY signal wire, and the MCSTANDBY signal wire starts slave unit impulse meter 193 and sends the MCSTARTBANG pulse.As shown in figure 19, slave unit 172 has circuit 191 and 192, is used for determining whether their pulse assignment BASSIGNMENT mates with current impulse counting BANGCNT, if coupling will produce a plate enabling signal BOARDEN, gathers so that begin.Intermediate pulse delay counter 181 beginning countdowns in mainboard 171 when it arrives 0, are just sent the pulse MCDECBANGCNT of a decaying pulse counting.This pulse MCDECBANGCNT makes mainboard impulse meter 185 and all slave unit impulse meters 193 reduce their step-by-step counting.After seven microseconds, mainboard 171 sends the pulse of another starting impulse.Continue this process, up to step-by-step counting BANGCNT be kept to zero and also the intermediate pulse delay counter be zero, at this moment, send interrupt request IRQACQ, the output of trigger 183 raises signal wire MCSTANDBY, and, stoped the control of mainboard 171.Can give each passage programming of ultrasonic testing system 10, so that during image data, optionally excite the pulse in its pulse producer or pre-amplification circuit 12 or 14.Therefore, if original meaning can excite simultaneously to the hyperchannel programming.Polylith plate 10 can be programmed for close synchronization ground while image data each other.

Multi Channel Controller 111 fast, flexibly and can expand, and acquisition system intersects only to use once at each grid and interrupts, and how much quantity of tube passage is not, thus, reduced the quantity of the computer bus that passes through in the above.In a preferred embodiment, can use 8 blocks of plates and 16 passages at most, and 2 analog channels to of every plate multipath transmission A/D circuit 18.Carry out the hardware gate circuit collection of sync waveform and/or data on ultrasonic testing system 10 feasible all passages onboard of the present invention.Therefore, the present invention has avoided the shortcoming of prior art, promptly needs a plurality of pulses and they are followed in time-division multiplex system ring turn-on time.And, when selecting the highest sampling rate, by simultaneously a simulating signal being presented to a double channel A/D converter 21, make can two Half Speeds of parallel processing data stream, thus, can carry out waveform and hardware gate processing by enough CMOS logical circuit technology high-speeds.

Compare with existing detection system, ultrasonic testing system of the present invention provides dramatic benefit.For example, ultrasonic testing system provides digital hardware video rectifier a kind of fast quick-recovery, that have symbol and wave filter, the data in the ultrasonic transducer signal that this rectifier and wave filter can be pressed up to 16: 1 or the compression of higher fixed ratio is received.Rectifier and wave filter are stored the sampled value of one group of crest amplitude in the sampling, and recover quickly than common modeling scheme.Ultrasonic testing system also provides a kind of more high-resolution rectifier and wave filter, can preserve the accurate travel-time at interval by the timing information that adds a byte at each waveform sampling.

Ultrasonic testing system of the present invention also can be used as the digital run length coding, RLC device of a kind of hardware based on threshold value and uses, and is used for compressing the data of the ultrasonic transducer signal that is received, and is used for only storing the data that amplitude surpasses the selected threshold value of user.By stored number respectively by the user select, from bottom to top and before the threshold crossings from top to bottom and data point afterwards, strengthen run length coding, RLC based on threshold value.Ultrasonic testing system also can combine the run length coding, RLC based on threshold value with the digital hardware video rectifier and the wave filter that have symbol, so that obtain high waveform compression ratio.

Ultrasonic testing system of the present invention provides the capacity that is used for a large amount of digital hardware gate circuits.For example, ultrasonic testing system can be searched for the ultrasonic transducer signal that is received, and storage peak value and polarity and corresponding to travel-time of the peak value of determined scouting interval of user.A threshold value defective gate circuit also can be provided, be used to search for signal that ultrasound wave derives and one by the determined scouting interval of user, by one by the selected threshold value of user, storage corresponding to travel-time of the skew first time of described signal at interval.As another example, an interface gate circuit can be provided, be used to postpone normal defects gate circuit search and waveform storing process, up to the ultrasonic transducer signal that is received the search time that can select by the user surpass at interval one can threshold value by user's selection till.

Ultrasonic testing system of the present invention also provides compact logic control for three gate circuits that only have two counters.Each can be connected to get up at interval, and can bring expansion with portal vein of each bit wide by the timer storer.Compare with the structure of a traditional width timer of a delay timer and each gate circuit, the present invention provides more gate circuit with less power and logical circuit.

Ultrasonic testing system of the present invention also provides a kind of quick, flexible open-ended Multi Channel Controller, no matter how many port numbers is, sort controller only uses a look-at-me to each grid intersection that acquisition system caused.Further, as mentioned above, the feasible data that can gather waveform and/or hardware gate circuit simultaneously to numerous passages of a kind of multi-channel detection system, and two data stream of parallel processing.

For showing and illustrative purposes that the front has provided the explanation of the preferred embodiments of the present invention.Do not plan exhaustive or be confined to disclosed precise forms the present invention.According to above-mentioned instruction, many improvement and modification all are possible.

Select and illustrated embodiment for principle of the present invention and practical application thereof are described best, thus, make that other those of ordinary skills can best applications the present invention and various embodiment, and adopt each that be fit to the special-purpose considered to improve.Plan to make scope of the present invention only from here appending claims limit.

Claims

Modification according to the 19th of treaty

1. ultrasonic testing system that is used for compressed digital-data, this system comprises:

A pulsing circuit is used for exciting a ultrasonic transducer with a voltage signal, and receives analog data signal from described transducer;

A timing circuit that is used for determining acquisition interval;

An A/D converter is used in described acquisition interval described analog data signal being converted to numerical data;

A counter circuit that is used for definite by the selected numerical data set of samples of user;

A peak detector circuit that is used for gathering a peak value of numerical data in each numerical data set of samples; And

A storer is used for only storing the peak value of a numerical data from each described numerical data set of samples, thus, described digital data compression is become described peak value.

2. ultrasonic testing system as claimed in claim 1, wherein said numerical data is compressed by the ratio of integers that is no less than 16: 1.

3. ultrasonic testing system as claimed in claim 1, wherein said numerical data is compressed by the ratio of integers that is no less than 2: 1.

4. ultrasonic testing system as claimed in claim 1, also comprise one second pulsing circuit, this second pulsing circuit is used for exciting one second ultrasonic transducer and receiving second analog data signal from described transducer with one second voltage signal, wherein said A/D converter becomes second numerical data to described second analog signal conversion, and described peak detector circuit is determined peak value from described numerical data and described second numerical data.

5. ultrasonic testing system as claimed in claim 1 also comprises a control circuit, and this control circuit is used to prevent described memory stores peak value, surpasses certain threshold value during the determined in front scouting interval of described numerical data.

6. ultrasonic testing system as claimed in claim 1, it is characterized in that described peak detector circuit just described analog data signal on the occasion of during gather described peak value so that obtain the half-wave rectification of described analog data signal.

7. ultrasonic testing system as claimed in claim 1 is characterized in that the just described peak value of collection during the negative value of described analog data signal of described peak detector circuit, so that obtain the half-wave rectification of described analog data signal.

8. ultrasonic testing system as claimed in claim 1, it is characterized in that described peak detection circuit described analog data signal on the occasion of with negative value during all gather described peak value so that obtain described

Claims

A timing circuit that is used for determining acquisition interval;

An A/D converter converts described analog data signal to numerical data in described acquisition interval;

A counter circuit that is used for determining the numerical data set of samples;

A peak detector circuit is used for gathering the peak value of the numerical data of each numerical data set of samples; And

A storer is used for only storing the peak value of a described numerical data from each numerical data set of samples, thus, described digital data compression is become described peak value.

8. ultrasonic testing system as claimed in claim 1, it is characterized in that described peak detection circuit described analog data signal on the occasion of with negative value during all gather described peak value so that obtain the full-wave rectification of described analog data signal.

9. ultrasonic testing system that is used for compressed digital-data, this system comprises:

An A/D converter that is used for described analog data signal is converted to numerical data;

A threshold value comparator circuit is used for determining whether described numerical data surpasses one by the selected threshold value of user, and

One is used to store the storer that surpasses described numerical data by the selected threshold value of user.

10. ultrasonic testing system as claimed in claim 9, wherein said storer surpasses described by the user before the selected threshold value and all store data afterwards in above-mentioned data.

11. ultrasonic testing system as claimed in claim 9, it is above-mentioned by the selected threshold value of user that wherein said threshold value comparator circuit determines an interim of being chosen by the user whether described digital signal surpasses.

12. it is above-mentioned by the selected threshold value of user that ultrasonic testing system as claimed in claim 11, wherein said threshold value comparator circuit determine in some intervals selected by the user whether described numerical data surpasses.

13. ultrasonic testing system as claimed in claim 9 also comprises a control circuit, is used to prevent described memory stores numerical data, up to described numerical data till surpassing second threshold value during the previous predetermined scouting interval.

14. ultrasonic testing system as claimed in claim 9, also comprise one second pulsing circuit, be used for exciting second ultrasonic transducer with second voltage signal, and receive second analog data signal from described transducer, wherein said A/D converter becomes second numerical data to described second analog signal conversion, and described threshold value comparator circuit determines whether described second numerical data surpasses one by the second selected threshold value of user, and described memory stores surpasses described described second numerical data by the second selected threshold value of user.

15. a ultrasonic testing system, this ultrasonic testing system comprises:

One is used for determining one by user's timing circuit of selected scouting interval;

A peak detector circuit is used for obtaining the peak value of described numerical data during described scouting interval selected by the user;

A first memory that is used to store the peak value of described numerical data;

One is used for determining and timer at interval of corresponding travel-time of described peak value;

One is used to store second memory at interval of described travel-time.

16. ultrasonic testing system as claimed in claim 15, wherein said timing circuit is determined many by the selected scouting interval of user, described peak detctor collection is for described those peak values at interval, described first memory is stored the numerical value of described peak value, described timer is determined the travel-time interval of described peak value, and described second memory is stored the described travel-time at interval.

17. ultrasonic testing system as claimed in claim 15 also comprises a control circuit, is used to prevent described system delay search peak and travel-time interval then, surpasses second threshold value up to described numerical data during a previous predetermined scouting interval.

18. ultrasonic testing system as claimed in claim 15, also comprise one second pulsing circuit, be used for exciting one second ultrasonic transducer with one second voltage signal, and receive second analog data signal from described transducer, wherein said A/D converter becomes second numerical data to described second analog signal conversion, and described peak detector circuit is gathered the peak value of described numerical data and described second numerical data.

19. ultrasonic testing system as claimed in claim 15, wherein said peak detector circuit are also determined the polarity of above-mentioned peak value, and described first memory is stored this polarity.

20. a ultrasonic testing system comprises:

One is used for determining whether described numerical data surpasses the comparer by the selected threshold value of user during the scouting interval selected by the user;

One be used for determining one with a timer that surpasses by the relevant travel-time interval of first data sampling of the selected threshold value of user; And

One is used to store storer at interval of described travel-time.

21. ultrasonic testing system as claimed in claim 20, also comprise a control circuit, this control circuit is used to prevent described system delay and searches for a threshold crossings then, surpasses one second threshold value up to described numerical data during a previous predetermined scouting interval.

22. ultrasonic testing system as claimed in claim 20, also comprise one second pulsing circuit, be used for exciting one second ultrasonic transducer with one second voltage signal, and receive second analog data signal from described transducer, wherein said A/D converter converts described second analog data signal to second numerical data, and described comparer determines whether described second numerical data second selected interim is surpassing one by selected second threshold value of user by the user.

23. a ultrasonic testing system comprises:

One first pulsing circuit is used for exciting one first ultrasonic transducer with one first voltage signal, and receives first analog data signal from described first ultrasonic transducer;

One second pulsing circuit is used for exciting one second ultrasonic transducer with one second voltage signal, and receives second analog data signal from described second ultrasonic transducer;

The A/D conversion equipment, be used to receive described first and second analog data signals, and described first and second analog data signals are converted to first numerical data and second numerical data, described A/D conversion equipment postpones described first numerical data with respect to described second numerical data; And

Be used for device with described second numerical data and the processing of described first parallel digital data.

24. ultrasonic testing system as claimed in claim 23, wherein said A/D conversion equipment comprises a double channel A/D converter.

25. ultrasonic testing system as claimed in claim 23, it is characterized in that described A/D conversion equipment comprises single A/D converter, and described system also comprises the device that is used for the output signal of described single A/D converter is separated into described first numerical data and second numerical data.