SU1197091A1 - Device for decoding pulse sequence - Google Patents

Description

The invention relates to computing and can be used in data transmission systems. The purpose of the invention is to increase reliability with an increase in time. base pulse sequence. FIG. 1 shows a functional diagram of the device; in fig. 2 time diagrams of his work. The device contains a shift pulse generator 1, a buffer register 2, an element OR 3, a delay unit 4, the first 5 and second 6 decoders, a counter 7, a gate driver 8 and an AND 9 element, the device input connected to the buffer single-bit register 2, output which is connected to the first input of the second de-cipher 6 and through the 13 element OR 3 to the informational input of the delay unit 4, the last output of which is connected to the first input of the AND 9 element, the output of which is connected to another input of the OR 3. Clock inputs of the register 2, block 4 and counter and 7 are combined and connected to generator 1. The outputs of the decoders 5 and 6 are connected respectively to the output of the device and the start input of the counter 7, the discharge outputs of which are connected to the corresponding inputs of the gateway 8 of the gate, the output of which is connected to the second input of the And 9 element. The shaper 8 may be implemented in the form of a waiting multivibrator with a decoder at the input. Decoders 5 and 6 can be inserted as elements AND, the inputs of the first decoder 5 are connected to the outputs of the delay unit 4 corresponding to the time positions of the pulses in the received sequence, and the inputs of the second decoder 6 are combined with those of the first decoder 5, which correspond to the pulses of the initial part of the received pulse sequence. The pulse sequence decoding device works in a funny way. . The frequency of operation of the delay unit 4, the buffer register 2 and the counter 7 is set by the shift pulse generator 1. An 11g signal (Fig. 2a) is fed to the information input of the buffer register 2 and then through the element OR 3 to the information,; input of the delay unit 4. The recording of the pulse signal in block 4 delay J is of course divided into two cycles. In the first cycle, the delay block 4, via the buffer register 2 and the element OR 3, is recorded in the first part of the pulse sequence of FIG. 26J. The first input of the second decoder -6 is connected to the output of buffer register 2, the remaining inputs are connected to the outputs of block 4 delay so as to highlight the distinguishing feature of this signal. Distinguishing feature - it is necessary to have a group of pulses that are part of a pulse signal, by which the preliminary recognition of this signal takes place. The final decoding of the pulse signal is performed by the first decoder 5 after the entire signal has been recorded in the 4-delay block. The output of the discriminator 6 decoder 6 is a trigger pulse. The start-up pulse starts the counter 7, which counts the time interval required for recording the remaining part of the pulse signal in block 4 of the delay. The gate former 8 generates a resolution gate equal in duration to this time interval (Fig. 2c). The resolution gate arrives at element 9. At the second input of element 9, information is received from the last output of block 4 delays. In the second cycle, in the presence of a resolution strobe, the first part of the pulse signal from the output of block 4 delay through element 9 and through element OR 3 again falls into block 4 delay (fig. 2d). Through the other input of the element OR 3, the second part of the pulse sequence enters the input of the delay unit 4 (Fig. 2e). The pulse signal, which is completely recorded in block 4 of delay, is shown in FIG. 2nd. The decoding of this signal is carried out by the decoder 5, the inputs of which are connected in a certain order (corresponding to the code of this sequence) with the outputs of the delay unit 4. If the first tap of the decoder 6 of the hallmark is not connected to the output of the buffer register 2, but to the output of the delay unit 4, i.e. if we exclude the buffer register 2, then the distinguishing feature will be decoded more than once, as is necessary an infinite number of times, which will cause the information to ring in the delay line.

The counter 7 is designed in such a way that if, during the interval of the resolution interval, a trigger pulse will come.

1197091

counter 7 is zeroed and the resolution interval is recalled. This is done by the D.P. of the order that the interference, if a distinctive feature is formed from them, would not disrupt the operation of the pulse sequence decoding device.

1 cycle

H

2 cycle

FIG. g

Claims (1)

(54) (57) A PULSE SEQUENCE DECODING DEVICE, comprising a shift pulse generator, a delay unit, a counter, an AND element, the output of which is connected to the first input of the OR element, and the first and second decoders, the output of the first decoder is the output of the device, and the inputs are connected to corresponding outputs of the delay unit, characterized in that, in order to increase reliability while increasing the time base of the pulse sequence, a second decoder, gate generator and buffer register, information whose input is the input of the device, the clock input is combined with the clock inputs of the delay unit of the counter and connected to the output of the shear pulse generator, the output of the buffer register is connected to the first input of the second decoder and the second input of the OR element, the output of which is connected to the information input of the delay unit the last output of which is connected to the first input of the And element, and the corresponding outputs of the delay unit are connected to the second inputs of the second decoder, the output of which is connected to the counter start input, the outputs of the discharges of which are connected to the corresponding inputs of the gate generator, the output of which is connected to the second input of the element I.