CN1197090C - 高速半导体存储器件 - Google Patents
高速半导体存储器件 Download PDFInfo
- Publication number
- CN1197090C CN1197090C CNB991003233A CN99100323A CN1197090C CN 1197090 C CN1197090 C CN 1197090C CN B991003233 A CNB991003233 A CN B991003233A CN 99100323 A CN99100323 A CN 99100323A CN 1197090 C CN1197090 C CN 1197090C
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- China
- Prior art keywords
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- order
- unit
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- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0879—Burst mode
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
Abstract
Description
Claims (22)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP001688/98 | 1998-01-07 | ||
JP001688/1998 | 1998-01-07 | ||
JP168898A JPH11203860A (ja) | 1998-01-07 | 1998-01-07 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1225492A CN1225492A (zh) | 1999-08-11 |
CN1197090C true CN1197090C (zh) | 2005-04-13 |
Family
ID=11508467
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB991003233A Expired - Fee Related CN1197090C (zh) | 1998-01-07 | 1999-01-06 | 高速半导体存储器件 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6345334B1 (zh) |
JP (1) | JPH11203860A (zh) |
KR (1) | KR100328330B1 (zh) |
CN (1) | CN1197090C (zh) |
DE (1) | DE19900365A1 (zh) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6668317B1 (en) * | 1999-08-31 | 2003-12-23 | Intel Corporation | Microengine for parallel processor architecture |
US6606704B1 (en) * | 1999-08-31 | 2003-08-12 | Intel Corporation | Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode |
US6427196B1 (en) * | 1999-08-31 | 2002-07-30 | Intel Corporation | SRAM controller for parallel processor architecture including address and command queue and arbiter |
US6983350B1 (en) * | 1999-08-31 | 2006-01-03 | Intel Corporation | SDRAM controller for parallel processor architecture |
WO2001016702A1 (en) | 1999-09-01 | 2001-03-08 | Intel Corporation | Register set used in multithreaded parallel processor architecture |
US6532509B1 (en) | 1999-12-22 | 2003-03-11 | Intel Corporation | Arbitrating command requests in a parallel multi-threaded processing system |
US6694380B1 (en) | 1999-12-27 | 2004-02-17 | Intel Corporation | Mapping requests from a processing unit that uses memory-mapped input-output space |
US6625654B1 (en) * | 1999-12-28 | 2003-09-23 | Intel Corporation | Thread signaling in multi-threaded network processor |
US6307789B1 (en) * | 1999-12-28 | 2001-10-23 | Intel Corporation | Scratchpad memory |
US6631430B1 (en) * | 1999-12-28 | 2003-10-07 | Intel Corporation | Optimizations to receive packet status from fifo bus |
US6661794B1 (en) | 1999-12-29 | 2003-12-09 | Intel Corporation | Method and apparatus for gigabit packet assignment for multithreaded packet processing |
US6584522B1 (en) * | 1999-12-30 | 2003-06-24 | Intel Corporation | Communication between processors |
US6631462B1 (en) * | 2000-01-05 | 2003-10-07 | Intel Corporation | Memory shared between processing threads |
US7681018B2 (en) * | 2000-08-31 | 2010-03-16 | Intel Corporation | Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set |
JP3932166B2 (ja) * | 2001-08-07 | 2007-06-20 | シャープ株式会社 | 同期型半導体記憶装置モジュールおよびその制御方法、情報機器 |
US6868476B2 (en) * | 2001-08-27 | 2005-03-15 | Intel Corporation | Software controlled content addressable memory in a general purpose execution datapath |
US7126952B2 (en) * | 2001-09-28 | 2006-10-24 | Intel Corporation | Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method |
JP3851865B2 (ja) | 2001-12-19 | 2006-11-29 | 株式会社東芝 | 半導体集積回路 |
US7895239B2 (en) | 2002-01-04 | 2011-02-22 | Intel Corporation | Queue arrays in network devices |
US6934951B2 (en) * | 2002-01-17 | 2005-08-23 | Intel Corporation | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section |
JP2003280982A (ja) * | 2002-03-20 | 2003-10-03 | Seiko Epson Corp | 多次元メモリのデータ転送装置及び多次元メモリのデータ転送プログラム、並びに多次元メモリのデータ転送方法 |
US6910087B2 (en) * | 2002-06-10 | 2005-06-21 | Lsi Logic Corporation | Dynamic command buffer for a slave device on a data bus |
US7471688B2 (en) * | 2002-06-18 | 2008-12-30 | Intel Corporation | Scheduling system for transmission of cells to ATM virtual circuits and DSL ports |
KR100484161B1 (ko) * | 2002-09-13 | 2005-04-19 | 삼성전자주식회사 | 데이터를 워드 단위 또는 바이트 단위로 로드하고 워드단위로 저장하는 장치 및 방법 |
US7433307B2 (en) * | 2002-11-05 | 2008-10-07 | Intel Corporation | Flow control in a network environment |
JP4314057B2 (ja) * | 2003-04-18 | 2009-08-12 | サンディスク コーポレイション | 不揮発性半導体記憶装置および電子装置 |
US7213099B2 (en) * | 2003-12-30 | 2007-05-01 | Intel Corporation | Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches |
US20060171234A1 (en) | 2005-01-18 | 2006-08-03 | Liu Skip S | DDR II DRAM data path |
JP4820566B2 (ja) * | 2005-03-25 | 2011-11-24 | パナソニック株式会社 | メモリアクセス制御回路 |
WO2007113757A2 (en) * | 2006-04-04 | 2007-10-11 | Koninklijke Philips Electronics N.V. | System and method for supporting a hot-word-first request policy for a multi-heirarchical memory system |
CN107368440B (zh) * | 2017-07-06 | 2021-06-18 | 沈阳理工大学 | 一种同位控制猝发总线的控制方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0713860B2 (ja) | 1988-11-25 | 1995-02-15 | 三菱電機株式会社 | 半導体記憶装置 |
US5131083A (en) | 1989-04-05 | 1992-07-14 | Intel Corporation | Method of transferring burst data in a microprocessor |
US5255378A (en) * | 1989-04-05 | 1993-10-19 | Intel Corporation | Method of transferring burst data in a microprocessor |
JPH04184791A (ja) | 1990-11-20 | 1992-07-01 | Nec Corp | 半導体メモリ |
JP3992757B2 (ja) * | 1991-04-23 | 2007-10-17 | テキサス インスツルメンツ インコーポレイテツド | マイクロプロセッサと同期するメモリ、及びデータプロセッサ、同期メモリ、周辺装置とシステムクロックを含むシステム |
JPH06124585A (ja) * | 1991-09-04 | 1994-05-06 | Citizen Watch Co Ltd | 半導体メモリ装置とその書込読出し方法 |
JPH06111561A (ja) | 1992-09-25 | 1994-04-22 | Nec Corp | 半導体メモリ装置 |
JP2812154B2 (ja) * | 1993-07-27 | 1998-10-22 | 日本電気株式会社 | 半導体記憶装置 |
JPH08129882A (ja) * | 1994-10-31 | 1996-05-21 | Mitsubishi Electric Corp | 半導体記憶装置 |
US5526320A (en) * | 1994-12-23 | 1996-06-11 | Micron Technology Inc. | Burst EDO memory device |
JP2817685B2 (ja) | 1995-11-29 | 1998-10-30 | 日本電気株式会社 | 半導体メモリ |
US5715476A (en) * | 1995-12-29 | 1998-02-03 | Intel Corporation | Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic |
KR100247923B1 (ko) | 1997-01-29 | 2000-03-15 | 윤종용 | 스위치신호발생기및이를이용한고속동기형sram |
JPH10290582A (ja) | 1997-04-15 | 1998-10-27 | Nikon Corp | 振動アクチュエータ |
US5903496A (en) * | 1997-06-25 | 1999-05-11 | Intel Corporation | Synchronous page-mode non-volatile memory with burst order circuitry |
US5973989A (en) * | 1997-08-22 | 1999-10-26 | Micron Technology, Inc. | Method and apparatus for transmitting and receiving data at both the rising edge and the falling edge of a clock signal |
-
1998
- 1998-01-07 JP JP168898A patent/JPH11203860A/ja active Pending
-
1999
- 1999-01-06 CN CNB991003233A patent/CN1197090C/zh not_active Expired - Fee Related
- 1999-01-06 US US09/225,464 patent/US6345334B1/en not_active Expired - Lifetime
- 1999-01-07 DE DE19900365A patent/DE19900365A1/de not_active Withdrawn
- 1999-01-07 KR KR1019990000174A patent/KR100328330B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN1225492A (zh) | 1999-08-11 |
DE19900365A1 (de) | 1999-09-23 |
KR19990067772A (ko) | 1999-08-25 |
KR100328330B1 (ko) | 2002-03-12 |
JPH11203860A (ja) | 1999-07-30 |
US6345334B1 (en) | 2002-02-05 |
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C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
ASS | Succession or assignment of patent right |
Owner name: NEC ELECTRONICS TAIWAN LTD. Free format text: FORMER OWNER: NIPPON ELECTRIC CO., LTD. Effective date: 20030615 |
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C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20030615 Address after: Kanagawa, Japan Applicant after: NEC Corp. Address before: Tokyo, Japan Applicant before: NEC Corp. |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050413 Termination date: 20100208 |