CN1186339A - 用于半导体芯片封装的带有预模制底盘的引线框 - Google Patents

用于半导体芯片封装的带有预模制底盘的引线框 Download PDF

Info

Publication number
CN1186339A
CN1186339A CN97120446A CN97120446A CN1186339A CN 1186339 A CN1186339 A CN 1186339A CN 97120446 A CN97120446 A CN 97120446A CN 97120446 A CN97120446 A CN 97120446A CN 1186339 A CN1186339 A CN 1186339A
Authority
CN
China
Prior art keywords
lead frame
underpan
premolded
support
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN97120446A
Other languages
English (en)
Other versions
CN1127763C (zh
Inventor
李秉德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
LG Semicon Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LG Semicon Co Ltd filed Critical LG Semicon Co Ltd
Publication of CN1186339A publication Critical patent/CN1186339A/zh
Application granted granted Critical
Publication of CN1127763C publication Critical patent/CN1127763C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种用于半导体芯片封装的带有预模制底盘的改进引线框,可以防止模制体与其上安装有半导体芯片封装中的半导体芯片的底盘之间发生剥离和龟裂,该引线框包括:设置于引线框的内引线内部区域的EMC预模制底盘,该预模制底盘与从引线框的支撑部件延伸的支撑条相连,用于在其上安装半导体芯片。

Description

用于半导体芯片封装的 带有预模制底盘的引线框
本发明涉及一种用于半导体芯片封装的带预模制底盘的引线框，特别涉及一种用于半导体芯片封装的带预模制底盘的改进引线框，能够防止模制体与其上设置半导体芯片封装中的半导体芯片的底盘间发生剥离和龟裂。
参见图1，引线框，一种用于制造半导体芯片封装的金属结构，一般包括引线框1a两侧上的导轨10，用于支撑引线框1a自身以及在制造期间自动传递引线框1a时引导引线框1a；和其中心处的底盘11，用于贴装半导体芯片5。另外，引线框1a还包括：内引线2，每根皆由金属丝12电连接到作为半导体芯片5的外连端的键合焊盘；和内引线2外的外引线13。阻拦条14设置在内引线2和外引线13之间，用于支撑内引线2和外引线13，在EMC(环氧树脂模制化合物)模制后的修整时阻拦条14被去掉。底盘11由支撑条4a支撑，并由此连接到引线框1a的主体上，内引线2和底盘11之间存在着间隙。
然而，上述常规引线框1a中，包封半导体芯片5和底盘11的模制体8是EMC制成的，而占据引线框1a最大面积的底盘11是与其它部件相同的铜合金制的，因两者间性质不同造成两者之间的热膨胀系数彼此不同。为此，封装工艺、完成封装后的老化、可靠性试验的热处理、或安装封装后封装工作期间，存在着出现因剪应力造成的底盘11的底与模制体8间紧密粘结分离的剥离现象的可能性，剪切应力是因两者间热膨胀系数不同引起的。另外，如果湿汽渗透到此剥离之间，封装的模制体8便会发生龟裂，这会引起许多问题，例如，生产成品率下降，在将封装安装在电路板上后使用该封装期间封装失效，导致要替换封装。
因此，本发明旨在提供一种用于半导体芯片封装的带有预模制底盘的引线框，基本上能克服现有技术的局限和缺点造成的几个问题。
本发明的其它特点和优点如说明书所述，部分可从说明书中显现，或可以实施本发明获知。特别是书面说明和权利要求书及附图中指出的结构将会实现和获得本发明的目的和优点。
为了实现这些和其它优点，根据本发明的目的，正如所概述和概要说明的那样，用于半导体芯片封装的带有预模制底盘的引线框包括：设置于引线框的内引线内部区域中的EMC预模制底盘，该底盘与从引线框的支撑部件延伸的支撑条相连，用于在其上安装半导体芯片。
应该明白，上述的概括说明和以下的详细说明皆是例证性和说明性的，旨在对所申请的发明作进一步地说明。
各附图可以用于更深入的地理解发明，它们与说明书结合构成说明书的一部分，用于展示发明的实施例，并与说明书一起解释发明的原理。
各附图中：
图1是常规引线框的平面图；
图2是常规半导体芯片封装的纵剖图；
图3a是根据本发明第一实施例的引线框的平面图；
图3b是根据本发明第一实施例的引线框的平面图，展示了形成于其上的预模制底盘；
图4是具有应用于其中的本发明引线框的半导体芯片封装的纵剖图；
图5是根据本发明第二实施例的引线框的平面图；
图6是根据本发明第三实施例的引线框的平面图；
图7是根据本发明第四实施例的引线框的平面图；
图8是根据本发明第五实施例的引线框的平面图。
下面结合示于附图中的实例对本发明的优选实施例作详细说明。
图3a是根据本发明第一实施例的引线框的平面图，图3b是根据本发明第一实施例的引线框的平面图，展示了形成于其上的预模制底盘，图4是具有应用于其中的本发明引线框的半导体芯片封装的纵剖图。
参见3a、3b和4，根据本发明第一实施例的引线框包括：从引线框1的支撑部件延伸的支撑条4，该支撑条4设置于引线框1的内引线2的内部区域；形成于支撑条4上的EMC预制底盘6，用于安装半导体芯片5。预模制底盘支撑片7a设置于每根从引线框1的支撑部件3延伸的支撑条4前端，用于支撑预模制底盘6。预模制底盘支撑片7a垂直于支撑条4的轴形成。
下面说明上述本发明引线框的功能。
与一般引线框一样，本发明的引线框也是在预先分开制造完后被引入封装步骤，但不是半导体芯片5设置于其上的结构。即，预模制底盘支撑片7a只位于每根从引线框1的支撑部件3延伸的支撑条4的前端，用于在此后的步骤中形成预模制底盘6时支撑该预模制底盘6。因此，在通过预模制底盘6形成步骤形成了用于在其上安装半导体芯片5的预模制底盘后，且在进行封装工艺中的芯片贴装步骤之前，先进行以下步骤，如芯片贴装和引线键合。所以，为了进行将本发明的引线框应用于封装工艺，作为形成EMC预模制底盘6的步骤的模制步骤是本发明的主题，该步骤应该包括在引线框制造工艺中，或芯片贴装步骤之前的封装工艺中。
这样，因为本发明的半导体芯片封装工艺应用具有预先形成于其中的模制底盘6的引线框，该工艺的以下步骤与一般封装工艺步骤顺序相同，所以，该半导体芯片封装工艺的有益之处在于，半导体芯片封装工艺步骤和封装制造设备无需随引线框材料和制造工艺的变化而变化。因此，如果包封设置于模制底盘6上的半导体芯片5的模制步骤在完成了封装工艺中的一步芯片贴装和引线键合后进行，其中芯片贴装步骤将半导体芯片贴装于模制底盘6上，引线键合步骤用金属丝12电连接半导体芯片上的键合焊盘与内引线，则本发明的引线框1易于应用与预模制底盘6相同的EMC材料模制该封装。结果，如图4中虚线所示，由于具有设置于其上的半导体芯片5的预制底盘6与模制体8紧密附着在一起，且因它们由具有相同性质的同一材料制成，它们的热膨胀系数相同，因而可以消除半导体芯片封装工艺期间或老化和可靠性试验工艺期间发生的热失配，本发明的引线框可以防止由因合金底盘11与包封半导体芯片5的模制体8的热膨胀系数不同造成的剪切应力引起的底盘11和模制体8之间发生剥离。
图5是根据本发明第二实施例的引线框的平面图，示出了一种环形预模制底盘支撑片7b，该片位于每根支撑条4的前端，用于支撑预模制底盘6，其中支撑条4从引线框1的支撑部件3延伸。
图6是根据本发明第三实施例的引线框的平面图，示出一种Y形、树结构的预模制底盘支撑片7C，该片位于每根支撑条4的前端，用于在支撑预模制底盘6时提供更宽的面积，其中支撑条4从引线框1的支撑部件3延伸。
图7是根据本发明第四实施例的引线框的平面图，示出了一种连接条9，用于连接一对支撑条4的前端，其中支撑条4从引线框1的支撑部件3延伸。
图8是根据本发明第五实施例的引线框的平面图，示出了一种矩形连接环9，用于连接所有支撑条4的前端，其中支撑条4从引线框1的支撑部件3延伸。
容易了解到，对于位于引线框1的支撑条4前端的预模制支撑片，当然可以不拘泥于上述任一种几何形状和结构而改变其几何形状和结构。另外，显然可以将本发明的带有预模制底盘6的引线框1应用于所有需要用于在其上设置半导体芯片的底盘的半导体芯片封装。
如上所述，本发明的引线框改进了半导体芯片封装中引线框1的结构，容易消除半导体芯片的封装中半导体芯片5与EMC间的剥离和龟裂。即，由于避免了半导体芯片封装期间或封装完成后的老化和可靠性试验期间发生的热失配，可以防止底盘11的底部和EMC间界面处发生剥离，所以，本发明的引线框可以提高半导体芯片封装的生产成品率和可靠性。
显然，对于本领域的普通技术人员来说，在不脱离本发明精神或范围的情况下，可以对本发明制造半导体器件的方法做出各种改型和变化。但是，本发明将覆盖这些会落入权利要求书及其等同的范围内的改型和变化。

Claims (7)

1.一种用于半导体芯片封装的带预模制底盘的引线框，该引线框包括：
设置于引线框的内引线内部区域的环氧树脂模制化合物预模制底盘，该预模制底盘与从引线框的支撑部件延伸的支撑条相连，用于在其上安装半导体芯片。
2.如权利要求1的引线框，其中，每根从引线框的支撑部件延伸的支撑条的前端具有预模制底盘支撑片，用于在支撑模制底盘时提供更大的面积。
3.如权利要求2的引线框，其中，预模制底盘支撑片垂直于支撑条的轴形成。
4.如权利要求2的引线框，其中，预模制底盘支撑片为Y形树结构。
5.如权利要求2的引线框，其中，预模制底盘支撑片为环形。
6.如权利要求1的引线框，还包括连接条，用于连接一对从引线框的支撑部件延伸的支撑条前端。
7.如权利要求1的引线框，还包括矩形连接环，用于连接从引线框的支撑部件延伸的支撑条前端。
CN97120446A 1996-12-27 1997-10-15 用于半导体芯片封装的带有预模制底盘的引线框 Expired - Fee Related CN1127763C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR73493/96 1996-12-27
KR73493/1996 1996-12-27
KR1019960073493A KR100205353B1 (ko) 1996-12-27 1996-12-27 프리-몰드 패들을 갖는 반도체 패키지 제조 공정용 리드 프레임

Publications (2)

Publication Number Publication Date
CN1186339A true CN1186339A (zh) 1998-07-01
CN1127763C CN1127763C (zh) 2003-11-12

Family

ID=19491361

Family Applications (1)

Application Number Title Priority Date Filing Date
CN97120446A Expired - Fee Related CN1127763C (zh) 1996-12-27 1997-10-15 用于半导体芯片封装的带有预模制底盘的引线框

Country Status (5)

Country Link
US (1) US6091135A (zh)
JP (1) JP2976199B2 (zh)
KR (1) KR100205353B1 (zh)
CN (1) CN1127763C (zh)
DE (1) DE19756179B4 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6504238B2 (en) * 2000-01-31 2003-01-07 Texas Instruments Incorporated Leadframe with elevated small mount pads
US20080284038A1 (en) * 2007-05-16 2008-11-20 Dimaano Jr Antonio B Integrated circuit package system with perimeter paddle
US8497165B2 (en) 2011-10-20 2013-07-30 Intersil Americas Inc. Systems and methods for lead frame locking design features

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5423570U (zh) * 1977-07-19 1979-02-16
US4400714A (en) * 1980-11-06 1983-08-23 Jade Corporation Lead frame for semiconductor chip
US4466183A (en) * 1982-05-03 1984-08-21 National Semiconductor Corporation Integrated circuit packaging process
US4536825A (en) * 1984-03-29 1985-08-20 Unitrode Corporation Leadframe having severable fingers for aligning one or more electronic circuit device components
US4651415A (en) * 1985-03-22 1987-03-24 Diacon, Inc. Leaded chip carrier
EP0213575B1 (en) * 1985-08-23 1992-10-21 Nec Corporation Method of manufacturing a semiconductor device employing a film carrier tape
JPH0415947A (ja) * 1990-05-09 1992-01-21 Hitachi Cable Ltd 半導体装置用リードフレームおよび半導体装置
US5138429A (en) * 1990-08-30 1992-08-11 Hewlett-Packard Company Precisely aligned lead frame using registration traces and pads
US5122858A (en) * 1990-09-10 1992-06-16 Olin Corporation Lead frame having polymer coated surface portions
US5214846A (en) * 1991-04-24 1993-06-01 Sony Corporation Packaging of semiconductor chips
US5278447A (en) * 1992-01-16 1994-01-11 Lsi Logic Corporation Semiconductor device assembly carrier
US5539251A (en) * 1992-05-11 1996-07-23 Micron Technology, Inc. Tie bar over chip lead frame design
JPH05326808A (ja) * 1992-05-15 1993-12-10 Ibiden Co Ltd 電子部品搭載用基板およびこれを用いた半導体装置
US5233222A (en) * 1992-07-27 1993-08-03 Motorola, Inc. Semiconductor device having window-frame flag with tapered edge in opening
US5294827A (en) * 1992-12-14 1994-03-15 Motorola, Inc. Semiconductor device having thin package body and method for making the same
JPH06244348A (ja) * 1993-02-15 1994-09-02 Seiko Epson Corp 半導体装置用リードフレーム
TW276357B (zh) * 1993-03-22 1996-05-21 Motorola Inc
JP2767404B2 (ja) * 1994-12-14 1998-06-18 アナムインダストリアル株式会社 半導体パッケージのリードフレーム構造

Also Published As

Publication number Publication date
DE19756179B4 (de) 2007-01-25
US6091135A (en) 2000-07-18
KR100205353B1 (ko) 1999-07-01
JP2976199B2 (ja) 1999-11-10
CN1127763C (zh) 2003-11-12
JPH10200040A (ja) 1998-07-31
DE19756179A1 (de) 1998-07-02
KR19980054345A (ko) 1998-09-25

Similar Documents

Publication Publication Date Title
US5438021A (en) Method of manufacturing a multiple-chip semiconductor device with different leadframes
US8637965B2 (en) Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
CN1085408C (zh) 半导体封装及引线框架
US6222258B1 (en) Semiconductor device and method for producing a semiconductor device
CN100359681C (zh) 半导体装置
US6239487B1 (en) Lead frame with heat spreader and semiconductor package therewith
US5874773A (en) Lead frame having a supporting pad with a plurality of slits arranged to permit the flow of resin so as to prevent the occurrence of voids
CN100380650C (zh) 半导体集成电路器件及其制造方法
EP0577966A1 (en) Reduced stress plastic package
US5891758A (en) Semiconductor device and method for manufacturing semiconductor device
US20020057553A1 (en) Stacked intelligent power module package
EP0996962A2 (en) Resin molded type semiconductor device and a method of manufacturing the same
JPH1174442A (ja) リードフレーム及びこれを用いた半導体パッケージ
CN1751390A (zh) 包括无源器件的引线框架
US6849933B2 (en) Semiconductor mounting device and method of manufacturing the same
KR950000205B1 (ko) 리이드 프레임 및 이를 사용한 반도체 장치
US20010008308A1 (en) Integrated circuit chip and method for fabricating the same
CN1127763C (zh) 用于半导体芯片封装的带有预模制底盘的引线框
US5408127A (en) Method of and arrangement for preventing bonding wire shorts with certain integrated circuit components
US5945731A (en) Resin encapsulated semiconductor device and method for manufacturing the same
US6858474B1 (en) Wire bond package and packaging method
CN101320886A (zh) 无盖封装及其制造方法
JPH0955407A (ja) テープキャリア構造
JP3723351B2 (ja) 半導体装置、およびその製造方法
JPH11145369A (ja) リードフレームおよびそれを用いた半導体装置ならびにその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20031112

Termination date: 20131015