CN118472041B

CN118472041B - Semiconductor device and preparation method thereof

Info

Publication number: CN118472041B
Application number: CN202410918644.2A
Authority: CN
Inventors: 袁俊
Original assignee: Hubei Jiufengshan Laboratory
Current assignee: Hubei Jiufengshan Laboratory
Priority date: 2024-07-10
Filing date: 2024-07-10
Publication date: 2024-09-06
Anticipated expiration: 2044-07-10
Also published as: CN118472041A

Abstract

The application discloses a semiconductor device and a preparation method thereof, which relate to the technical field of semiconductors, wherein the semiconductor device comprises: a semiconductor substrate having an epitaxial layer on one side surface; a well region is arranged in the surface of one side of the epitaxial layer, which faces away from the semiconductor substrate; two first grooves and a second groove positioned between the first grooves are formed in the surface of one side of the epitaxial layer, which is away from the semiconductor substrate, and the depth of each of the first grooves and the depth of each of the second grooves are larger than that of the well region; a groove source electrode is arranged in the first groove; a trench gate is arranged in the second trench; the trench source comprises first source regions and second source regions which are alternately distributed in the length direction of the first trench; the trench source all corresponds and is provided with first masking structure, and first masking structure includes: the first doped region is positioned in the epitaxial layer opposite to the bottom of the first source region; the second doped region is positioned at the bottom of the second source region and in the epitaxial layer with the opposite side walls, and the second doped region is connected with the metal source above the epitaxial layer.

Description

Semiconductor device and preparation method thereof

Technical Field

The application relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.

Background

In recent years, ultra wide band gap semiconductor materials (such as gallium oxide, diamond, aluminum nitride, etc.) having a wide band gap (such as SiC and GaN, etc.) and a larger band gap have been attracting attention from the industry due to excellent material characteristics.

Compared with the traditional Si material, the wide band gap and ultra-wide band gap semiconductor material has more advantages in physical characteristics such as the band gap, the critical breakdown electric field intensity, the electron saturation drift speed and the like, and the power device (such as a diode, a transistor and the like) prepared based on the wide band gap or ultra-wide band gap semiconductor material has more excellent electrical characteristics, can adapt to the application requirements of high power, high voltage, high frequency, high temperature and the like which cannot be met by a silicon-based device, and is also one of breakthrough paths exceeding the Moore law. Therefore, the wide band gap and ultra-wide band gap semiconductor material is widely applied to the field of new energy (such as photovoltaic, energy storage, charging piles, electric automobiles and the like), and the development of the new energy revolution is promoted.

Although the semiconductor device using the wide band gap or ultra wide band gap semiconductor material has better performance than the semiconductor device using the conventional Si material, there is still a need for improvement in the voltage resistance.

Disclosure of Invention

In view of the above, the present application provides a semiconductor device and a method for manufacturing the same, which achieve the purpose of improving the withstand voltage performance. The specific scheme is as follows:

A first aspect of the present application provides a semiconductor device comprising:

a semiconductor substrate having an epitaxial layer on one side surface thereof; a well region is arranged in the surface of one side of the epitaxial layer, which faces away from the semiconductor substrate;

Two first grooves and a second groove positioned between the first grooves are formed in the surface of one side of the epitaxial layer, which is away from the semiconductor substrate, and the depth of each of the first grooves and the depth of each of the second grooves are larger than that of the well region; a groove source electrode is arranged in the first groove; a trench gate is arranged in the second trench; the trench source comprises first source regions and second source regions which are alternately distributed in the length direction of the first trench;

The trench source all corresponds and is provided with first masking structure, and first masking structure includes: the first doped region is positioned in the epitaxial layer opposite to the bottom of the first source region; the second doped region is positioned in the epitaxial layer at the bottom of the second source region and opposite to the side wall, and the second doped region is connected with the metal source above the epitaxial layer.

Optionally, in the semiconductor device, a portion of the second doped region opposite to the sidewall of the second source region extends to an upper surface of the epitaxial layer to be connected to the metal source;

Or, the portion of the second doped region opposite to the sidewall of the second source region extends to the well region to be connected with the metal source based on the well region.

Optionally, in the semiconductor device, in the same first masking structure, a portion of the second doped region below the bottom of the second source region and the first doped region are the same implantation region formed by the same ion implantation.

Optionally, in the semiconductor device, a portion of the second doped region located on a sidewall of the second source region is a first implanted region formed before the first trench is formed, and a portion of the second doped region located under a bottom of the second source region is a second implanted region formed based on the first trench.

Optionally, in the above semiconductor device, further comprising: the second masking structure is arranged corresponding to the trench gate;

The second masking structure includes a third doped region within the epitaxial layer; the third doped region covers part of the bottom of the trench gate and is connected with two second doped regions opposite to each other in the first direction;

the first direction is parallel to the plane of the semiconductor substrate and perpendicular to the length direction of the first groove.

Optionally, in the semiconductor device, a depth of the first trench is greater than a depth of the second trench;

the part of the second doped region opposite to the side wall of the second source region and the third doped region are the same first doped region formed by the same ion implantation, the upper surface of the first doped region is flush with the upper surface of the epitaxial layer, and the bottom depth of the first doped region is greater than the depth of the second groove and less than the depth of the first groove.

the upper surface of the third doped region is positioned below the bottom of the well region, and the bottom of the third doped region is positioned above the bottom of the first groove.

Optionally, in the semiconductor device, the second masking structure further includes a fourth doped region, where the fourth doped region at least covers a part of the bottom of the trench gate and is not in contact with the first masking structure;

the third doped regions and the fourth doped regions are alternately distributed in the length direction of the second groove, and the third doped regions and the fourth doped regions are not contacted.

A second aspect of the present application provides a method for manufacturing any one of the above semiconductor devices, including:

Providing a semiconductor substrate, wherein one side surface of the semiconductor substrate is provided with an epitaxial layer; a well region is arranged in the surface of one side of the epitaxial layer, which faces away from the semiconductor substrate;

forming a trench source electrode, a trench gate electrode and a first masking structure in the surface of one side of the epitaxial layer, which is away from the semiconductor substrate; wherein,

Optionally, in the above preparation method, the method for forming the first masking structure includes:

Forming a first implantation region in a region of the epitaxial layer corresponding to the first trench by first ion implantation before forming the first trench;

after forming the first groove, forming an isolation layer on the side wall of the first groove, wherein the isolation layer is exposed out of the bottom of the first groove;

Forming a second implantation region in the epitaxial layer at the bottom of the first trench through second ion implantation;

The width of the first injection region is larger than that of the first groove, the depth of the first groove is larger than that of the first injection region, and the first groove penetrates through the first injection region from the middle of the first injection region to form a part of the second doped region on the side wall of the second source region; the second implant region is used to form portions of the first and second doped regions below the bottom of the second source region.

Optionally, in the above preparation method, further comprising: forming a second masking structure within the semiconductor substrate;

Optionally, in the above preparation method, the method for forming the second masking structure includes:

Forming a first implantation region in the epitaxial layer corresponding to the region of the second groove synchronously through the first ion implantation;

The first injection region corresponding to the trench gate region is used for forming the third doped region, the upper surface of the first injection region is flush with the upper surface of the epitaxial layer, and the bottom depth of the first injection region is greater than the depth of the second trench and less than the depth of the first trench.

forming an implant region within the epitaxial layer for use as a third doped region based on a single ion implantation;

wherein the depth of the first groove is greater than the depth of the second groove; the upper surface of the third doped region is positioned below the bottom of the well region, and the bottom of the third doped region is positioned above the bottom of the first groove.

Optionally, in the above preparation method, the second masking structure further includes a fourth doped region, where the fourth doped region at least covers a part of the bottom of the trench gate and is not in contact with the first masking structure; the third doped regions and the fourth doped regions are alternately distributed in the length direction of the second groove, and the third doped regions and the fourth doped regions are not contacted.

By means of the technical scheme, in the semiconductor device and the manufacturing method thereof, the trench source electrode is respectively arranged on two sides of the trench gate electrode, the first masking structure is arranged in the region corresponding to the epitaxial layer and the trench source electrode, and the electric field of the trench gate electrode can be shielded based on the trench source electrode and the first masking structure, so that the gate dielectric layer in the trench gate electrode can be effectively prevented from being broken down by the electric field, and the voltage resistance of the device is improved.

The first masking structure includes a first doped region and a second doped region. On the one hand, the first doped region is located in the epitaxial layer below the bottom of the first source region, does not cover the side wall of the first source region or covers the side wall of the first source region close to the bottom of the first groove, and is located below the opposite region of the groove source electrode and the groove gate electrode, namely below the channel region, so that diffusion of injected ions forming the first doped region can be prevented from polluting the channel region between the groove gate electrode and the groove source electrode, further reduction of a device cell is facilitated, and the effective area of the cell is increased. On the other hand, the first masking structure can be electrically connected with the metal source electrode through the second doping region, so that the first masking structure is prevented from weakening or failing in the electric field masking effect due to suspension depletion during the switching process of the device.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings required for the description of the embodiments or the prior art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to the provided drawings without inventive effort to those skilled in the art.

The structures, proportions, sizes, etc. shown in the drawings are shown only in connection with the present disclosure, and therefore should not be construed as limiting the application, but rather as limiting the scope of the application, so that any structural modifications, proportional changes, or dimensional adjustments should fall within the scope of the application without affecting the efficacy or achievement thereof.

Fig. 1 is a cross-sectional view of a conventional semiconductor device having a dual trench source;

fig. 2 is a schematic diagram of layout design of a doped region in an epitaxial layer in a semiconductor device according to an embodiment of the present application;

FIG. 3 is a cross-sectional view of the semiconductor device in the position A-A' of FIG. 2;

FIG. 4 is a cross-sectional view of the semiconductor device in the position B-B' in FIG. 2;

fig. 5 is a schematic diagram of layout design of a doped region in an epitaxial layer in another semiconductor device according to an embodiment of the present application;

FIG. 6 is a cross-sectional view of the semiconductor device at the position C-C' in FIG. 5;

FIG. 7 is another cross-sectional view of the semiconductor device at the position C-C' in FIG. 5;

Fig. 8 is a schematic diagram of layout design of a doped region in an epitaxial layer in a semiconductor device according to another embodiment of the present application;

FIG. 9 is a cross-sectional view of the semiconductor device in the B-B' position of FIG. 8;

Fig. 10 is a schematic diagram of layout design of a doped region in an epitaxial layer in a semiconductor device according to another embodiment of the present application;

FIG. 11 is a cross-sectional view of the semiconductor device in the position B-B' in FIG. 10;

fig. 12 to fig. 30 are schematic product structures of a semiconductor device manufacturing method according to an embodiment of the present application at different process steps.

Reference numerals:

10-an electric field masking layer; 11-a semiconductor substrate; 12-an epitaxial layer; 13-trench source; 131-a first source region; 132-a second source region; 14-trench gate; 141-gate dielectric layer; 15-well region; 16-a first trench; 17-a second trench; 18-a first masking structure; 19-a metal source; 20-a second masking structure; 21-a first contact region; 22-a second contact region; 23-mask layer; 24-a first implanted region; 25-isolating layer; 26-a second implanted region; 31-a first doped region; 32-a second doped region; 33-a third doped region; 34-fourth doped region.

Detailed Description

Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown. As one of ordinary skill in the art can know, with the development of technology and the appearance of new scenes, the technical scheme provided by the embodiment of the application is also applicable to similar technical problems.

It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application. The terminology used in the embodiments of the application is for the purpose of describing particular embodiments of the application only and is not intended to be limiting of the application.

The wide band gap or ultra-wide band gap semiconductor material has excellent optical and electrical properties, and the semiconductor device adopting the wide band gap or ultra-wide band gap semiconductor material has larger band gap, so that the semiconductor device can be applied to a plurality of extremely severe environments. Higher drilling speeds and lower failure rates can be achieved, as in the context of geothermal energy production and oil and gas production; such as at high temperatures, to allow for higher operating temperatures in electronic sensor controlled aluminum, steel, and coal and gas fired power plants, thereby improving the energy efficiency of these industrial processes.

Taking trench MOSFET devices as an example, semiconductor devices of wide band gap or ultra wide band gap semiconductor materials still have some problems to be ameliorated: if the protection capability of the trench gate is insufficient, the electric field at the trench corner of the trench gate is easy to gather, and the gate dielectric layer is easy to be broken down rapidly under high drain voltage.

Although the above-described problem can be solved by forming an electric field masking structure grounded inside the semiconductor device to reduce the electric field of the trench gate at the trench corner position. But in order to ensure dynamic reliability of the semiconductor device, it is necessary to construct an electric field masking structure in the cell structure of each device unit. The electric field masking structure generally needs to pass through an ultra-high energy ion implantation device, and scattering caused by high-temperature and high-energy ion implantation can cause that the cell line width in the semiconductor device can not be further reduced, so that continuous iterative optimization is difficult.

Referring to fig. 1, fig. 1 is a cross-sectional view of a conventional semiconductor device having a dual trench source, the semiconductor device comprising:

a semiconductor substrate 11;

an epitaxial layer 12 on the surface of the semiconductor substrate 11;

a trench gate 14 and two trench sources 13 are arranged in the upper surface of the epitaxial layer 12, and the trench gate 14 is positioned between the two trench sources 13;

The epitaxial layer 12 has an electric field masking layer 10 within its surface that surrounds the trench source 13. Wherein the electric field masking layer 10 is uniformly constant in the length direction of the trench source 13.

In the semiconductor device shown in fig. 1, a trench source 13 is disposed on both sides of a trench gate 14, and an electric field shielding layer 10 surrounding the trench source 13 is disposed, and the electric field of the trench gate 14 is shielded by the trench source 13 and the electric field shielding layer 10. Although this method can effectively prevent the gate dielectric layer 141 in the trench gate 14 from being broken down, when the device cell is further reduced, the channel region between the trench source 13 and the trench gate 14 is abnormal due to scattering of the implanted ions (black circles in fig. 1) forming the electric field shielding layer 10 due to the reduced distance between the trench source 13 and the trench gate 14. This problem results in difficulty in device cell size reduction and a lower cell effective area.

In order to solve the above-described problems, an embodiment of the present application provides a semiconductor device including:

Two first grooves and a second groove positioned between the first grooves are formed in the surface of one side of the epitaxial layer, which is away from the semiconductor substrate, and the depth of each of the first grooves and the depth of each of the second grooves are larger than that of the well region; a groove source electrode is arranged in the first groove; a trench gate is arranged in the second trench; the trench gate includes first source regions and second source regions alternately distributed in a length direction of the first trench;

In the semiconductor device provided by the embodiment of the application, the trench source electrodes are respectively arranged at the two sides of the trench gate electrode, and the first masking structure is arranged in the region of the epitaxial layer corresponding to the trench source electrodes, so that the electric field of the trench gate electrode can be shielded based on the trench source electrodes and the first masking structure, thereby effectively preventing the gate dielectric layer in the trench gate electrode from being broken down by the electric field and improving the voltage resistance of the device.

The foregoing is a core concept of the technical solution of the embodiments of the present application, and in order to make the above objects, features and advantages of the present application more obvious and understandable, the present application will be described in further detail below with reference to the accompanying drawings and specific embodiments.

Referring to fig. 2-4, fig. 2 is a schematic diagram illustrating a layout design of a doped region in an epitaxial layer in a semiconductor device according to an embodiment of the present application, fig. 3 is a cross-sectional view of the semiconductor device at A-A 'position in fig. 2, and fig. 4 is a cross-sectional view of the semiconductor device at B-B' position in fig. 2.

As shown in fig. 2 to 4, the semiconductor device includes:

A semiconductor substrate 11, wherein one side surface of the semiconductor substrate 11 is provided with an epitaxial layer 12; the epitaxial layer 12 has a well region 15 in a surface of a side facing away from the semiconductor substrate 11;

The epitaxial layer 12 is provided with two first grooves 16 and a second groove 17 positioned between the first grooves 16 in the surface of one side facing away from the semiconductor substrate 11, and the depth of each of the first grooves 16 and the second grooves 17 is larger than that of the well region 15; a trench source 13 is arranged in the first trench 16; a trench gate 14 is arranged in the second trench 17; the trench source 13 includes first source regions 131 and second source regions 132 alternately distributed in a length direction (vertical direction in fig. 2) of the first trench;

The trench sources 13 are each provided with a first masking structure 18, and the first masking structure 18 includes: the first doped region 31, the first doped region 31 is located in the epitaxial layer 12 opposite to the bottom of the first source region 131; the second doped region 32, the second doped region 32 is located in the epitaxial layer 12 opposite to the bottom and the sidewall of the second source region 132, and the second doped region 32 is connected to the metal source 19 above the epitaxial layer 12.

In the semiconductor device provided by the embodiment of the application, the trench source electrode 13 is respectively arranged at two sides of the trench gate electrode 14, and the first masking structure 18 is arranged in the region of the epitaxial layer 12 corresponding to the trench source electrode 13, and the electric field of the trench gate electrode 14 can be shielded based on the trench source electrode 13 and the first masking structure 18, so that the gate dielectric layer 141 in the trench gate electrode 14 can be effectively prevented from being broken down by the electric field, and the voltage resistance of the device is improved.

Alternatively, two trench sources 13 may be symmetrically disposed at both sides of the trench gate 14. In other embodiments, the two trench sources 13 may also have an asymmetric structure.

Alternatively, the first masking structures 18 corresponding to the two trench sources 13 may be symmetrically disposed on both sides of the trench gate 14. In other embodiments, the first masking structures 18 corresponding to the two trench sources 13 may also be asymmetric structures.

Wherein the first masking structure 18 comprises a first doped region 31 and a second doped region 32.

On the one hand, the first doped region 31 is located in the epitaxial layer 12 below the bottom of the first source region 131, and does not cover the sidewall of the first source region 131, i.e., the first doped region 31 is located below the bottom of the first trench 16, and the first doped region 31 does not exceed the bottom coverage area of the first trench 16, so that the first doped region 31 not only can realize electric field masking of the area where the first doped region 31 is located, but also, since the injection region of the first doped region 31 is located in the area of the epitaxial layer 12 opposite to the first trench 16, the first doped region 31 does not cover the sidewall of the first source region 131 or cover the sidewall of the first source region 131 near the bottom of the first trench, and the first doped region 31 is located below the opposite area of the trench source 13 and the trench gate 14, i.e., below the trench region, and the injected ions of the first doped region 31 will not pollute the trench 16 and the trench 17, and the problem of conduction abnormality of the trench region due to scattering will not occur when the first doped region 31 of the first source region 131 is further reduced in size of the device cell. Therefore, the diffusion of the implanted ions during the formation of the first doped region 31 can be prevented from contaminating the channel region between the trench gate 14 and the trench source 13, which is convenient for further reduction of the device cell, so as to increase the effective cell area.

On the other hand, the first masking structure 18 may be electrically connected to the metal source 19 through the second doped region 32 to prevent the first masking structure 18 from weakening or failing the electric field masking effect due to suspended depletion during switching of the device.

In the embodiment of the present application, in the same trench source 13, the area ratio of the first source region 131 is larger than the area ratio of the second source region 132, so that the cross-sectional view corresponding to the A-A' position is the main structure of the device.

If the first masking structures 18 corresponding to the two trench source electrodes 13 are symmetrically disposed on two sides of the trench gate electrode 14, as shown in fig. 2, the first doped regions 31 in one first masking structure 18 are disposed opposite to the first doped regions 31 in the other first masking structure 18 in the first direction (horizontal direction in fig. 2), and the second doped regions 32 in one first masking structure 18 are disposed opposite to the second doped regions 32 in the other first masking structure 18 in the first direction.

In one implementation of the embodiment of the present application, as shown in fig. 4, a portion of the second doped region 32 opposite to the sidewall of the second source region 132 extends to the upper surface of the epitaxial layer 12 to be connected to the metal source 19. In this manner, the second doped region 32 may be electrically connected directly to the metal source 19 to prevent the first masking structure 18 from weakening or failing the electric field masking effect due to suspended depletion during switching of the device.

In other embodiments, the portion of the second doped region 32 opposite to the sidewall of the second source region 132 may also extend at least to the well region 15, so as to connect with the metal source 19 based on the well region 15 or the contact region in the well region, so as to prevent the first masking structure 18 from weakening or failing the electric field masking effect due to suspended depletion during the switching process of the device.

In one implementation of the embodiment of the present application, in the same first masking structure, the portion of the second doped region 32 under the bottom of the second source region 132 and the first doped region 31 are the same implantation region formed by the same ion implantation. The portion of the second doped region 32 below the bottom of the second source region 132 and the first doped region 31 are both within the epitaxial layer 12 below the bottom of the first trench 16, so that both can be simultaneously fabricated within the epitaxial layer 12 below the bottom of the first trench 16 by the same ion implantation.

In one aspect, the portion of the second doped region 32 below the bottom of the second source region 132 and the first doped region 31 can be simultaneously fabricated, and the fabrication process is simple and the fabrication cost is low.

On the other hand, based on the ion implantation performed by the first trench 16, the portion of the second doped region 32 below the bottom of the second source region 132 and the first doped region 31 are formed in the epitaxial layer 12 below the bottom of the first trench 16, as shown in fig. 3 and fig. 4, the portion of the second doped region 32 below the bottom of the second source region 132 and the first doped region 31 are formed simultaneously, and are the same implanted region, and have the same thickness, and the upper surface of the implanted region is the bottom of the first trench 16, that is, the initial position of the ion implantation is the bottom of the first trench 16, so that the ion implantation depth is greatly reduced compared with the manner of ion implantation starting from the upper surface of the epitaxial layer 12. The energy of ion implantation can be reduced, and thus the problem of contamination of the channel region by diffusion of implanted ions caused by an excessively high ion implantation energy can be prevented.

In the embodiment of the present application, the portion of the second doped region 32 located on the sidewall of the second source region 132 is a first implanted region formed before the first trench 16 is formed, and the portion of the second doped region 32 located under the bottom of the second source region 132 is a second implanted region formed based on the first trench 16.

Before forming the first trench 16, a first implantation region is formed, where the first implantation region is used to form a portion of the second doped region 32 located on the sidewall of the first trench 16, where the implantation region is located in the epitaxial layer 12 above the bottom of the first trench 16, where the implantation depth is shallower, and ion implantation can be performed from the upper surface of the epitaxial layer 12, where the ion implantation energy is smaller, and where the implanted ions can be well controlled in a first target region, where the portion of the second doped region 32 located on the sidewall of the first trench 16 is located, where no problem of obvious ion scattering pollution to the channel region occurs.

After the first trench 16 is formed, the second implantation region is formed, and ion implantation can be performed based on the first trench 16, so that the implantation starting position of the second implantation region is the bottom of the first trench 16, and compared with the manner of performing ion implantation from the upper surface of the epitaxial layer 12, the implantation depth of the second implantation region can be greatly reduced, so that the energy of the implanted ions is reduced, the implanted ions can be well controlled in the second target region, and the second target region is the epitaxial layer region where the portion of the second doped region 32 below the bottom of the first trench 16 is located, so that the problem of obvious ion scattering pollution to the channel region does not occur.

As can be seen from the above description, the second doped region 32 is formed based on the first implanted region and the second implanted region formed by two ion implantations, so that the ion implantation energy can be reduced, and the channel region can be prevented from being polluted by the ion implantation process for forming the second doped region 32, which is convenient for further reducing the size of the device cell and increasing the effective area of the cell.

The first doped region 31 contacts the bottom of the first trench 16, and the second doped region 32 contacts the bottom and the sidewall of the first trench 16, so as to achieve a better electric field shielding effect.

In one implementation of the embodiment of the present application, as shown in fig. 2, the first masking structures 18 corresponding to the two trench sources 13 may be respectively provided to be implantation regions separated from each other in the epitaxial layer 12. In other embodiments, as described below, the second masking structure 20 may be further disposed in the epitaxial layer 12, and the first masking structures 18 on two sides of the trench gate 14 are connected through the third doped region 33 in the second masking structure 20 to form a grid-shaped masking structure, so that the voltage-resistant performance of the device may be better improved.

Referring to fig. 5 and 6, fig. 5 is a schematic diagram illustrating a layout design of a doped region in an epitaxial layer in another semiconductor device according to an embodiment of the present application, and fig. 6 is a cross-sectional view of the semiconductor device at a position C-C' in fig. 5. The cross-sectional views of fig. 5 at the A-A 'and B-B' positions are the same as the cross-sectional views at the same positions in fig. 2.

Unlike the above embodiment, in the manner shown in fig. 5 and 6, the semiconductor device further includes: a second masking structure 20 disposed in correspondence with trench gate 14; second masking structure 20 includes a third doped region 33 within epitaxial layer 12; the third doped region 33 wraps part of the bottom of the trench gate 14 and connects two second doped regions 32 opposite in the first direction; the first direction (horizontal direction in fig. 5) is parallel to the plane of the semiconductor substrate 11 and perpendicular to the length direction of the first trench 16. Wherein the third doped region 33 is in contact with the bottom of the second trench 17 to achieve a better electric field shielding effect.

Based on the third doped region 33, the first masking structure 18 and the second masking structure 20 can be connected into grids, so that a grid-shaped masking structure is formed in the epitaxial layer 12, a better electric field shielding effect is achieved, the trench gate 14 can be better protected, and the voltage resistance of the device is further improved. The grid-like masking structure may be connected to the metal source 19 in the second doped region 32 or to the metal source 19 in the second doped region 32 and the third doped region 33, respectively, to prevent the first masking structure 18 from weakening or failing the electric field masking effect due to suspended depletion during switching of the device.

In the embodiment of the application, the depth of the first trench 16 is greater than the depth of the second trench 17, so that the depth of the trench source 13 is greater than the depth of the trench gate 14, and the trench source 13 at two sides of the trench gate 14 and the first masking structure 18 better shield the electric field of the trench gate 14, so as to prevent the gate dielectric layer 141 from being broken down, thereby better improving the voltage-withstanding performance of the device.

In one embodiment, as shown in fig. 6, a portion of the second doped region 32 opposite to the sidewall of the second source region 132 and the third doped region 33 are the same first doped region formed by the same ion implantation, and the upper surface of the first doped region is flush with the upper surface of the epitaxial layer 12, and the bottom depth of the first doped region is greater than the depth of the second trench 17 and less than the depth of the first trench 16. In this manner, ion implantation may be performed in the epitaxial layer 12 before forming the first trench 16 to form a first implantation region, and the third doped region 33 and the second doped region 32 integrally connected by the first implantation region after forming the first trench 16.

Referring to fig. 7, fig. 7 is another cross-sectional view of the semiconductor device at the position C-C' in fig. 5, which is different from the manner shown in fig. 6 in that in the manner shown in fig. 7, the upper surface of the third doped region 33 is located below the bottom of the well region 15, a space is provided between the third doped region 33 and the well region 15, the bottom of the third doped region 33 is located above the bottom of the first trench 16, and the bottom of the third doped region 33 is spaced from the bottom of the first trench 16.

Referring to fig. 8 and 9, fig. 8 is a schematic diagram illustrating a layout design of a doped region in an epitaxial layer in a semiconductor device according to still another embodiment of the present application, and fig. 9 is a cross-sectional view of the semiconductor device at a position B-B' in fig. 8. The cross-sectional views of fig. 8 at the A-A 'and C-C' positions are the same as the cross-sectional views at the same positions in fig. 5.

Unlike the above embodiment, for the cut-away view of the B-B' position, in the manner shown in fig. 8 and 9, the second masking structure 20 further comprises a fourth doped region 34, the fourth doped region 34 at least partially covering the bottom of the trench gate 14 and not contacting the first masking structure 18; the third doped regions 33 and the fourth doped regions 34 are alternately distributed along the length direction of the second trench 17, and the third doped regions 33 and the fourth doped regions 34 are not contacted.

In the manner shown in fig. 9, the fourth doped region 34 may cover a portion of the bottom of the trench gate 14 as shown in fig. 9, and cover a portion of the sidewall of the trench gate 14 near the bottom of the second trench.

Referring to fig. 10 and 11, fig. 10 is a schematic diagram illustrating a layout design of a doped region in an epitaxial layer in a semiconductor device according to still another embodiment of the present application, and fig. 11 is a cross-sectional view of the semiconductor device at a position B-B' in fig. 10. The cross-sectional views of fig. 11 at the A-A 'and C-C' positions are the same as the cross-sectional views at the same positions in fig. 5 and 8.

Unlike the above embodiment, for the cut-away view of the B-B' position, in the manner shown in fig. 10 and 11, the fourth doped region 34 is located in the epitaxial layer 12 below the bottom of the trench gate 14 and does not laterally exceed the shielding range of the trench gate 14, i.e., the fourth doped region 34 is located between the opposite sidewalls of the second trench 17.

In the first direction, a third doped region 33 may be disposed between two opposite second doped regions 32, and the third doped region 33 connects the two second doped regions 32; a fourth doped region 34 may be disposed between the two opposing second doped regions 32 with a distance between the fourth doped region 34 and the two second doped regions 32. In other ways, in the first direction, a fourth doped region 34 may also be provided between two opposite first doped regions 31. The relative positions of the fourth doped region 34 with respect to the first doped region 31 and the second doped region 32 are not limited in the embodiments of the present application.

The semiconductor device provided by the embodiment of the application further comprises an ohmic contact region arranged in the surface of the well region 15, wherein the ohmic contact region comprises first contact regions 21 and second contact regions 22 which are alternately distributed in the surface of the well region 15. Wherein the doping type of the first contact region 21 and the second contact region are different.

In the semiconductor device, the doping type of first masking structure 18 and second masking structure 20 is the same and different from the doping type of epitaxial layer 12. Well region 15 is of a different doping type than epitaxial layer 12. The doping type of the semiconductor substrate 11 is the same as the doping type of the epitaxial layer 12.

In the embodiment of the application, the doping type comprises P type doping and N type doping. For two objects with different doping types in the semiconductor device, one is P-type doping, and the other is N-type doping. For two objects with the same doping type in the semiconductor device, the two objects are both doped with N type or both doped with P type.

In one embodiment, the well region 15, the first contact region 21, the first masking structure 18 and the second masking structure 20 may be P-type doped, for example, the well region 15 may be P-doped, the first masking structure 18 and the second masking structure 20 may be p+ doped, and the first contact region 21 may be p++ doped, where the doping concentrations of the P-, p++ and p++ doped sequentially increase. The epitaxial layer 12 may be provided as N-doped, the semiconductor substrate 11 as n+ doped, and the second contact region 22 as n++ doped, wherein the doping concentrations of the N-, n+ and n++ doped are sequentially increased.

In the embodiment of the application, the semiconductor device can be a MOS device, and further, the semiconductor device can be an NMOS device or a PMOS device. The doping types of each part in the semiconductor device can be set corresponding to the NMOS device or the PMOS device, and the doping types and the doping concentrations of different areas in the semiconductor device are not limited in the embodiment of the application.

As can be seen from the above description, the structure of the semiconductor device having the dual-trench source 13 is improved, and a novel dual-trench source semiconductor device is designed, in which the first masking structure 18 and the second masking structure 20 having periodic structures are formed in the epitaxial layer 12, and the masking structures in the epitaxial layer 12 can be periodically connected to the metal source 19 based on the second doped region 32 or the third doped region 33. The semiconductor device can avoid scattering pollution of the channel region caused by the injected ions of the first masking structure 18 when the size of the device cell is further reduced, avoid abnormal conduction of the channel region caused by the scattering pollution, and prevent the problem that the electric field masking effect of the device is weakened or even fails due to suspension depletion in the switching process.

On the basis of the above embodiment, another embodiment of the present application further provides a method for manufacturing a semiconductor device, which is used for manufacturing the semiconductor device according to any one of the foregoing embodiments.

Referring to fig. 12 to fig. 30, fig. 12 to fig. 30 are schematic product structures of a semiconductor device manufacturing method according to an embodiment of the present application in different process steps, where the manufacturing method includes:

step S11: as shown in fig. 12 and 13, a semiconductor substrate 11 is provided, and one side surface of the semiconductor substrate 11 has an epitaxial layer 12; the epitaxial layer 12 has a well region 15 in a surface of a side facing away from the semiconductor substrate 11.

First, as shown in fig. 12, an epitaxial layer 12 is formed on the surface of a semiconductor substrate 11. Alternatively, the semiconductor substrate 11 may be a wide band gap or ultra wide band gap semiconductor material, such as any one of a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, a gallium oxide (Ga ₂O₃) substrate, a diamond (C) substrate, and an aluminum nitride (AlN) substrate. An N-doped epitaxial layer 12 may be formed on the surface of the n+ doped semiconductor substrate 11 by an epitaxial process.

Then, as shown in fig. 13, a well region 15 and first and second contact regions 21 and 22 located in the well region 15 are formed in the upper surface of the epitaxial layer 12 by ion implantation. A P-doped well region 15 may be formed in the upper surface of the epitaxial layer 12 by P-type ion implantation, a p++ doped first contact region 21 may be formed in the well region 15 by P-type ion implantation, and an n++ doped second contact region 22 may be formed in the well region 15 by N-type ion implantation.

Step S12: as shown in fig. 14-28 and related figures in the semiconductor device embodiment, a trench source 13, a trench gate 14, and a first masking structure 18 are formed in a surface of the epitaxial layer 12 on a side facing away from the semiconductor substrate 11.

Wherein, the epitaxial layer 12 has two first trenches 16 and a second trench 17 between the first trenches 16 in a side surface facing away from the semiconductor substrate 11, and the depths of the first trenches 16 and the second trenches 17 are both greater than the depth of the well region 15; a trench source 13 is arranged in the first trench 16; a trench gate 14 is arranged in the second trench 17; the trench source 13 includes first source regions 131 and second source regions 132 alternately distributed in the length direction of the first trench 16. The trench sources 13 are each provided with a first masking structure 18, and the first masking structure 18 includes: the first doped region 31, the first doped region 31 is located in the epitaxial layer 12 opposite to the bottom of the first source region 131; the second doped region 32, the second doped region 32 is located in the epitaxial layer 12 opposite to the bottom and the sidewall of the second source region 132, and the second doped region 32 is connected to the metal source 19 above the epitaxial layer 12.

In the above-described method of making, the method of forming the first masking structure 18 includes:

Step S21: as shown in fig. 14 or 15, a first implant region 24 is formed in the epitaxial layer 12 in the region corresponding to the first trench 16 by a first ion implantation prior to forming the first trench 16. A patterned mask layer 23 may be formed on the upper surface of the epitaxial layer 12 according to a predetermined layout, and ion implantation may be performed based on the mask layer 23 to form the first implantation region 24. In this step, if the layout shown in FIG. 2 or FIG. 5 is used, the cross-sectional view at the B-B' position is shown in FIG. 14; if the layout shown in FIG. 10 is used, a cross-sectional view at the B-B' position is shown in FIG. 15.

In fig. 14, the width of the first implantation region 24 corresponding to the trench source 13 is greater than the width of the first trench 16, so that after the first trench 16 is formed, a portion of the first implantation region 24 can be remained in the epitaxial layer 12 opposite to both sides of the first trench 16, thereby forming a portion of the second doped region 32 on the sidewall of the first source region 131. In fig. 15, the width of the first implanted region 24 corresponding to the trench gate 14 is not greater than the width of the second trench 17, so that only a portion of the first implanted region 24 located under the second trench 17 remains as the fourth doped region 34 after the second trench 17 is formed.

In step S21, the ion implantation is used to form the portion of the second doped region 32 on the sidewall of the trench source 13, and the implantation of the first doped region 31 is not involved, so the first doped region 31 is formed in a subsequent process.

Step S22: as shown in fig. 16 to 21, after the first trench 16 is formed, an isolation layer 25 is formed on the sidewall of the first trench 16, and the isolation layer 25 exposes the bottom of the first trench 16.

First, as shown in fig. 16 to 18, the first trench 16 is formed. Wherein FIG. 16 is a cross-sectional view of each layout at A-A ', FIG. 17 is a cross-sectional view of the layout shown in FIGS. 2 and 5 at B-B ', and FIG. 18 is a cross-sectional view of the layout shown in FIG. 10 at B-B '. In order to avoid affecting the first implanted regions 24 of the corresponding areas of the second trenches 17 when etching the first trenches 16, a new mask layer 23 is required to mask the first implanted regions 24 of the corresponding second trenches 17 before forming the first trenches 16, as compared to fig. 15 and 18. In comparison with fig. 14 and 17, in comparison with fig. 15 and 18, in order to retain a portion of the first implant region 24 on both sidewalls of the first trench 16, a new mask layer 23 is required to mask an edge portion of the first implant region 24 corresponding to the first trench 16 and expose a region of the first implant region 24 in between where the first trench 16 needs to be etched before the first trench 16 is formed.

Then, on the basis of fig. 16 to 18, as shown in fig. 19 to 21, an isolation layer 25 is formed. The isolation layer 25 may be prepared during this process based on CVD or ALD processes.

Step S23: on the basis of fig. 19 to 21, as shown in fig. 22 to 24, a second implantation region 26 is formed in the epitaxial layer 12 at the bottom of the first trench by a second ion implantation.

Wherein the width of the first implantation region 24 is greater than the width of the first trench 16, the depth of the first trench 16 is greater than the depth of the first implantation region 24, and the first trench 16 penetrates the first implantation region 24 from the middle of the first implantation region 24 to form a portion of the second doped region 32 on the sidewall of the second source region 132; the second implant region 26 is used to form the first doped region 31 and the portion of the second doped region 32 below the bottom of the second source region 132.

Ion implantation is performed on the bottom of the first trench 16 based on the isolation layer 25 covered by the sidewall of the first trench 16, and a second implantation region 26 is formed. The second implant region 26 corresponding to the first source region 131 may serve as the first doped region 31. The second implant region 26 corresponding to the second source region 132 may be connected to the opposite first implant region 24 integrally to form the second doped region 32.

Since the first doped region 31 corresponding to the first source region 131 with a larger cell area of the device is mainly located in the epitaxial layer 12 below the bottom of the trench source 13 and below the trench gate 14, i.e. the first doped region 31 is located below the channel region. Even if the first doped region 31 diffuses upwards at the bottom of the first trench 16 by a certain distance during the formation of the second implanted region 26, the first doped region 31 exceeds the bottom coverage area of the first trench 16, and the second implanted region 26 is implanted by the first trench 16 to have a smaller implantation depth, so that the ion implantation energy is smaller, the problem of ion implantation pollution to the channel region during the formation of the first doped region 31 does not occur, and the conduction performance of the channel region is not affected.

In the preparation process of the semiconductor device, the ion implantation depth and implantation energy of the first doping region 31 and the second doping region 32 are low, so that the channel region can be effectively prevented from being polluted by the implanted ions, the device cell can be further reduced, and the effective area of the cell can be increased.

After forming the second implant region 26, the spacer 25 is removed as shown in fig. 25-27 on the basis of fig. 22-24. The isolation layer 25 may be a silicon oxide layer, and a wet etching agent such as HF solution may be used to remove the isolation layer 25, and a cleaning process may be combined to remove surface stains. And (3) drying after cleaning, and then performing high-temperature activation annealing to activate implanted ions. Optionally, the high-temperature ion activation process temperature of the silicon carbide device can be 1500-1900 ℃, and the process duration can be 10-30 min.

Thereafter, as shown in fig. 28 to 30, on the basis of fig. 25 to 27, etching is performed based on the new mask layer 23 to form the second trench 17.

In a subsequent process, an oxide layer is formed on the surfaces of the first trench 16 and the second trench 17 by oxidation of the trench sidewalls. The oxide layer covered on the surface of the second trench 17 serves as a gate dielectric layer 141. After an oxide layer is formed on the surface of the trench, polysilicon is filled in the trench to form a trench gate 14 and a trench source 13. Finally, preparing a surface metal electrode, comprising a metal source electrode 19 on the front surface and a metal drain electrode on the back surface of the semiconductor substrate 11, so as to form a MOS structure.

The preparation method provided by the embodiment of the application further comprises the steps of forming a second masking structure 20 in the semiconductor substrate 11; second masking structure 20 includes a third doped region 33 within epitaxial layer 12; the third doped region 33 wraps part of the bottom of the trench gate 14 and connects two second doped regions 32 opposite in the first direction; wherein the first direction is parallel to the plane of the semiconductor substrate 11 and perpendicular to the length direction of the first trench 16. The structure of the third doped region 33 can be seen in fig. 5-7 with reference to the above-described embodiments.

Optionally, the method of forming second masking structure 20 includes: by the first ion implantation, a first implantation region 24 is formed simultaneously in the epitaxial layer 12 in the region corresponding to the second trench 17. Wherein the first implantation region 24 corresponding to the trench gate region is used to form a third doped region; the upper surface of the first implant region 24 is flush with the upper surface of the epitaxial layer 12, and the bottom depth of the first implant region 24 is greater than the depth of the second trench 17 and less than the depth of the first trench 16. In this manner, the second doped region 32 and the third doped region 33 may be formed simultaneously during the formation of the first implanted region 24, and the device structure is as shown in fig. 6.

In other aspects, a method of forming second masking structure 20 includes: forming an implantation region for serving as a third doping region 33 in the epitaxial layer 12 based on the single ion implantation; wherein the depth of the first trench 16 is greater than the depth of the second trench 17; the upper surface of the third doped region 33 is located below the bottom of the well region 15, and the bottom of the third doped region 33 is located above the bottom of the first trench 16. In this manner, the third doped region 33 may be formed based on a single ion implantation, the device structure being as shown in fig. 7.

In the preparation method provided by the embodiment of the application, the second masking structure 20 further comprises a fourth doped region 34, and the fourth doped region 34 at least covers part of the bottom of the trench gate 14 and is not contacted with the first masking structure 18; the third doped regions 33 and the fourth doped regions 34 are alternately distributed along the length direction of the second trench 17, and the third doped regions 33 and the fourth doped regions 34 are not contacted, so that the device structure is as shown in fig. 9 or 11. In this manner, before forming the second trenches 17, ion implantation may be performed at the regions corresponding to the trench gates 14 by a single ion implantation to form the fourth doped regions 34. The implantation regions corresponding to the third doped region 33 and the fourth doped region 34 may be formed by the same ion implantation or may be formed by one ion implantation respectively.

When the manufacturing method of the semiconductor device is needed to be described, the manufacturing method of the semiconductor device is not limited to the process sequence and the layout design provided by the embodiment of the application, and the process sequence and the layout of the semiconductor device can be flexibly designed based on the structure of the semiconductor device to be manufactured.

In the description of the present application, each embodiment is described in a progressive manner, or in parallel manner, or in a combination of progressive and parallel manners, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other. The embodiments provided by the embodiments of the application can be combined with each other without contradiction.

It is to be noted, however, that the description of the drawings and embodiments are illustrative and not restrictive. Like reference numerals refer to like structures throughout the embodiments of the specification. In addition, the drawings may exaggerate the thicknesses of some layers, films, panels, regions, etc. for understanding and ease of description. It will also be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In addition, "on …" refers to positioning an element on or under another element, but not essentially on the upper side of the other element according to the direction of gravity.

The terms "upper," "lower," "top," "bottom," "inner," "outer," and the like are used for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not denote or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the application. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or device comprising the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor device, comprising:

A semiconductor substrate, wherein one side surface of the semiconductor substrate is provided with an epitaxial layer; a well region is arranged in the surface of one side of the epitaxial layer, which faces away from the semiconductor substrate;

Two first grooves and a second groove positioned between the first grooves are formed in the surface of one side, facing away from the semiconductor substrate, of the epitaxial layer, and the depth of each of the first grooves and the depth of each of the second grooves are larger than that of the well region; a groove source electrode is arranged in the first groove; a trench gate is arranged in the second trench; the trench source electrode comprises first source regions and second source regions which are alternately distributed in the length direction of the first trench;

The trench sources are respectively and correspondingly provided with a first masking structure, and the first masking structure comprises: the first doped region is positioned in the epitaxial layer opposite to the bottom of the first source electrode region; the second doped region is positioned in the epitaxial layer with the bottom and the side wall opposite to each other and is connected with the metal source electrode above the epitaxial layer.

2. The semiconductor device of claim 1, wherein a portion of the second doped region opposite the second source region sidewall extends to an upper surface of the epitaxial layer to connect with the metal source;

or, a portion of the second doped region opposite to the second source region sidewall extends to the well region to connect with the metal source based on the well region.

3. The semiconductor device of claim 1, wherein in the same first masking structure, a portion of the second doped region below a bottom of the second source region is a same implanted region formed by the same ion implantation as the first doped region.

4. The semiconductor device of claim 1, wherein the portion of the second doped region on the sidewall of the second source region is a first implanted region formed prior to preparing the first trench, and the portion of the second doped region under the bottom of the second source region is a second implanted region formed based on the first trench.

5. The semiconductor device according to any one of claims 1 to 4, further comprising: a second masking structure arranged corresponding to the trench gate;

6. The semiconductor device according to claim 5, wherein a depth of the first trench is greater than a depth of the second trench;

7. The semiconductor device according to claim 5, wherein a depth of the first trench is greater than a depth of the second trench;

The upper surface of the third doped region is located below the bottom of the well region, and the bottom of the third doped region is located above the bottom of the first trench.

8. The semiconductor device of claim 5, wherein the second masking structure further comprises a fourth doped region that wraps around at least a portion of a bottom of the trench gate and is not in contact with the first masking structure;

9. A method for manufacturing a semiconductor device according to any one of claims 1 to 8, comprising:

forming a groove source electrode, a groove grid electrode and a first masking structure in the surface of one side of the epitaxial layer, which is away from the semiconductor substrate; wherein,

Two first grooves and a second groove positioned between the first grooves are formed in the surface of one side, facing away from the semiconductor substrate, of the epitaxial layer, and the depth of each of the first grooves and the depth of each of the second grooves are larger than that of the well region; the first groove is internally provided with the groove source electrode; the second groove is internally provided with the groove grid electrode; the trench source electrode comprises first source regions and second source regions which are alternately distributed in the length direction of the first trench;

The trench sources are respectively and correspondingly provided with the first masking structures, and the first masking structures comprise: the first doped region is positioned in the epitaxial layer opposite to the bottom of the first source electrode region; the second doped region is positioned in the epitaxial layer with the bottom and the side wall opposite to each other and is connected with the metal source electrode above the epitaxial layer.

10. The method of preparing according to claim 9, wherein the method of forming the first masking structure comprises:

After the first groove is formed, forming an isolation layer on the side wall of the first groove, wherein the isolation layer exposes the bottom of the first groove;

forming a second implantation region in the epitaxial layer at the bottom of the first groove through second ion implantation;

The width of the first injection region is larger than that of the first groove, the depth of the first groove is larger than that of the first injection region, and the first groove penetrates through the first injection region from the middle of the first injection region to form a part of the second doping region on the side wall of the second source region; the second implantation region is used for forming a part of the first doping region and the second doping region which is positioned below the bottom of the second source region.

11. The method of manufacturing according to claim 10, further comprising: forming a second masking structure within the semiconductor substrate;

12. The method of preparing according to claim 11, wherein the method of forming the second masking structure comprises:

Forming a first implantation region in the epitaxial layer corresponding to the second trench through the first ion implantation;

The first injection region corresponding to the trench gate region is used for forming the third doped region; the upper surface of the first injection region is flush with the upper surface of the epitaxial layer, and the bottom depth of the first injection region is greater than the depth of the second groove and less than the depth of the first groove.

13. The method of preparing according to claim 11, wherein the method of forming the second masking structure comprises:

Forming an implant region within the epitaxial layer for use as the third doped region based on a single ion implantation;

Wherein the depth of the first groove is greater than the depth of the second groove; the upper surface of the third doped region is located below the bottom of the well region, and the bottom of the third doped region is located above the bottom of the first trench.

14. The method of claim 11, wherein the second masking structure further comprises a fourth doped region that covers at least a portion of the bottom of the trench gate and is not in contact with the first masking structure; the third doped regions and the fourth doped regions are alternately distributed in the length direction of the second groove, and the third doped regions and the fourth doped regions are not contacted.