CN118335803B

CN118335803B - Semiconductor device and manufacturing method thereof

Info

Publication number: CN118335803B
Application number: CN202410772967.5A
Authority: CN
Inventors: 袁俊
Original assignee: Hubei Jiufengshan Laboratory
Current assignee: Hubei Jiufengshan Laboratory
Priority date: 2024-06-14
Filing date: 2024-06-14
Publication date: 2024-08-23
Anticipated expiration: 2044-06-14
Also published as: CN118335803A

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, relating to the technical field of semiconductor devices, wherein the semiconductor device comprises: a semiconductor substrate; an epitaxial stack including a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer sequentially stacked on a surface of the semiconductor substrate; the doping types of the first epitaxial layer and the third epitaxial layer are the same as those of the semiconductor substrate, and the doping types of the second epitaxial layer and the semiconductor substrate are different; a well region, a source region and a trench gate are arranged in the surface of one side of the third epitaxial layer, which is away from the semiconductor substrate; a plurality of first doped regions disposed within the second epitaxial layer, the first doped regions having a different doping type than the second epitaxial layer; in the first direction, each first doped region has an overlapping portion with the trench gate; the first direction is perpendicular to the plane of the semiconductor substrate; and the second doping regions extend downwards from the source region to the second epitaxial layer, and the doping types of the second doping regions and the second epitaxial layer are the same.

Description

Semiconductor device and manufacturing method thereof

Technical Field

The application relates to the technical field of semiconductor devices, in particular to a semiconductor device and a manufacturing method thereof.

Background

In recent years, ultra wide band gap semiconductor materials (such as gallium oxide, diamond, aluminum nitride, etc.) having a wide band gap (such as SiC and GaN, etc.) and a larger band gap have been attracting attention from the industry due to excellent material characteristics.

Compared with the traditional Si material, the wide band gap and ultra-wide band gap semiconductor material has more advantages in physical characteristics such as the band gap, the critical breakdown electric field intensity, the electron saturation drift speed and the like, and the power device (such as a diode, a transistor and the like) prepared based on the wide band gap or ultra-wide band gap semiconductor material has more excellent electrical characteristics, can adapt to the application requirements of high power, high voltage, high frequency, high temperature and the like which cannot be met by a silicon-based device, and is also one of breakthrough paths exceeding the Moore law. Therefore, the wide band gap and ultra-wide band gap semiconductor material is widely applied to the field of new energy (such as photovoltaic, energy storage, charging piles, electric automobiles and the like), and the development of the new energy revolution is promoted.

Although the semiconductor device using the wide band gap or ultra wide band gap semiconductor material has better performance than the semiconductor device using the conventional Si material, there is still a need for improvement in the modulation performance of the current distribution.

Disclosure of Invention

In view of the above, the present application provides a semiconductor device and a method for manufacturing the same, so as to achieve the purpose of improving the modulation performance of the current distribution in the semiconductor device. The specific scheme is as follows:

A first aspect of the present application provides a semiconductor device comprising:

a semiconductor substrate;

An epitaxial stack including a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer sequentially stacked on a surface of the semiconductor substrate; the doping types of the first epitaxial layer and the third epitaxial layer are the same as those of the semiconductor substrate, and the doping types of the second epitaxial layer and the semiconductor substrate are different;

A well region, a source region and a trench gate are arranged in the surface of one side of the third epitaxial layer, which is away from the semiconductor substrate;

A plurality of first doped regions disposed within the second epitaxial layer, the first doped regions having a different doping type than the second epitaxial layer; in the first direction, each first doped region has an overlapping portion with the trench gate; the first direction is perpendicular to the plane of the semiconductor substrate;

and the second doping regions extend downwards from the source region to the second epitaxial layer, and the doping types of the second doping regions and the second epitaxial layer are the same.

Optionally, in the semiconductor device, a third doped region is further disposed in the third epitaxial layer;

The doping types of the third doping region and the second doping region are the same; the third doped region covers part of the bottom of the trench gate; the second epitaxial layer is provided with a first doped region in a region opposite to the third doped region.

Optionally, in the semiconductor device, at least one of a fourth doped region and a fifth doped region is further disposed in the third epitaxial layer;

the doping type of the fourth doping region is the same as that of the second doping region; the fourth doped region covers part of the bottom of the trench gate and also covers part of the side wall of the trench gate so as to be connected with the source region along the side wall of the trench gate; the first doped region is arranged in a region of the second epitaxial layer opposite to the fourth doped region.

The doping type of the fifth doping region is the same as that of the second doping region; the fifth doped region covers part of the bottom of the trench gate; in the first direction, the fifth doped region has no overlapping portion with the first doped region, and the fifth doped region is connected with the second epitaxial layer.

Optionally, in the semiconductor device, the source region is located in the well region, and the source region is smaller than an implantation depth of the well region;

the fourth doped region is connected with the well region and is connected with the source region through the well region.

the fourth doped region passes through the well region and is connected with the source region.

Optionally, in the semiconductor device, the fourth doped region is connected to the source region through one sidewall of the trench gate.

Optionally, in the semiconductor device, the fourth doped region is connected to the source region through opposite sidewalls of the trench gate.

Optionally, in the semiconductor device, a plurality of trench gates sequentially arranged in the second direction are provided in a surface of the third epitaxial layer, and the trench gates extend along the third direction; the second direction and the third direction are orthogonal and are parallel to the plane of the semiconductor substrate;

in the first direction, at least one of a third doped region, a fourth doped region and a fifth doped region is arranged in a third epitaxial layer opposite below the trench gate.

Optionally, in the semiconductor device, a plurality of connection doped regions are disposed in the third epitaxial layer opposite to each trench gate, and the connection doped regions are fourth doped regions or fifth doped regions.

Optionally, in the semiconductor device, the connection doped regions disposed in the third epitaxial layer opposite to the same trench gate are both fourth doped regions or both fifth doped regions.

Optionally, in the semiconductor device, if a third doped region and a connection doped region are disposed in a third epitaxial layer opposite to the trench gate, the third doped region and the connection doped region are integrally connected at the bottom of the trench gate.

In the above semiconductor device, alternatively, for any adjacent two trench gates in the second direction,

A plurality of third doped regions and connecting doped regions which are alternately arranged along a third direction are arranged in a third epitaxial layer opposite to the lower part of the trench gate, and the third doped regions opposite to the lower part of the trench gate and the connecting doped regions are integrally connected;

a plurality of connecting doped regions are arranged in the third epitaxial layer opposite to the lower part of the other trench gate at intervals.

Optionally, in the semiconductor device, in the third direction, doped regions in a third epitaxial layer opposite to the same trench gate are periodically arranged.

The second aspect of the present application provides a method for manufacturing the semiconductor device, including:

Providing a semiconductor substrate, wherein an epitaxial lamination layer is formed on one side surface of the semiconductor substrate; the epitaxial lamination comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are sequentially laminated on the surface of the semiconductor substrate; the doping types of the first epitaxial layer and the third epitaxial layer are the same as those of the semiconductor substrate, and the doping types of the second epitaxial layer and the semiconductor substrate are different;

Performing ion implantation on the epitaxial lamination to form a plurality of first doped regions in the second epitaxial layer; the doping types of the first doping region and the second epitaxial layer are different;

forming a well region, a source region, a plurality of second doped regions and a trench gate in the surface of one side of the third epitaxial layer, which is away from the semiconductor substrate;

Wherein, in the first direction, each first doped region has an overlapping portion with the trench gate; the first direction is perpendicular to the plane of the semiconductor substrate; the second doped region extends downwards from the source region to the second epitaxial layer, and the doping type of the second doped region is the same as that of the second epitaxial layer.

Optionally, in the above manufacturing method, forming a well region, a source region, a plurality of second doped regions, and a trench gate in a surface of the third epitaxial layer facing away from the semiconductor substrate includes:

forming a well region in the third epitaxial layer, and forming a source region in the well region;

Forming a second doped region in the third epitaxial layer connecting the second epitaxial layer and the source region;

a trench gate is formed within the third epitaxial layer.

Optionally, in the above manufacturing method, before forming the trench gate, the method further includes:

forming a third doped region in the region of the third epitaxial layer corresponding to the trench gate;

forming at least one of a fourth doped region and a fifth doped region within the third epitaxial layer; wherein,

By means of the technical scheme, in the semiconductor device and the manufacturing method thereof, the epitaxial layer is provided with the first epitaxial layer, the second epitaxial layer and the third epitaxial layer which are sequentially stacked on the surface of the semiconductor substrate, and a well region, a source region and a trench gate are formed in the surface of one side, which is away from the semiconductor substrate, of the third epitaxial layer. A plurality of first doped regions with different doping types from the second epitaxial layer are formed in the second epitaxial layer, and a second doped region extending downwards from the source region to the second epitaxial layer is arranged in the third epitaxial layer, wherein the doping type of the second doped region is the same as that of the second epitaxial layer, so that the source region and the second doped layer are connected through the second doped region. Because the doping types of the first doping region and the first epitaxial layer are the same as those of the third epitaxial layer, and the doping types of the first doping region and the third epitaxial layer are different from those of the second epitaxial layer, a grid-shaped current path can be formed on the basis of the second epitaxial layer with a plurality of first doping regions, the grid-shaped current path can be connected to the source region through the second doping region so as to be grounded through a source electrode connected with the source region, dynamic floating is avoided, the grid-shaped current path can realize better electric field shielding on the bottom of the trench gate and the trench angle position, the gate dielectric layer is prevented from being broken down, and the modulation performance of the current distribution of the semiconductor device can be improved by controlling the distribution of the first doping region in the second epitaxial layer.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings required for the description of the embodiments or the prior art will be briefly described below, and it is apparent that the drawings in the following description are only embodiments of the present application, and other drawings may be obtained according to the provided drawings without inventive effort to those skilled in the art.

The structures, proportions, sizes, etc. shown in the drawings are shown only in connection with the present disclosure, and therefore should not be construed as limiting the application, but rather as limiting the scope of the application, so that any structural modifications, proportional changes, or dimensional adjustments should fall within the scope of the application without affecting the efficacy or achievement thereof.

Fig. 1 is a schematic diagram of layout design of a doped region in an epitaxial layer in a semiconductor device according to an embodiment of the present application;

FIG. 2 is a cross-sectional view of the semiconductor device at the location of the A-A' cut in FIG. 1;

FIG. 3 is a cross-sectional view of the semiconductor device at the location of the B-B' cut in FIG. 1;

FIG. 4 is a schematic view of a current path of the semiconductor device at the cross-sectional location shown in FIG. 2;

FIG. 5 is a schematic view of a current path of the semiconductor device at the cross-sectional location shown in FIG. 3;

fig. 6 is a cross-sectional view of a semiconductor device according to an embodiment of the present application;

FIG. 7 is a schematic view of a current path of the semiconductor device at the location of the cross-sectional view shown in FIG. 6;

fig. 8 is a cross-sectional view of another semiconductor device according to an embodiment of the present application;

FIG. 9 is a schematic view of a current path of the semiconductor device at the location of the cross-sectional view shown in FIG. 8;

Fig. 10 is a cross-sectional view of yet another semiconductor device provided in an embodiment of the present application;

FIG. 11 is a schematic view of a current path of the semiconductor device at the location of the cross-sectional view shown in FIG. 10;

fig. 12-18 are block diagrams of a semiconductor device manufacturing method according to an embodiment of the present application at different process stages.

Reference numerals:

10-a semiconductor substrate; 11-an epitaxial stack; 111-a first epitaxial layer; 112-a second epitaxial layer; 113-a third epitaxial layer; 12 well regions; 13-source region; 131-a first sub-source region; 132-a second sub-source region; 14-trench gate; 141-a gate dielectric layer; 142-gate fill material; 15-source electrode; 16-an insulating layer; 17-drain; 21-a first doped region; 22-a second doped region; 23-a third doped region; 24-fourth doped region; 25-a fifth doped region; 251-a first sub-doping region; 252-second sub-doped region.

Detailed Description

Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown. As one of ordinary skill in the art can know, with the development of technology and the appearance of new scenes, the technical scheme provided by the embodiment of the application is also applicable to similar technical problems.

It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application. The terminology used in the embodiments of the application is for the purpose of describing particular embodiments of the application only and is not intended to be limiting of the application.

The wide band gap or ultra-wide band gap semiconductor material has excellent optical and electrical properties, and the semiconductor device adopting the wide band gap or ultra-wide band gap semiconductor material has larger band gap, so that the semiconductor device can be applied to a plurality of extremely severe environments. Higher drilling speeds and lower failure rates can be achieved, as in the context of geothermal energy production and oil and gas production; such as at high temperatures, to allow for higher operating temperatures in electronic sensor controlled aluminum, steel, and coal and gas fired power plants, thereby improving the energy efficiency of these industrial processes.

Taking trench MOSFET devices as an example, semiconductor devices of wide band gap or ultra wide band gap semiconductor materials still have some problems to be ameliorated: the protection capability of the trench gate is insufficient, the electric field at the trench corner of the trench gate is easy to gather, and the gate dielectric layer is easy to be broken down rapidly under high drain voltage.

Although the above-described problem can be solved by forming an electric field masking structure grounded inside the semiconductor device to reduce the electric field of the trench gate at the trench corner position. But in order to ensure dynamic reliability of the semiconductor device, it is necessary to construct an electric field masking structure in the cell structure of each device unit. The electric field masking structure generally needs to pass through ultra-high energy ion implantation equipment, high-temperature and high-energy ion implantation causes productivity bottleneck of mass production, and meanwhile, high-energy ion implantation damage is easily formed in an active working area of a device core, so that a semiconductor device is easy to have long-term reliability.

In addition, the electric field shielding structure needs to sacrifice the area of the semiconductor device so that the electric field shielding structure keeps the grounding state, so that the solution not only leads to the complex manufacturing process and high manufacturing cost of the semiconductor device, but also can sacrifice a larger area, so that the effective area of a cell in the semiconductor device is lower, and further the conduction characteristic of the semiconductor device is poor.

In view of this, an embodiment of the present application provides a semiconductor device, including:

a semiconductor substrate;

A plurality of first doped regions disposed within the second epitaxial layer, the first doped regions having a different doping type than the second epitaxial layer; in the first direction, the first doped region and the trench gate have overlapping portions; the first direction is perpendicular to the plane of the semiconductor substrate;

In the semiconductor device provided by the embodiment of the application, the doping types of the first doping region and the first epitaxial layer are the same as those of the third epitaxial layer, and the doping types of the first doping region and the third epitaxial layer are different from those of the second epitaxial layer, so that a grid-shaped current path can be formed on the basis of the second epitaxial layer with a plurality of first doping regions, the grid-shaped current path can be connected to the source region through the second doping region, the source electrode connected with the source region is grounded, dynamic floating is avoided, the grid-shaped current path can realize better electric field shielding on the bottom and the groove angle position of the trench gate electrode, the gate dielectric layer is prevented from being broken down, and the modulation performance of the current distribution of the semiconductor device can be improved by controlling the distribution of the first doping region in the second epitaxial layer.

In addition, the semiconductor device provided by the embodiment of the application can form each doped region in the third epitaxial layer first, then form the trench gate, which is equivalent to the conventional scheme of preparing the trench of the trench gate first, then forming the doped region below the bottom of the trench gate based on ion implantation of the trench in the third epitaxial layer, and ion implantation is not required to be performed in the limited region at the bottom of the trench gate, so that the line width size of the trench gate can be further reduced, the cell size in the semiconductor device can be reduced to improve the cell density and the conduction performance, and the influence of the conventional electric field masking structure on the effective area in the semiconductor device can be solved.

Further, as shown below, the electric field intensity born by the gate dielectric layer can be further reduced by forming a doped region with the opposite doping type to the doped region of the third epitaxial layer in the third epitaxial layer corresponding to the trench gate. By forming a periodic doping region in the third epitaxial layer corresponding to the trench gate, the electric field intensity born by the gate dielectric layer is adjusted, a connection structure for connecting the second epitaxial layer is not required to be arranged below the trench gate of each cell structure in the semiconductor device, and the manufacturing process of the semiconductor device is simple and the manufacturing cost is low.

The foregoing aspects are provided as an overview of the present application, and are further described in detail below with reference to the accompanying drawings and detailed description of the application so that the above objects, features and advantages of the present application may be more readily understood.

Referring to fig. 1 to 3, fig. 1 is a schematic diagram of layout design of a doped region in an epitaxial layer in a semiconductor device according to an embodiment of the present application, fig. 2 is a cross-sectional view of the semiconductor device at A-A 'tangential position in fig. 1, and fig. 3 is a cross-sectional view of the semiconductor device at B-B' tangential position in fig. 1, where the semiconductor device includes:

a semiconductor substrate 10;

An epitaxial stack 11, the epitaxial stack 11 including a first epitaxial layer 111, a second epitaxial layer 112, and a third epitaxial layer 113 sequentially stacked on a surface of the semiconductor substrate 10; the doping type of the first epitaxial layer 111 is the same as that of the third epitaxial layer 113 and the semiconductor substrate 10, and the doping type of the second epitaxial layer 112 is different from that of the semiconductor substrate 10;

a well region 12, a source region 13 and a trench gate 14 are arranged in the surface of the third epitaxial layer 113 facing away from the semiconductor substrate 10;

A plurality of first doped regions 21 disposed within the second epitaxial layer 112, the first doped regions 21 being of a different doping type than the second epitaxial layer 112; in the first direction (vertical direction in fig. 2), each of the first doped regions 21 has an overlapping portion with the trench gate 14; the first direction is perpendicular to the plane of the semiconductor substrate 10;

A plurality of second doped regions 22, the second doped regions 22 extending from the source region 13 down to the second epitaxial layer 112, the second doped regions 22 being of the same doping type as the second epitaxial layer 112.

In the semiconductor device, since the doping types of the first doped region 21 and the first epitaxial layer 111 and the third epitaxial layer 113 are the same, and the doping type of the second epitaxial layer 112 is different, the grid-shaped current path can be formed based on the second epitaxial layer 112 with a plurality of first doped regions 21, and can be connected to the source region 13 through the second doped region 22 so as to be grounded through the source electrode 15 connected with the source region 13, dynamic floating is avoided, the grid-shaped current path can realize better electric field shielding on the bottom of the trench gate 14 and the trench angle position, the gate dielectric layer 141 is prevented from being broken down, and the modulation performance of the current distribution of the semiconductor device can be improved by controlling the distribution of the first doped region 21 in the second epitaxial layer 112.

The trench gate 14 includes: a trench in the surface of the third epitaxial layer 113, the sidewalls and bottom of the trench being covered with a gate dielectric layer 141; gate fill material 142, gate fill material 142 fills the trench with gate dielectric layer 141 covered on the surface.

Wherein a surface of the epitaxial stack 11 facing away from the semiconductor substrate 10 is covered with a source electrode 15. The source electrode 15 is insulated from the trench gate electrode 14 by an insulating layer 16. The insulating layer 16 and the gate dielectric layer 141 may be made of the same material or different materials, and if they are made of the same material, they may be made of a silicon oxide film.

The doping type of the respective regions in the semiconductor device may be P-type doping and N-type doping. If the doping types of the two objects are the same, the two objects are P-type doping or N-type doping. If the doping types of the two objects are different, one is P-type doping, and the other is P-type doping.

The side surface of the semiconductor substrate 10 facing away from the epitaxial stack 11 is covered with a drain 17, and the trench gate 14, together with the source 15 and the drain 17, can form a MOSFET structure. The MOSFET may be NMOS or PMOS, which is not limited in this embodiment of the present application. In the embodiment of the application, the doping types of different regions in the semiconductor device can be set based on requirements so as to obtain the semiconductor device with the PMOS structure or the semiconductor device with the NMOS structure.

Optionally, in the semiconductor device provided in the embodiment of the present application, a third doped region 23 is further disposed in the third epitaxial layer 113; wherein the doping type of the third doped region 23 is the same as that of the second doped region 22; the third doped region 23 covers a portion of the bottom of the trench gate 14; the first doped region 21 is provided in a region of the second epitaxial layer 112 opposite to the third doped region 23.

The third doped region 23 can enhance the withstand voltage capability of the bottom of the trench gate 14. And based on the third doped region 23 and the first doped region 21 oppositely arranged below the third doped region 23, a current path in the vertical direction can be formed, and in combination with the grid-shaped current path formed by the second epitaxial layer 112 with the first doped region 21, semiconductor devices which are flexibly distributed in a three-dimensional space and have different interface structures can be formed, so that modulation of the electric field masking effect at the bottom of the trench gate 14 is realized in the three-dimensional space, and modulation of current distribution is realized. In addition, the temperature distribution in the semiconductor device can also be modulated based on the arrangement of the distribution areas of the first doped region 21, the second doped region 22, and the third doped region 23.

Optionally, as shown in fig. 2, a fourth doped region 24 is further disposed in the third epitaxial layer 113; the doping type of the fourth doping region 24 is the same as that of the second doping region 22; the fourth doped region 24 covers part of the bottom of the trench gate 14 and also covers part of the sidewall of the trench gate 14 to connect with the source region 13 along the sidewall of the trench gate 14; the first doped region 21 is provided in a region of the second epitaxial layer 112 opposite to the fourth doped region 24.

The inside of the semiconductor device can be connected with the source region 13 through the fourth doped region 24, and then the fourth doped region 24 can be grounded through the source electrode 15, so that the electric field intensity of the gate dielectric layer 141 is further reduced, and the reliability of the gate dielectric layer 141 in the semiconductor device is better improved.

Alternatively, the fourth doped region 24 may be prepared simultaneously with the third doped region 23, both of which are formed based on the same ion implantation process.

Source region 13 is located within well region 12. The well region 12 is doped differently from the third epitaxial layer 113. As shown in fig. 2, the source region 13 includes a plurality of first sub-source regions 131 and second sub-source regions 132 alternately distributed in the second direction (horizontal direction of fig. 1 to 9). The doping types of the first sub-source region 131 and the second sub-source region 132 are different. The doping type of the first sub-source region 131 is the same as the doping type of the well region 12 and is different from the doping type of the second sub-source region 132.

Referring to fig. 4 and 5, fig. 4 is a schematic view of a current path of the semiconductor device at the cross-sectional position shown in fig. 2, and fig. 5 is a schematic view of a current path of the semiconductor device at the cross-sectional position shown in fig. 3. Wherein the current transmission path is illustrated with dashed arrows in fig. 4 and 5. Fig. 4 shows a current path of the cross-sectional view shown in fig. 2 when the semiconductor device is turned on, and fig. 5 shows a current path of the cross-sectional view shown in fig. 3 when the semiconductor device is turned on. For the sake of clarity in illustrating the current transmission path, reference numerals in the semiconductor device are not shown in fig. 4 and 5, and reference numerals in the cross-sectional view shown in fig. 4 may correspond to those in fig. 2, and reference numerals in the cross-sectional view shown in fig. 5 may correspond to those in fig. 3.

As shown in fig. 2 and 4, in the semiconductor device in the cell region shown in the cross-section A-A', the middle-region current can flow to both sides of the cell region shown in the cross-section through the channel formed by the well region 12.

As shown in fig. 3 and 5, the semiconductor device may still conduct current between the source and the drain in the B-B ' cross-sectional view, and the current flows through the channel formed by the well region 12 to the inside of the cell region shown in the cross-sectional view, and then enters the cell region shown in the A-A ' cross-sectional view to merge with the current in the cell region shown in the A-A ' cross-sectional view.

Therefore, the semiconductor device can conduct current in the B-B' section view, and the conduction characteristic of the device is greatly improved. Meanwhile, by controlling the area ratio of the cell region shown in the A-A 'cross-sectional view and the cell region shown in the B-B' cross-sectional view in the length direction of the trench gate 14, the trade-off relationship between the specific on-resistance and the reliability of the gate dielectric layer 141 of the semiconductor device can be further improved.

As can be seen from fig. 2 to fig. 4, in the semiconductor device provided by the embodiment of the present application, based on the flexible design of the first doped region 21 to the fourth doped region 24 on the layout, a semiconductor device with a current distribution flexibly distributed in a three-dimensional space and a plurality of different cross-sectional structures can be formed, so that the modulation of the electric field shielding at the bottom of the trench gate 14, the modulation of the current distribution and the modulation of the internal temperature distribution can be realized in the three-dimensional space of the semiconductor device design.

Referring to fig. 6 and 7, fig. 6 is a cross-sectional view of a semiconductor device according to an embodiment of the present application, and fig. 7 is a schematic view of a current path of the semiconductor device at a position of the cross-sectional view shown in fig. 6. Fig. 6 may be a cut-away view of the semiconductor device at the position of the cut-away view A-A' shown in fig. 1. Fig. 7 illustrates the current transmission path with dashed arrows. Fig. 7 shows the current path of the cross-sectional view shown in fig. 6 when the semiconductor device is on. For the sake of clarity in illustrating the current transmission path, reference numerals in the semiconductor device are not shown in fig. 7, and reference numerals in the cross-sectional view shown in fig. 7 may correspond to reference numerals in fig. 6.

In any of the embodiments described above, in the embodiment shown in fig. 6 and 7, the fifth doped region 25 is further provided in the third epitaxial layer 113. The fifth doped region 25 has the same doping type as the second doped region 22; the fifth doped region 25 covers a portion of the bottom of the trench gate 14; in the first direction, the fifth doped region 25 has no overlapping portion with the first doped region 21, and the fifth doped region 25 is connected with the second epitaxial layer 112.

In the embodiment shown in fig. 6, the semiconductor device can be connected to the second epitaxial layer 112 through the fifth doped region 25, and further, the second doped region 22 connected to the second epitaxial layer 112 is connected to the source region 13, and the source electrode 15 is grounded, so that the grounding of the fifth doped region 25 can be realized, and the electric field intensity of the gate dielectric layer 141 can be further reduced, so that the reliability of the gate dielectric layer 141 in the semiconductor device can be better improved.

In the manner shown in fig. 2 and 3, the fourth doped region 24 occupies part of the channel by being connected up to ground through the connection source region 13. As shown in fig. 4 and 5, for any two adjacent trench gates 14, only the channels on both sides of one trench gate 14 can conduct the transmission current, and the channels on both sides of the other trench gate 14 are not conducted.

In the manner shown in fig. 6, after the fifth doped region 25 is connected to the second epitaxial layer 112 downward, grounding is achieved by connecting the second doped region 22 to the source region 13, so that the channel region is not occupied, and the conduction capability of the trench gate 14 of a partial region in the semiconductor device is not sacrificed. Therefore, as shown in fig. 7, the channels on both sides of the trench gate 14 can be enabled to conduct the transmission current, and the conduction capability of the semiconductor device can be further improved.

Optionally, the fifth doped region 25 includes a first sub-doped region 251 and a second sub-doped region 252. The first sub-doped region 251 may be prepared simultaneously with the third doped region 23, both of which are formed based on the same ion implantation process. The second sub-doped region 252 connects the first sub-doped region 251 and the underlying second epitaxial layer 112. The second sub-doped region 252 may be prepared simultaneously with the second doped region 22, both of which are formed based on the same ion implantation process.

In the semiconductor device provided in the embodiment of the present application, the third epitaxial layer 113 may include one of the fourth doped region 24 and the fifth doped region 25, and may also include both the fourth doped region 24 and the fifth doped region 25.

In any of the embodiments of the present application, source region 13 is located within well region 12, and source region 13 is less than the implantation depth of well region 12.

In one implementation of the embodiment of the present application, as shown in any of fig. 2 to 5, the fourth doped region 24 may be connected to the well region 12 and connected to the source region 13 through the well region 12.

In other embodiments, a fourth doped region 24 may also be provided in connection with source region 13 through well region 12. At this time, the fourth doped region 24 passes through the well region 12 and is directly connected with the source region 13, so that the resistance of the connection path between the fourth doped region 24 and the source region 13 is smaller, and the performance of the semiconductor device is further improved.

If the fourth doped region 24 is provided in the semiconductor device, the fourth doped region 24 may be connected to the source region through opposite sidewalls of the trench gate as shown in any of fig. 2-5. At this time, for the trench gate 14 having the fourth doped region 24 provided at the bottom, the channels on both sides of the trench gate 14 may be turned off at the same time as shown in fig. 4, or the channels on both sides of the trench gate 14 may be turned on at the same time as shown in fig. 5.

If the semiconductor device is provided with the fourth doped region 24, the structure of the fourth doped region 24 may also be as shown in fig. 8 and 9.

Referring to fig. 8 and 9, fig. 8 is a cross-sectional view of another semiconductor device according to an embodiment of the present application, and fig. 9 is a schematic view of a current path of the semiconductor device at the position of the cross-sectional view shown in fig. 8. Fig. 8 may be a cut-away view of the semiconductor device at the A-A' cut-away position shown in fig. 1. Fig. 9 illustrates a current transmission path with a dotted arrow. Fig. 9 shows the current path of the cross-sectional view shown in fig. 8 when the semiconductor device is on. For the sake of clarity in illustrating the current transmission path, reference numerals in the semiconductor device are not shown in fig. 9, and reference numerals in the cross-sectional view shown in fig. 9 may correspond to reference numerals in fig. 8.

In the embodiment shown in fig. 8 and 9, the fourth doped region 24 is connected to the source region 13 through one sidewall of the trench gate 14 on the basis of any of the above embodiments. Therefore, for the trench gate provided with the fourth doped region 24, the channel adjacent to the side wall of the trench gate 14 not covered by the fourth doped region 24 can be turned on, and the channel adjacent to the side wall of the other side covered by the fourth doped region 24 can be turned off, so that the channel on one side of the trench gate 14 can be turned on to improve the conduction capability, and the channel on the other side can be turned off, thereby achieving the purpose of grounding the fourth doped region 24, and more flexibly achieving the modulation of the current distribution in the semiconductor device and the grounding control of the fourth doped region 24.

As shown in any one of fig. 1 to 9, in the semiconductor device provided in the embodiment of the present application, the surface of the third epitaxial layer 113 has a plurality of trench gates 14 sequentially arranged in the second direction, and the trench gates 14 extend along the third direction (vertical direction in fig. 1); the second direction and the third direction are orthogonal and are both parallel to the plane of the semiconductor substrate 10. In the first direction, at least one of the third doped region 23, the fourth doped region 24 and the fifth doped region 25 is disposed in the third epitaxial layer 113 opposite under the trench gate 14, so as to protect the bottom of the trench gate 14 and reduce the electric field intensity born by the gate dielectric layer 141.

If at least one of the fourth doped region 24 and the fifth doped region 25 is disposed below the trench gate 14, the fourth doped region 24 or the fifth doped region 25 can be used as a connection doped region, and the connection doped region is grounded, so as to avoid the dynamic floating problem and ensure the dynamic reliability of the semiconductor device.

Optionally, in the semiconductor device, a plurality of connection doped regions are disposed in the third epitaxial layer 113 opposite to each trench gate 14, and the connection doped regions are the fourth doped region 24 or the fifth doped region 25. Thus, each trench gate 14 has a region grounded by connecting the doped regions to avoid dynamic floating problems.

In the embodiment of the present application, as shown in fig. 1, the connection doped regions disposed in the third epitaxial layer 113 opposite to the same trench gate 14 are all fourth doped regions 24; or the connection doped regions arranged in the third epitaxial layer 113 opposite to the same trench gate 14 are all fifth doped regions 25; alternatively, a part of the connection doped region disposed in the third epitaxial layer 113 opposite to the same trench gate 14 may be the fourth doped region 24, and the other part of the connection doped region may be the fifth doped region 25. The layout of the connection doped regions corresponding to different trench gates 14 may be the same or different.

The current distribution in the semiconductor device and the grounding layout of the connection doped regions can be flexibly adjusted by designing the layout mode of the connection doped regions corresponding to the trench gates 14, so that the performance of the semiconductor can be better optimized and improved.

As shown in fig. 1, if the third doped region 23 and the connection doped region are disposed in the third epitaxial layer 113 opposite to the trench gate 14, at the bottom of the trench gate 14, the third doped region 23 and the connection doped region are integrally connected.

If the connection doped region is the fourth doped region 24, based on the layout design, the third doped region 23 and the fourth doped region 24 can be formed synchronously by the same ion implantation, and the third doped region 23 and the fourth doped region 24 below the same trench gate 14 are integrated into the same doped region.

If the connection doped region is the fifth doped region 25, based on the layout design, the first sub-doped regions 251 of each third doped region 23 and the fifth doped region 25 can be formed simultaneously by the same ion implantation, and the second sub-doped regions 252 of each second doped region 22 and the fifth doped region 25 can be formed simultaneously by another ion implantation.

In the embodiment of the present application, as shown in fig. 1, for any two trench gates 14 adjacent in the second direction, there are provided: a plurality of third doped regions 23 and connection doped regions alternately arranged along a third direction are arranged in the third epitaxial layer 113 opposite to the lower part of the trench gate 14, and the third doped regions 23 opposite to the lower part of the trench gate 14 are integrally connected with the connection doped regions; a plurality of spaced apart connection doped regions are provided in the third epitaxial layer 113 opposite under the other trench gate 14. In the manner shown in fig. 1, the fourth doped region 24 is taken as an example of the connection doped regions disposed under the trench gate 14, and as described above, the fifth doped region 25 may also be disposed as the connection doped regions disposed under the trench gate 14, or a part of the connection doped regions may be the fourth doped region 24, and another part of the connection doped regions may be the fifth doped region 25.

Referring to fig. 10 and 11, fig. 10 is a cross-sectional view of a semiconductor device according to another embodiment of the present application, and fig. 11 is a schematic view of a current path of the semiconductor device at the position of the cross-sectional view shown in fig. 10. Fig. 10 may be a cut-away view of the semiconductor device at the C-C' cut-away position shown in fig. 1. Fig. 11 illustrates a current transmission path with a dotted arrow. Fig. 11 shows a current path in the cross-sectional view shown in fig. 10 when the semiconductor device is on. For the sake of clarity in illustrating the current transmission path, reference numerals in the semiconductor device are not shown in fig. 11, and reference numerals in the cross-sectional view shown in fig. 11 may correspond to reference numerals in fig. 10. Among these, the A-A ' cut position, the B-B ' cut position, and the C-C ' cut position are three different cut positions of the semiconductor device along the length direction of the trench gate 14.

Based on any of the above embodiments, in the embodiments shown in fig. 10 and 11, at the C-C' section position, the semiconductor device can not only make the channels adjacent to the two trench gates 14 on the left and right sides conductive, but also make the channels adjacent to the middle trench gate 14 conductive, so that the current is transferred to the middle region, and the conductive capability is improved.

In the embodiment of the present application, the same trench gate has a plurality of different cell regions along the length direction (third direction) of the trench gate 14. For example, the A-A ' tangential position, the B-B ' tangential position and the C-C ' tangential position correspond to different cellular regions, respectively. The semiconductor device has different doping regions in the third epitaxial layer 113 corresponding to the lower part of the trench gate 14 in different cell regions, so that different device structures are provided in the third direction, and the electric field modulation performance, the internal current distribution modulation performance and the temperature distribution modulation performance at the bottom of the trench gate 14 are better optimally designed.

Optionally, in the third direction, the doped regions (at least one of the third doped region 23 to the fifth doped region 25) in the third epitaxial layer 113 opposite to the same trench gate 14 are arranged periodically, so that the semiconductor device can have multiple periodic structures, and the doped regions in the corresponding third epitaxial layer 113 under the trench gate 14 in different periodic structures are different, so that the doped regions are formed in the third epitaxial layer 113.

The trench gate 14 may have a first cell region, a second cell region, and a third cell region arranged in this order in the same periodic structure in the length direction. The semiconductor device has different doping regions in the third epitaxial layer 113 under the trench gate 14 in different cell regions, so that different device structures are provided in the third direction.

The first unit cell region may correspond to the cross-sectional view shown in fig. 2, and for three trench gates 14 that are arranged in succession, a third doped region 23 is disposed in the third epitaxial layer 113 corresponding to the lower portion of two trench gates 14 on the left and right sides, and a fourth doped region 24 or a fifth doped region 25 is disposed in the third epitaxial layer 113 corresponding to the lower portion of the middle trench gate 14.

In the second cell region, which may correspond to the cross-sectional view shown in fig. 3, for three trench gates 14 that are arranged in succession, a fourth doped region 24 or a fifth doped region 25 is disposed in the third epitaxial layer 113 corresponding to the lower portion of two trench gates 14 on the left and right sides, and no doped region is disposed in the third epitaxial layer 113 corresponding to the lower portion of the middle trench gate 14.

In the third cell region, which may correspond to the cross-sectional view shown in fig. 11, for three trench gates 14 that are arranged in succession, a third doped region 23 is disposed in the third epitaxial layer 113 corresponding to the lower portion of two trench gates 14 on the left and right sides, and no doped region is disposed in the third epitaxial layer 113 corresponding to the lower portion of the middle trench gate 14.

The doping types of the semiconductor substrate 10, the first epitaxial layer 111, the first doping region 21, the third epitaxial layer 113 and the second sub-source region 132 are the same as each other and are all of the first type. The second epitaxial layer 112, the second doped regions 22 to the fifth doped regions 25, the well region 12 and the first sub-source region 131 are all doped of the second type. One of the first type doping and the second type doping is an N-type doping, and the other is a P-type doping.

The doping concentration of the third epitaxial layer 113 may be set to be greater than that of the first epitaxial layer 111, so that the semiconductor device has better current diffusion and conduction capability in the conduction region, and the doping concentrations of the third epitaxial layer and the first epitaxial layer may be set based on requirements. The second sub-source region 132 is greater than the doping concentration of the semiconductor substrate. The doping concentration of the first doped region 21 may be set based on the requirement. If the first doping type is N-type doping, the doping concentration of the semiconductor substrate 10 may be set to n+ and the doping concentration of the second sub-source region 132 may be set to n++ with n++ being greater than n+.

The doping concentrations of the second doped region 22 to the fifth doped region 25 may be set to be the same, greater than the doping concentration of the second epitaxial layer 112, and less than the doping concentration phase of the first sub-source region 131. The doping concentration of well region 12 may be set based on requirements. If the second doping type is P-type doping, the doping concentration of the second epitaxial layer 112 may be set to P-, the doping concentrations of the second doping region 22 to the fifth doping region 25 are p+, the doping concentration of the first sub-source region 131 is p++, p+ is greater than P-, and p++ is greater than p+.

In the embodiment of the application, the doping concentration of each region can be set based on requirements, and the embodiment of the application does not limit the value of the doping concentration of each device.

As can be seen from the above description, in the semiconductor device provided by the embodiment of the present application, the second epitaxial layer 112 formed with the first doped region 21 not only can form a grid-shaped current path, but also can be used as a grid-shaped electric field shielding structure, and the dynamic floating problem can be avoided after the source region 13 is grounded. The grid-like electric field shielding structure can also provide a very good electric field shielding effect on the bottom and the groove corners of the trench gate 14. At least one of the third doped region 23 to the fifth doped region 25 can be selectively formed below the trench gate 14 as another electric field masking structure, so as to further enhance the bottom masking effect of the trench gate 14, further reduce the electric field intensity born by the gate dielectric layer 141, and better enhance the reliability of the gate dielectric layer 141. Wherein, all the first doped regions 21 in the second epitaxial layer 112 maintain the grounded state in three-dimensional space, so that the dynamic reliability of the semiconductor device can be improved.

In the embodiment of the present application, at least one of the third doped region 23 to the fifth doped region 25 can be selectively formed below the trench gate 14 as an electric field masking structure, and a novel trench MOSFET device structure with high reliability and wide forbidden band can be formed by combining the trench gate 14, the first sub-source region 131 and the second sub-source region 132 of the source region 13, the well region 12, the source 15 and the drain 17.

Based on the semiconductor device provided in the foregoing embodiment, another embodiment of the present application further provides a manufacturing method for manufacturing the semiconductor device provided in any one of the foregoing embodiments.

Referring to fig. 12 to fig. 18, fig. 12 to fig. 18 are product structure diagrams of a semiconductor device manufacturing method at different process stages according to an embodiment of the present application, and cross-sectional views shown in the manufacturing method are illustrated by taking the structure of the A-A' cross-sectional position as an example, and product structures of other cross-sectional positions may be described with reference to the foregoing embodiments, which are not repeated in the manufacturing method embodiment. The manufacturing method comprises the following steps:

step S11: as shown in fig. 12, a semiconductor substrate 10 is provided.

Wherein an epitaxial stack 11 is formed on one surface of the semiconductor substrate 10; the epitaxial stack 11 includes a first epitaxial layer 111, a second epitaxial layer 112, and a third epitaxial layer 113 sequentially stacked on the surface of the semiconductor substrate 10; the first epitaxial layer 111 has the same doping type as the third epitaxial layer 113 and the semiconductor substrate 10, and the second epitaxial layer 112 has a different doping type than the semiconductor substrate 10.

The semiconductor substrate 10 may be a wide band gap or ultra-wide band gap semiconductor material such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga ₂O₃), diamond (C), and aluminum nitride (AlN).

Step S12: as shown in fig. 13 and 14, ion implantation is performed on the epitaxial stack to form a plurality of first doped regions 21 within the second epitaxial layer; the first doped region 21 is doped differently from the second epitaxial layer 112, thereby forming a grid-like current path and a grid-like electric field masking structure. Fig. 13 is a schematic layout diagram of an implantation window when the first doped region 21 is formed by ion implantation, and fig. 14 is a cross-sectional view after the first doped region 21 is formed.

Alternatively, the semiconductor device may be fabricated using an epitaxial wafer of NPN structure with a P-type epitaxial layer interlayer of tens of nanometers to hundreds of nanometers. The epitaxial wafer comprises an n+ doped semiconductor substrate 10, the first epitaxial layer 111 and the third epitaxial layer 113 on the surface of which are N-doped, and the second epitaxial layer 112 in the middle is P-doped.

With the second epitaxial layer 112 doped with P-type as the epitaxial buried layer, the first doped region 21 may be formed by implanting N-type ions into the inside thereof to form a grid-like current path. The deep P-type masking structures are formed in a grid shape by the P-type epitaxial buried layer by a simple ion implantation method, are connected in a grid shape with each other, and can be connected to the source region 13 through the P-type second doping regions 22 of a very small area, which are periodically distributed, to be grounded through the source electrode 15, so that the dynamic floating problem can be avoided. And the grid-shaped deep P-type masking structure can also form a very good electric field shielding effect on the bottom and the groove angle of the trench gate 14.

Optionally, at least one of the third doped region 23 to the fifth doped region 25 may be formed under the trench gate 14 in a subsequent process, so as to further enhance the bottom masking effect of the trench gate 14, further reduce the electric field intensity born by the gate dielectric layer 141, and better enhance the reliability of the gate dielectric layer 141.

Step S13: a well region 12, a source region 13, a plurality of second doped regions 22, and a trench gate 14 are formed in a side surface of the third epitaxial layer 113 facing away from the semiconductor substrate 10.

Wherein, in the first direction, each first doped region 21 has an overlapping portion with the trench gate 14; the first direction is perpendicular to the plane of the semiconductor substrate 10; the second doped region 22 extends from the source region 13 down to the second epitaxial layer 112, the second doped region 22 being of the same doping type as the second epitaxial layer 112.

In the manufacturing method provided by the embodiment of the application, the doped region can be selectively formed in the third epitaxial layer 113 corresponding to the lower part of the trench gate 14 as the bottom masking structure of the trench gate 14, so that the electric field intensity of the gate dielectric layer 141 can be further reduced on the basis of the grid-shaped second epitaxial layer 112, and the reliability of the gate dielectric layer 141 can be better improved.

Optionally, before forming the trench gate 14, further includes: forming a third doped region 23 in a region of the third epitaxial layer 113 corresponding to the trench gate 14; wherein the doping type of the third doped region 23 is the same as that of the second doped region 22; the third doped region 23 covers a portion of the bottom of the trench gate 14; the first doped region 21 is provided in a region of the second epitaxial layer 112 opposite to the third doped region 23. An electric field masking structure can be formed at the bottom of trench gate 14 by third doped region 23.

Optionally, before forming the trench gate 14, further includes: forming at least one of a fourth doped region 24 and a fifth doped region 25 within the third epitaxial layer 113; wherein the doping type of the fourth doped region 24 is the same as that of the second doped region 22; the fourth doped region 24 covers part of the bottom of the trench gate 14 and also covers part of the sidewall of the trench gate 14 to connect with the source region 13 along the sidewall of the trench gate 14; the first doped region 21 is provided in a region of the second epitaxial layer 112 opposite to the fourth doped region 24. The fourth doped region 24 and the fifth doped region 25 can implement the electric field masking structure at the bottom of the trench gate 14 to be grounded to avoid the occurrence of dynamic floating problems.

The fifth doped region 25 has the same doping type as the second doped region 22; the fifth doped region 25 covers a portion of the bottom of the trench gate 14; in the first direction, the fifth doped region 25 has no overlapping portion with the first doped region 21, and the fifth doped region 25 is connected with the second epitaxial layer 112.

Ion implantation may be performed to form the third doped region 23 and the fourth doped region 24 in the third epitaxial layer 113 based on the layout design shown in fig. 1, and a semiconductor device having the structure shown in fig. 2, 3, and 10 may be formed. In the layout shown in fig. 1, ion implantation windows of the first doped region 21, the second doped region 22, the third doped region 23, and the fourth doped region 24 are shown, as well as trench etched regions of the trench gate 14.

In the above step S13, the well region 12, the source region 13, the plurality of second doped regions 22, and the trench gate 14 are formed in the surface of the third epitaxial layer 113 facing away from the semiconductor substrate 10, including:

Step S21: as shown in fig. 15, the well region 12 is formed in the third epitaxial layer 113, and the source region 13 is formed in the well region 12.

The well region 12 doped P-type may be formed by P-type ion implantation, the first sub-source region 131 may be formed by P-type ion implantation, and the second sub-source region 132 may be formed by N-type ion implantation. The doping concentration of the first sub-source region 131 is p++, the doping concentration of the second sub-source region 132 is n++, and the first sub-source region and the second sub-source region are ohmic contact regions, so that the contact resistance between the source region 13 and the source electrode 15 can be reduced.

Step S22: as shown in fig. 16, a second doped region 22 connecting the second epitaxial layer 112 and the source region 13 is formed in the third epitaxial layer 113.

In this process, if based on the layout shown in fig. 1, the third doped region 23 and the fourth doped region 24 may also be selectively formed in the third epitaxial layer 113. A plurality of p+ doped regions may be formed in the region of the third epitaxial layer 113 corresponding to the trench gate 14 by p+ ion implantation, for constituting the p+ doped third doped region 23 and the fourth doped region 24 after the formation of the trench gate 14.

Step S23: a trench gate 14 is formed within the third epitaxial layer 113.

Finally, the source electrode 15 and the drain electrode 17 are formed on the upper and lower surfaces, respectively, by a process to form a semiconductor device having the structure shown in fig. 2.

In the manufacturing method provided by the embodiment of the application, if the semiconductor device with the structure shown in fig. 8 is manufactured, only the implantation window structures of the third doped region 23 and the fourth doped region 24 in the layout need to be simply changed. At this time, the corresponding layout is shown in fig. 17.

Referring to fig. 17, fig. 17 is a schematic diagram of layout design of a doped region in an epitaxial layer in another semiconductor device according to an embodiment of the present application. In this layout, a fourth doped region 24 covering a single sidewall of trench gate 14 may be formed at the A-A 'and B-B' cross-sectional locations. Can pass through P +

In the manufacturing method provided by the embodiment of the application, if the semiconductor device with the structure shown in fig. 6 is manufactured, only the implantation window structures of the third doped region 23 and the second doped region 22 in the layout need to be simply changed. The fifth doped region 25 is formed using an implantation process of the third doped region 23 and the second doped region 22, which may be as shown in fig. 18.

Referring to fig. 18, fig. 18 is a schematic diagram of a fifth doped region forming method according to an embodiment of the present application, in which, while forming the second doped region 22, ion implantation is performed simultaneously with respect to a region where the fifth doped region 25 is required to be formed, for forming the first sub-doped region 251 after forming the trench gate 14, and in which, in addition, ion implantation is performed simultaneously with forming the third doped region 23, ion implantation is performed simultaneously with respect to a region where the fifth doped region 25 is required to be formed, for forming the second sub-doped region 252 after forming the trench gate 14. After forming the trench gate 14 based on the structure shown in fig. 18, a semiconductor device of the structure shown in fig. 6 can be formed.

In the embodiment of the present application, the grounding design of the doped region under the trench gate 14 can be realized by flexibly selecting the fifth doped region 25 or the fourth doped region 24 based on the requirement.

In the description of the present application, each embodiment is described in a progressive manner, or in parallel manner, or in a combination of progressive and parallel manners, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other. The embodiments provided by the embodiments of the application can be combined with each other without contradiction.

It is to be noted, however, that the description of the drawings and embodiments are illustrative and not restrictive. Like reference numerals refer to like structures throughout the embodiments of the specification. In addition, the drawings may exaggerate the thicknesses of some layers, films, panels, regions, etc. for understanding and ease of description. It will also be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In addition, "on …" refers to positioning an element on or under another element, but not essentially on the upper side of the other element according to the direction of gravity.

The terms "upper," "lower," "top," "bottom," "inner," "outer," and the like are used for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not denote or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the application. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or device comprising the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

A plurality of first doped regions disposed within the second epitaxial layer, the first doped regions being of a different doping type than the second epitaxial layer; in a first direction, each first doped region has an overlapping portion with the trench gate; the first direction is perpendicular to the plane of the semiconductor substrate;

a plurality of second doped regions extending from the source region down to the second epitaxial layer, the second doped regions being of the same doping type as the second epitaxial layer;

A third doped region is also arranged in the third epitaxial layer; wherein the doping type of the third doping region is the same as that of the second doping region; the third doped region covers part of the bottom of the trench gate; the first doped region is arranged in a region of the second epitaxial layer opposite to the third doped region;

at least one of a fourth doped region and a fifth doped region is also arranged in the third epitaxial layer; the doping type of the fourth doping region is the same as that of the second doping region; the fourth doped region covers part of the bottom of the trench gate and also covers part of the side wall of the trench gate so as to be connected with the source region along the side wall of the trench gate; the first doped region is arranged in a region of the second epitaxial layer opposite to the fourth doped region; the doping type of the fifth doping region is the same as that of the second doping region; the fifth doped region covers part of the bottom of the trench gate; in the first direction, the fifth doped region has no overlapping portion with the first doped region, and the fifth doped region is connected with the second epitaxial layer.

2. The semiconductor device of claim 1, wherein the source region is located within the well region and the source region is less than an implantation depth of the well region;

3. The semiconductor device of claim 1, wherein the source region is located within the well region and the source region is less than an implantation depth of the well region;

4. The semiconductor device of claim 1, wherein the fourth doped region is connected to the source region through one sidewall of the trench gate.

5. The semiconductor device of claim 1, wherein the fourth doped region is connected to the source region through opposite sidewalls of the trench gate.

6. The semiconductor device according to any one of claims 1 to 5, wherein a surface of the third epitaxial layer has a plurality of the trench gates arranged in sequence in the second direction therein, the trench gates extending in the third direction; the second direction and the third direction are orthogonal and are parallel to the plane of the semiconductor substrate;

At least one of the third doped region, the fourth doped region, and the fifth doped region is disposed within the third epitaxial layer opposite below the trench gate in the first direction.

7. The semiconductor device of claim 6, wherein a plurality of connection doped regions are disposed in the third epitaxial layer opposite each trench gate, the connection doped regions being the fourth doped region or the fifth doped region.

8. The semiconductor device according to claim 7, wherein the connection doped regions provided in the third epitaxial layer opposite to the trench gate are the fourth doped region or the fifth doped region.

9. The semiconductor device according to claim 7, wherein if the third doped region and the connection doped region are provided in the third epitaxial layer opposite to the trench gate, the third doped region and the connection doped region are integrally connected at the bottom of the trench gate.

10. The semiconductor device according to claim 7, wherein, for any adjacent two of the trench gates in the second direction,

A plurality of third doped regions and connecting doped regions which are alternately arranged along the third direction are arranged in the third epitaxial layer opposite to the lower part of the trench gate, and the third doped regions opposite to the lower part of the trench gate and the connecting doped regions are integrally connected;

and a plurality of connecting doped regions which are arranged at intervals are arranged in the third epitaxial layer opposite to the lower part of the other trench gate.

11. The semiconductor device of claim 6, wherein doped regions within the third epitaxial layer opposite the trench gate are periodically arranged in the third direction.

12. A method of manufacturing a semiconductor device according to any one of claims 1 to 11, comprising:

performing ion implantation on the epitaxial stack to form a plurality of first doped regions in the second epitaxial layer; the doping types of the first doping region and the second epitaxial layer are different;

wherein, in the first direction, each first doped region has an overlapping portion with the trench gate; the first direction is perpendicular to the plane of the semiconductor substrate; the second doped region extends downwards from the source region to the second epitaxial layer, and the doping type of the second doped region is the same as that of the second epitaxial layer;

Before forming the trench gate, the method further comprises: forming a third doped region in a region of the third epitaxial layer corresponding to the trench gate; wherein the doping type of the third doping region is the same as that of the second doping region; the third doped region covers part of the bottom of the trench gate; the first doped region is arranged in a region of the second epitaxial layer opposite to the third doped region;

Before forming the trench gate, the method further comprises: forming at least one of a fourth doped region and a fifth doped region within the third epitaxial layer; wherein the doping type of the fourth doping region is the same as that of the second doping region; the fourth doped region covers part of the bottom of the trench gate and also covers part of the side wall of the trench gate so as to be connected with the source region along the side wall of the trench gate; the first doped region is arranged in a region of the second epitaxial layer opposite to the fourth doped region; the doping type of the fifth doping region is the same as that of the second doping region; the fifth doped region covers part of the bottom of the trench gate; in the first direction, the fifth doped region has no overlapping portion with the first doped region, and the fifth doped region is connected with the second epitaxial layer.

13. The method of claim 12, wherein forming a well region, a source region, a plurality of second doped regions, and a trench gate in a surface of the third epitaxial layer facing away from the semiconductor substrate, comprises:

forming the well region in the third epitaxial layer, and forming the source region in the well region;

Forming the second doped region connecting the second epitaxial layer and the source region within the third epitaxial layer;

And forming the trench gate in the third epitaxial layer.