CN118039698A - Wide bandgap semiconductor trench MOSFET device structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a wide band gap semiconductor groove MOSFET device structure and a manufacturing method thereof, wherein the structure comprises a substrate, an epitaxial layer, a first P+ masking layer, a second P+ masking layer, a first source electrode P+ region and a second source electrode P+ region; the epitaxial layer grows on the substrate; the first source electrode P+ region, the first P+ masking layer, the second source electrode P+ region and the second P+ masking layer are manufactured in the epitaxial layer at intervals in sequence along the horizontal direction; and manufacturing a P-Bus region between the first source P+ region and the first P+ masking layer, and/or between the second source P+ region and the second P+ masking layer, and/or between the first P+ masking layer and the second source P+ region, so as to realize the electric connection between the P+ masking layer and the source P+ region. The structure not only can greatly improve the conduction characteristic of the device, but also can improve the trade-off relation between the specific on-resistance and the gate oxide reliability of the device.

Description

Wide bandgap semiconductor trench MOSFET device structure and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductor devices, in particular to a wide band gap semiconductor trench MOSFET device structure and a manufacturing method thereof.

Background

At present, a silicon carbide (SiC) device can realize P-type doping through ion implantation or epitaxial growth, but materials with a larger forbidden band width than silicon carbide, such as gallium nitride (GaN), gallium oxide (Ga ₂O₃), diamond (C), aluminum nitride (AlN) and the like, are difficult to realize P-type doping through ion implantation, and can realize P-type through special processes, such as growth epitaxy or oxide and the like. In practice, however, the wide bandgap semiconductor trench MOSFET device still has several problems in process fabrication and application: (1) The traditional device structure has insufficient protection to the grid electrode, the electric field at the angle of the grid electrode groove is easy to gather, so that the grid dielectric layer is broken down rapidly under high drain voltage, and the electrostatic effect on severe environment and the high-voltage spike tolerance capability in a circuit are poor; (2) The traditional device structure adopts a bottom P+ masking layer to reduce the electric field of the grid groove angle, but in order to ensure the dynamic reliability of the device, part of the chip area needs to be sacrificed so that the P+ masking layer is kept in a grounded state, but the chip area is sacrificed by the solution, and the conduction characteristic of the device is poor.

Therefore, there is a need for new structural designs for MOSFET device structures, and the present invention provides a new wide bandgap semiconductor trench MOSFET device structure.

Disclosure of Invention

Based on the above description, the invention provides a wide bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof, which not only can improve the on-state characteristics of the device, but also further improve the trade-off relationship between the specific on-state resistance and the gate oxide reliability of the device.

The technical scheme for solving the technical problems is as follows:

In a first aspect, the present invention provides a wide bandgap semiconductor trench MOSFET device structure comprising: the epitaxial layer is arranged on the substrate, and the epitaxial layer is arranged on the epitaxial layer;

the epitaxial layer is grown on the substrate; the first source electrode P+ region, the first P+ masking layer, the second source electrode P+ region and the second P+ masking layer are manufactured in the epitaxial layer at intervals in sequence along the horizontal direction;

and a P-Bus region is manufactured between the first source P+ region and the first P+ masking layer, and/or between the second source P+ region and the second P+ masking layer, and/or between the first P+ masking layer and the second source P+ region, so as to realize the electric connection between the P+ masking layer and the source P+ region.

On the basis of the technical scheme, the invention can be improved as follows.

Further, the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer which are sequentially laminated and manufactured on the substrate;

The first source P+ region and the second source P+ region are located in the first epitaxial layer and the second epitaxial layer, and the first P+ masking layer and the second P+ masking layer are located in the first epitaxial layer.

Furthermore, the epitaxial layer is sequentially provided with a P well region, a source N+ region, a source ohmic contact region and a source electrode from bottom to top.

Further, source trenches are respectively arranged in the first source P+ region and the second source P+ region;

The source electrode groove penetrates through the source electrode N+ region, the P well region and part of the second epitaxial layer;

A source electrode dielectric layer is arranged on the inner wall side of the source electrode groove, and source electrode polysilicon is filled in the source electrode groove;

The source polycrystalline silicon, the first source P+ region and the second source P+ region are electrically connected with the source electrode through a source ohmic contact region at the top of the source trench.

Further, the first P+ masking layer and the second P+ masking layer are respectively wrapped with a grid groove;

The grid groove penetrates through the source electrode N+ region, the P well region, the second epitaxial layer and part of the first epitaxial layer;

a gate dielectric layer is arranged on the inner wall side of the gate groove, and gate polysilicon is filled in the gate groove;

and the grid polysilicon is contacted with the source electrode through an interlayer dielectric layer at the top of the grid groove.

Further, the grid electrode groove is of a multi-stage groove structure.

Further, the wide bandgap semiconductor trench MOSFET device structure further comprises a drain electrode;

the drain electrode is arranged at the bottom of the substrate.

In a second aspect, the present invention further provides a method for fabricating the wide bandgap semiconductor trench MOSFET device structure according to the first aspect, including:

Epitaxially growing an epitaxial layer on a substrate, forming a P-well region through ion implantation, secondary epitaxy or growing P-type oxide, and forming a source electrode N+ region on the P-well region through ion implantation;

manufacturing a P-Bus region by ion implantation;

forming a source trench and a gate trench by dry etching;

Forming a first source electrode P+ region, a first P+ masking layer, a second source electrode P+ region and a second P+ masking layer respectively through P-type ion implantation;

And sequentially performing gate and source dielectric growth, gate and source polysilicon growth and etching, interlayer dielectric deposition and etching, ohmic contact metal deposition and annealing, source metal deposition and etching and drain metal deposition to obtain the semiconductor device.

On the basis of the technical scheme, the invention can be improved as follows.

Further, the epitaxial growth of the epitaxial layer on the substrate specifically includes:

and sequentially epitaxially growing a first epitaxial layer and a second epitaxial layer on the substrate.

Compared with the prior art, the technical scheme of the application has the following beneficial technical effects:

Compared with the prior art, the wide bandgap semiconductor trench MOSFET device structure and the manufacturing method thereof have the following advantages:

The P+ masking layer and the source electrode P+ region are kept electrically connected by constructing the P-Bus region in the space, at the moment, the P+ masking layer is kept in a grounding state, the dynamic reliability of the device can be improved, the cell part with the P-Bus region still can conduct current, the electron current flows inwards through a channel, the conduction characteristic of the device is greatly improved, and meanwhile, the trade-off relation between the specific conduction resistance and the gate oxide reliability of the device can be further improved by controlling the area proportion of two cells (with the P-Bus region and without the P-Bus region).

In addition, the manufacturing method and the corresponding structure form ohmic contact on the source electrode, so that the source electrode N+ region and the source electrode P+ region are short-circuited together; the grid multistage groove and the P+ masking layer at the bottom form a masking structure, so that the grid oxygen electric field intensity can be reduced, and the grid oxygen reliability of the device is improved. Meanwhile, the method does not need extra process steps, and the complex amplitude and cost of the device are reduced.

Drawings

Fig. 1 is a schematic three-dimensional structure diagram of a wide bandgap semiconductor trench MOSFET device structure according to an embodiment of the present invention;

fig. 2 is a schematic cross-sectional structure diagram of a wide bandgap semiconductor trench MOSFET device structure at a cross-section a according to an embodiment of the present invention;

Fig. 3 is a schematic cross-sectional structure diagram of a wide bandgap semiconductor trench MOSFET device structure at a cross-section B according to an embodiment of the invention;

fig. 4 to fig. 10 are schematic structural diagrams of several arrangements of P-Bus regions of the wide bandgap semiconductor trench MOSFET device structure provided by the present invention;

Fig. 11 is a schematic diagram of a manufacturing method of a wide bandgap semiconductor trench MOSFET device structure according to an embodiment of the present invention;

in the drawings, the list of components represented by the various numbers is as follows:

1. A substrate; 2. an epitaxial layer; 201. a first epitaxial layer; 202. a second epitaxial layer; 3. a first source p+ region; 4. a first P+ masking layer; 5. a second source P+ region; 6. a second P+ masking layer; 7. P-Bus region; 8. a P well region; 9. a source n+ region; 10. a source ohmic contact region; 11. a source electrode; 12. a source electrode dielectric layer; 13. source polycrystalline silicon; 14. a gate dielectric layer; 15. gate polysilicon; 16. an interlayer dielectric layer; 17. and a drain electrode.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "front side" and "back side" are used only to define two sides that are opposite. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.

The invention provides a novel wide bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof. Embodiments of the present invention will be described in further detail with reference to the accompanying drawings and examples, which are provided to illustrate the present invention, but are not intended to limit the scope of the present invention.

In a first aspect, as shown in fig. 1, an embodiment of the present invention provides a wide bandgap semiconductor trench MOSFET device structure, including: substrate 1, epitaxial layer 2, first p+ masking layer 4, second p+ masking layer 6, first source p+ region 3 and second source p+ region 5.

An epitaxial layer 2 is grown on the substrate 1; the first source p+ region 3, the first p+ masking layer 4, the second source p+ region 5 and the second p+ masking layer 6 are sequentially fabricated in the epitaxial layer 2 at intervals along the horizontal direction.

And a P-Bus region 7 is manufactured between the first source P+ region 3 and the first P+ masking layer 4, and/or between the second source P+ region 5 and the second P+ masking layer 6, and/or between the first P+ masking layer 4 and the second source P+ region 5, so as to realize the electrical connection between the P+ masking layer and the source P+ region.

Specifically, the epitaxial layer 2 includes a first epitaxial layer 201 and a second epitaxial layer 202 sequentially stacked and fabricated on a substrate; as shown in fig. 2, the first source p+ region 3 and the second source p+ region 5 are located in the first epitaxial layer 201 and the second epitaxial layer 202, and the first p+ mask layer 4 and the second p+ mask layer 6 are located in the second epitaxial layer 202.

The epitaxial layer 2 is sequentially provided with a P well region 8, a source N+ region 9, a source ohmic contact region 10 and a source electrode 11 from bottom to top.

In an alternative embodiment, as shown in fig. 1, source trenches are provided in the first source p+ region 3 and the second source p+ region 5, respectively.

The source trench is disposed through the source n+ region 9, the P-well region 8 and a portion of the second epitaxial layer 202.

A source dielectric layer 12 is provided on the inner wall side of the source trench, and the source trench is filled with source polysilicon 13.

The source polysilicon 13, the first source p+ region 3 and the second source p+ region 5 are all electrically connected to the source electrode through a source ohmic contact region at the top of the source trench.

Correspondingly, as shown in fig. 1, the first p+ masking layer 4 and the second p+ masking layer 6 are respectively wrapped with a gate trench.

The gate trench is disposed through the source n+ region 9, the P-well region 8, the second epitaxial layer 202 and a portion of the first epitaxial layer 201.

A gate dielectric layer 14 is arranged on the inner wall side of the gate trench, and gate polysilicon 15 is filled in the gate trench.

The gate polysilicon 15 is in contact with the source electrode 11 through an interlayer dielectric layer 16 on top of the gate trench.

Further, as shown in fig. 1, the gate trench is a multi-level trench structure.

The wide bandgap semiconductor trench MOSFET device structure further includes a drain electrode 17; the drain electrode 17 is provided at the bottom of the substrate 1.

It should be noted that: the connection of the first source p+ region 3, the first p+ masking layer 4, the second source p+ region 5 and the second p+ masking layer 6 includes various embodiments, as exemplified in fig. 3 to 7 (only cross-section B in fig. 1 is shown as an example, which is illustrative).

As shown in fig. 3, the first source p+ region is electrically connected to the first p+ mask layer, the second source p+ region and the second p+ mask layer through the P-Bus region, respectively.

It should be noted that: as shown in fig. 2 and fig. 3, schematic diagrams of electron current paths of a section a and a section B are provided respectively, it can be seen that a cell portion of a section B with a P-Bus region still can conduct current, and electron current flows inward through a channel and then enters the section a to be merged with the current of the section a, so that the current can be conducted in the section B with the p+ masking layer kept in a grounded state, and the conduction characteristic of the device is greatly improved.

As shown in fig. 4, the first p+ masking layer and the second source p+ region are electrically connected through the P-Bus region, that is, the P-Bus region in the section B may also be on the right side of the multi-level trench gate, so that the p+ masking layer on the right side of the bottom of the multi-level trench gate is connected to the source p+ region, which may also achieve the same effects as described above.

As shown in fig. 5, the first source p+ region and the first p+ masking layer, and the second source p+ region and the second p+ masking layer, and the P-Bus region are formed between the first p+ masking layer and the second source p+ region, but the P-Bus regions in the cross section B may be distributed on the left side and the right side of the multi-level trench gate, so that the p+ masking layer on the right side of the gate is connected to the source p+ in a partial region, and the p+ masking layer on the left side of the gate is connected to the source p+ in a partial region, which may also achieve the same effects as described above.

As shown in fig. 6, the first source p+ region, the first p+ masking layer, the second source p+ region and the second p+ masking layer are all connected by the P-Bus region, that is, the P-Bus region in the section B may also connect the p+ masking layers at all bottoms of the multi-level trench gate and the source p+ and may also achieve the same effects as described above.

As shown in FIG. 7, the gate structure may be a single level trench or a multi-level trench, the number of trench levels being N, N.gtoreq.1; the source electrode can be a non-groove, single-stage or multi-stage groove, the number of groove stages is M, and M is more than or equal to 0; correspondingly, the section B can also be the sectional arrangement of various P-Bus areas of the section B-1, the section B-2 and the section B-3, and the various arrangements can have the same effect, realize the conduction current and greatly improve the conduction characteristic of the device.

As shown in fig. 8, since the p+ masking layer at the bottom of the multi-level trench gate structure can well protect the gate structure and reduce the electric field at the bottom of the gate oxide, the source p+ region in the section a may not be needed, and may be all the gate trenches, the section B may simultaneously achieve the retention of the source p+ region and the grounding of the p+ masking layer, and the spatial arrangement of the gate trench and the source trench may be the top view 1, the top view 2, or other similar arrangements.

As shown in FIG. 9, a plurality of gate trenches can exist between two source trenches, wherein K.gtoreq.1, and the P-Bus region of section B connects two source P+ and a plurality of P+ masking layers in between, so that the P+ masking layers are kept in a grounded state.

As shown in fig. 10, a p+ implantation is performed at a certain angle at the bottom of the gate trench to form a p+ masking layer and a p+ Halo region with a larger protection range, so that the electric field of the gate oxide layer can be greatly reduced.

The above examples are only some embodiments of the present application, and other embodiments according to the variations of the above examples may fall within the scope of the present application, and those skilled in the art may implement the corresponding designs according to the above examples.

The embodiment of the invention forms a wide band gap semiconductor trench MOSFET device structure by constructing a trench gate structure, a source N+ region, a source P+ region, a P well region, a source electrode and a drain electrode. Forming ohmic contact on the source electrode to short-circuit the source electrode N+ region and the source electrode P+ region; the grid multilevel groove and the P+ masking layer at the bottom form a masking structure, so that the grid oxygen electric field intensity can be reduced, and the grid oxygen reliability of the device can be improved; the P+ masking layer and the source electrode P+ region are kept electrically connected by constructing the P-Bus region in the space, and the P+ masking layer is kept in a grounding state at the moment, so that the dynamic reliability of the device can be improved; as shown in fig. 2 and fig. 3, schematic diagrams of the electron current paths of the section a and the section B are provided, it can be seen that the section B cell portion with the P-Bus area still can conduct current, and the electron current flows inward through the channel and then enters the section a to be merged with the current of the section a, i.e. the section B cell portion still can conduct current. Meanwhile, the area ratio of the two cells of the section A and the section B can be controlled, so that the trade-off relation between the specific on-resistance and the gate oxide reliability of the device can be further improved.

In a second aspect, the embodiment of the present invention further provides a method for manufacturing a wide bandgap semiconductor trench MOSFET device structure (illustrated by taking cross sections a and B as examples), as shown in fig. 11, and the method operates as follows:

step S1: (section A and section B) a first N-epitaxial layer is grown on a wide bandgap semiconductor material (SiC/GaN/Ga ₂O₃/C/AlN, etc.) substrate.

Step S2: (section a and section B) a second N-epitaxial layer is grown on the first N-epitaxial layer.

Step S3: (section A and section B) P-well regions are formed by ion implantation, secondary epitaxy, growing P-type oxide, and the like.

Step S4: (section a and section B) a source n+ region is formed by ion implantation.

Step S5: (section B) the P-Bus region is formed by ion implantation.

Step S6: (section a and section B) the source trench and the gate first level trench are formed by dry etching.

Step S7: (section a and section B) dry etching to form a gate trench second level trench.

Step S8: (section a and section B) the source p+ region and the p+ mask layer are simultaneously formed by P-type ion implantation.

Step S9: (section a and section B) gate and source dielectric layer growth, gate and source polysilicon growth and etching, interlayer dielectric deposition and etching, ohmic contact metal deposition and annealing, source metal deposition and etching, drain metal deposition.

The manufacturing method is used for manufacturing the wide band gap semiconductor groove MOSFET device structure, so that the beneficial effects of the wide band gap semiconductor groove MOSFET device structure are applicable to the manufacturing method, and the beneficial effects of the wide band gap semiconductor groove MOSFET device structure can be described with reference to the effects and are not repeated herein.

In the description of the present specification, reference to the term "a particular example" or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the invention. In this specification, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (9)

1. A wide bandgap semiconductor trench MOSFET device structure comprising: the epitaxial layer is arranged on the substrate, and the epitaxial layer is arranged on the epitaxial layer;

the epitaxial layer is grown on the substrate; the first source electrode P+ region, the first P+ masking layer, the second source electrode P+ region and the second P+ masking layer are manufactured in the epitaxial layer at intervals in sequence along the horizontal direction;

and a P-Bus region is manufactured between the first source P+ region and the first P+ masking layer, and/or between the second source P+ region and the second P+ masking layer, and/or between the first P+ masking layer and the second source P+ region, so as to realize the electric connection between the P+ masking layer and the source P+ region.

2. The wide bandgap semiconductor trench MOSFET device structure of claim 1, wherein said epitaxial layer comprises a first epitaxial layer and a second epitaxial layer sequentially stacked on said substrate;

The first source P+ region and the second source P+ region are located in the first epitaxial layer and the second epitaxial layer, and the first P+ masking layer and the second P+ masking layer are located in the first epitaxial layer.

3. The wide bandgap semiconductor trench MOSFET device structure of claim 2, wherein said epitaxial layer is formed with a P-well region, a source n+ region, a source ohmic contact region, and a source electrode in order from bottom to top.

4. The wide bandgap semiconductor trench MOSFET device structure of claim 3, wherein source trenches are provided in said first source p+ region and said second source p+ region, respectively;

The source electrode groove penetrates through the source electrode N+ region, the P well region and part of the second epitaxial layer;

A source electrode dielectric layer is arranged on the inner wall side of the source electrode groove, and source electrode polysilicon is filled in the source electrode groove;

The source polysilicon, the first source P+ region and the second source P+ region are all in contact with the source electrode through a source ohmic contact region at the top of the source trench.

5. The wide bandgap semiconductor trench MOSFET device structure of claim 3, wherein said first p+ masking layer and said second p+ masking layer are each wrapped with a gate trench;

The grid groove penetrates through the source electrode N+ region, the P well region, the second epitaxial layer and part of the first epitaxial layer;

a gate dielectric layer is arranged on the inner wall side of the gate groove, and gate polysilicon is filled in the gate groove;

and the grid polysilicon is contacted with the source electrode through an interlayer dielectric layer at the top of the grid groove.

6. The wide bandgap semiconductor trench MOSFET device structure of claim 5, wherein said gate trench is a multi-level trench structure.

7. The wide bandgap semiconductor trench MOSFET device structure of claim 1, further comprising a drain electrode;

the drain electrode is arranged at the bottom of the substrate.

8. A method for fabricating the wide bandgap semiconductor trench MOSFET device structure of any of claims 1-7, comprising:

Epitaxially growing an epitaxial layer on a substrate, forming a P-well region through ion implantation, secondary epitaxy or growing P-type oxide, and forming a source electrode N+ region on the P-well region through ion implantation;

manufacturing a P-Bus region by ion implantation;

forming a source trench and a gate trench by dry etching;

Forming a first source electrode P+ region, a first P+ masking layer, a second source electrode P+ region and a second P+ masking layer respectively through P-type ion implantation;

And sequentially performing gate and source dielectric growth, gate and source polysilicon growth and etching, interlayer dielectric deposition and etching, ohmic contact metal deposition and annealing, source metal deposition and etching and drain metal deposition to obtain the semiconductor device.

9. The method of claim 8, wherein epitaxially growing an epitaxial layer on the substrate, comprises:

and sequentially epitaxially growing a first epitaxial layer and a second epitaxial layer on the substrate.