CN118039697A - Wide bandgap semiconductor trench MOSFET device structure and manufacturing method thereof - Google Patents

Wide bandgap semiconductor trench MOSFET device structure and manufacturing method thereof Download PDF

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Publication number
CN118039697A
CN118039697A CN202410115473.XA CN202410115473A CN118039697A CN 118039697 A CN118039697 A CN 118039697A CN 202410115473 A CN202410115473 A CN 202410115473A CN 118039697 A CN118039697 A CN 118039697A
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region
layer
gate
source
device structure
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成志杰
袁俊
郭飞
王宽
陈伟
吴阳阳
徐少东
彭若诗
朱厉阳
李明哲
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Hubei Jiufengshan Laboratory
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Hubei Jiufengshan Laboratory
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a wide band gap semiconductor groove MOSFET device structure and a manufacturing method thereof, wherein the structure comprises a substrate, a first epitaxial layer, a second epitaxial layer, a P+ masking layer, a gate electrode and a source electrode P+ region; the first epitaxial layer and the second epitaxial layer are sequentially stacked and grown on the substrate; the plurality of gate electrodes are sequentially arranged in the second epitaxial layer at intervals along the length direction of the device structure, a P+ masking layer is arranged at the bottom of any gate electrode, and the P+ masking layer is positioned in the second epitaxial layer; the source electrode P+ region penetrates through the P+ masking layer at intervals along the length direction of the gate electrode, and the P+ masking layer and the P+ buried layer are electrically connected with the source electrode P+ region. The structure not only can improve the conduction characteristic of the device, but also has a good masking effect, and can improve the dynamic reliability of the device.

Description

Wide bandgap semiconductor trench MOSFET device structure and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a wide band gap semiconductor trench MOSFET device structure and a manufacturing method thereof.
Background
At present, a silicon carbide (SiC) device can realize P-type doping through ion implantation or epitaxial growth, but materials with a larger forbidden band width than silicon carbide, such as gallium nitride (GaN), gallium oxide (Ga 2O3), diamond (C), aluminum nitride (AlN) and the like, are difficult to realize P-type doping through ion implantation, and can realize P-type through special processes, such as growth epitaxy or oxide and the like. In practice, however, the wide bandgap semiconductor trench MOSFET device still has several problems in process fabrication and application: (1) The high electric field of the material drift region causes the electric field on the gate dielectric layer to be high, and the problem is aggravated at the groove angle, so that the gate dielectric layer is rapidly broken down under high drain voltage; electrostatic effect against severe environment and poor high voltage spike tolerance in the circuit; (2) In order to reduce the gate angle electric field, the conventional device needs to sacrifice part of the chip area, and thus the on-characteristics of the device are deteriorated.
Therefore, there is a need for new structural designs for MOSFET device structures, and the present invention provides a new wide bandgap semiconductor trench MOSFET device structure.
Disclosure of Invention
Based on the expression, the invention provides the wide-bandgap semiconductor trench MOSFET device structure and the manufacturing method thereof, and the structure not only can improve the conduction characteristic of the device, but also can improve the dynamic reliability of the device.
The technical scheme for solving the technical problems is as follows:
in a first aspect, the present invention provides a wide bandgap semiconductor trench MOSFET device structure comprising: the semiconductor device comprises a substrate, a first epitaxial layer, a second epitaxial layer, a P+ masking layer, a gate electrode and a source P+ region;
The first epitaxial layer and the second epitaxial layer are sequentially grown on the substrate in a stacking manner;
The gate electrodes are sequentially arranged in the second epitaxial layer at intervals along the length direction of the device structure, the bottom of any gate electrode is provided with the P+ masking layer, and the P+ masking layer is positioned in the second epitaxial layer;
The source P+ region penetrates through the P+ masking layer at intervals along the length direction of the gate electrode, and the P+ masking layer and the P+ buried layer are electrically connected with the source P+ region.
On the basis of the technical scheme, the invention can be improved as follows.
Further, the wide bandgap semiconductor trench MOSFET device structure further comprises a P+ buried layer;
the P+ buried layer is manufactured between the first epitaxial layer and the second epitaxial layer;
an N+ current channel is arranged in the P+ buried layer, and the N+ current channel is located right below the P+ masking layer.
Further, the source electrode p+ region is arranged in the middle region of the gate electrode along the length direction of the device structure, the bottom of the source electrode p+ region is in contact with the p+ buried layer, and the side wall of the source electrode p+ region is in contact with the p+ masking layer.
Further, the wide bandgap semiconductor trench MOSFET device structure further comprises a gate connecting groove;
The grid electrodes are connected through the grid connecting grooves, the source electrode P+ area is wrapped in the grid connecting grooves, and the grid connecting grooves are used for assisting source electrode P+ ion implantation.
Further, a plurality of source p+ regions penetrate through the gate electrode at intervals along the length direction of the gate electrode.
Further, the bottom of the gate electrode is provided with the P+ masking layer and a P+ Halo region/P+ Teeth region, and the P+ Halo region/P+ Teeth region is arranged on two sides of the P+ masking layer.
Furthermore, a P well region, a source electrode N+ region, an ohmic contact region and a source electrode are sequentially manufactured on the second epitaxial layer from bottom to top.
Further, the gate electrode comprises a gate trench, a gate dielectric layer and gate polysilicon;
The grid groove penetrates through the source electrode N+ region, the P well region and part of the second epitaxial layer;
the inner wall side of the gate trench is provided with the gate dielectric layer, and the gate polysilicon is filled in the gate trench.
Further, the wide bandgap semiconductor trench MOSFET device structure further comprises a drain electrode;
the drain electrode is arranged at the bottom of the substrate.
In a second aspect, the present invention further provides a method for fabricating the wide bandgap semiconductor trench MOSFET device structure according to the first aspect, including:
Epitaxially growing an epitaxial layer on a substrate, forming a P-well region through ion implantation, secondary epitaxy and growing a P-type oxide, and forming a source electrode N+ region on the P-well region through ion implantation;
Sequentially epitaxially growing a first epitaxial layer, a P+ buried layer and a second epitaxial layer on a substrate;
forming a P-well region by ion implantation, secondary epitaxy and growing P-type oxide, and forming a source N+ region on the P-well region by ion implantation;
forming a source trench and a gate trench by dry etching;
forming a source P+ region by ion implantation;
forming a P+ masking layer through P-type ion implantation;
forming an N+ current channel through N-type ion implantation;
and sequentially performing gate dielectric growth, gate polysilicon growth and etching, interlayer dielectric deposition and etching, ohmic contact metal deposition and annealing, source metal deposition and etching and drain metal deposition to obtain the semiconductor device.
Compared with the prior art, the technical scheme of the application has the following beneficial technical effects:
Compared with the prior art, the wide bandgap semiconductor trench MOSFET device structure and the manufacturing method thereof have the following advantages:
(1) The grid connecting groove is in a strip shape and is directly connected with polysilicon around the chip, so that the grid connecting groove can provide a grid layout design for a square grid structure;
(2) In the traditional scheme, a source electrode P+ region is required to mask a grid electrode groove angle electric field on two sides of each grid electrode groove, the source electrode P+ region occupies a larger chip area, if the electric field is required to be further reduced, a P+ masking layer in a grounding state is required to be maintained, the p+ region also occupies a certain chip area, the design of the P+ masking layer is utilized to ensure the low grid electrode groove angle electric field to improve the dynamic reliability of the device, meanwhile, the chip area of the P+ masking layer in grounding and the chip area of the source electrode P+ region can adopt the same area in space, one-time ion implantation is saved, the process cost is saved, the chip area is greatly saved, and the conduction characteristic of the device is improved;
(3) By adopting N-P-N sandwich epitaxy, the P+ buried layer can naturally form a protection effect on the groove angle of the grid electrode, the N+ current channel can form a device conducting region, the P+ region of the source electrode is electrically connected with the P+ masking layer and the P+ buried layer, ohmic contact can be formed on the surface of the P+ region of the source electrode at two sides of the grid electrode connecting groove and the N+ region of the source electrode, the P+ buried layer and the P+ masking layer are in short circuit, and the structure has a good masking effect and can promote the dynamic reliability of the device.
Drawings
Fig. 1 is a schematic three-dimensional structure diagram of a wide bandgap semiconductor trench MOSFET device structure according to an embodiment of the present invention;
Fig. 2 is a schematic top-down cross-sectional structure diagram of a wide bandgap semiconductor trench MOSFET device structure according to an embodiment of the invention;
FIG. 3 is a schematic cross-sectional structure at section A of FIG. 1;
FIG. 4 is a schematic cross-sectional structure at section B of FIG. 1;
Fig. 5 is a schematic diagram of a manufacturing method of a wide bandgap semiconductor trench MOSFET device structure according to an embodiment of the present invention;
Fig. 6 to fig. 9 are schematic structural diagrams of several arrangements of source p+ regions of the wide bandgap semiconductor trench MOSFET device structure provided by the present invention;
in the drawings, the list of components represented by the various numbers is as follows:
1. a substrate; 2. a first epitaxial layer; 3. a second epitaxial layer; 4. a P+ masking layer; 5. a P well region; 6. a source n+ region; 7. a gate electrode; 701. a gate dielectric layer; 702. gate polysilicon; 8. a P+ buried layer; 9. a gate connecting groove; 10. an n+ current channel; 11. an ohmic contact region; 12. a source p+ region; 13. and a drain electrode.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "front side" and "back side" are used only to define two sides that are opposite. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
The invention provides a novel wide bandgap semiconductor trench MOSFET device structure and a manufacturing method thereof. Embodiments of the present invention will be described in further detail with reference to the accompanying drawings and examples, which are provided to illustrate the present invention, but are not intended to limit the scope of the present invention.
In a first aspect, as shown in fig. 1, an embodiment of the present invention provides a wide bandgap semiconductor trench MOSFET device structure, including: a substrate 1, a first epitaxial layer 2, a second epitaxial layer 3, a p+ masking layer 4, a gate electrode 7 and a source p+ region 12.
A first epitaxial layer 2 and a second epitaxial layer 3 are grown on a substrate 1 in sequence.
The gate electrodes 7 are sequentially arranged in the second epitaxial layer 3 at intervals along the length direction of the device structure, a P+ masking layer 4 is arranged at the bottom of any gate electrode 7, and the P+ masking layer 4 is positioned in the second epitaxial layer 3.
The source p+ region 12 penetrates the gate electrode 7 at intervals along the length direction of the gate electrode 7, and the p+ masking layer 4 and the p+ buried layer 8 are electrically connected to the source p+ region 12.
Specifically, the epitaxial layers include a first epitaxial layer 2 and a second epitaxial layer 3 which are sequentially stacked and fabricated on a substrate 1; as shown in fig. 1, a p+ buried layer 8 is formed between the first epitaxial layer 2 and the second epitaxial layer 3; an n+ current channel 10 is provided in the p+ buried layer 8 and the n+ current channel 10 is located directly under the p+ masking layer 4.
The second epitaxial layer 3 is sequentially provided with a P well region 5, a source N+ region 6, an ohmic contact region 11 and a source electrode from bottom to top.
The gate electrode 7 comprises a gate trench, a gate dielectric layer 701 and gate polysilicon 702; the gate trench penetrates through the source n+ region 6, the P-well region 5 and a part of the second epitaxial layer 3.
A gate dielectric layer 701 is arranged on the inner wall side of the gate trench, and gate polysilicon 702 is filled in the gate trench.
As shown in fig. 1, the wide bandgap semiconductor trench MOSFET device structure further includes a drain electrode 13; the drain electrode 13 is provided at the bottom of the substrate 1.
In an alternative embodiment, as shown in fig. 1, a source p+ region 12 is disposed in a middle region of the gate electrode 7 along a length direction of the device structure, a bottom of the source p+ region 12 is in contact with the p+ buried layer 8, and a sidewall of the source p+ region 12 is in contact with the p+ masking layer 4.
The wide bandgap semiconductor trench MOSFET device structure further comprises a gate connecting groove 9; the gate electrodes 7 are connected through the gate connecting grooves 9, the source electrode P+ regions 12 are wrapped around the gate connecting grooves 9, and the gate connecting grooves 9 are used for assisting source electrode P+ ion implantation. As shown in fig. 1 and fig. 4, the gate trench configured above the p+ buried layer 8 may be square, and if the gate trench is square, a gate connection groove structure is required to connect the p+ buried layer, the gate connection groove 9 is in a strip shape and is directly connected with polysilicon around the chip, and the configured gate connection groove may provide a gate layout design for the square gate structure.
Wherein the n+ current channel 10 opening may be greater than, less than, or equal to the gate trench width, and the n+ current channel 10 may be in the region directly below, below left, or below right of the gate trench.
Fig. 2 shows a top view of the p+ buried layer 8, the source p+ region 12, the p+ masking layer 4 and the n+ current channel 10, wherein the width of the p+ masking layer 4 may be greater than, less than or equal to the width of the n+ current channel 10. As can be seen in conjunction with fig. 3, both p+ masking layer 4 and p+ buried layer 8 may be spatially electrically connected to source p+ region 12.
It should be noted that the source p+ region 12 further includes various embodiments, as illustrated in fig. 6 to 9, and illustrated by way of example in fig. 6, with a section a and a section B.
In an alternative embodiment, as shown in fig. 6, the gate trench configured above the p+ buried layer may also be in a strip shape, when the gate trench is in a strip shape, a source p+ region may also be formed in space, and multiple source p+ regions penetrate through the gate electrode at intervals along the length direction of the gate electrode, so that the chip area of the p+ mask layer grounded and the chip area of the source p+ region may be in the same area in space, thereby saving one time of ion implantation, greatly saving the chip area, and improving the conduction characteristic of the device.
As shown in fig. 7, when the device structure is manufactured, a secondary epitaxy process is adopted to form a suspension junction, the suspension junction can modulate the electric field distribution of the device, and the breakdown characteristic of the device is improved; simultaneously, in the section B, a single layout is used in a secondary epitaxy-ion implantation process, so that two layers of suspension junctions are kept connected at the position, wherein the number of layers of the suspension junctions is N, and N is more than or equal to 1; meanwhile, a source electrode P+ region can be formed on the section B, so that the P+ masking layer and the floating junction are kept in a grounding state through the source electrode P+ region, and the dynamic characteristic of the floating junction device is improved; the design of the grid connecting groove and the source electrode P+ region greatly saves the chip area and improves the conduction characteristic of the device.
As shown in FIG. 8, when the P+ buried layer and the N+ current channel are not present, the gate structure is a single-stage trench, a multi-stage trench or a combination of single-stage and multi-stage arrangements, the vertical injection at the bottom and the P+ masking layer and the P+ Halo region (P+ Halo region) formed by a certain angle injection can form a better protection effect on the gate, the P+ Halo region is arranged at two sides of the P+ masking layer, the electric field of the gate oxide layer is reduced, the P+ region is formed by injecting the whole surface of the P+ in the section B, and meanwhile, the P+ masking layer can be kept in a space grounded state, so that the dynamic reliability of the device is improved.
As shown in FIG. 9, when there is no P+ buried layer and N+ current channel, the gate structure is a single-stage trench, a multi-stage trench or a combination of single-stage and multi-stage spaced arrangement, the vertical injection at the bottom of the multi-stage trench and the injection at a larger side wall angle form a P+ masking layer and a P+ Teeth region (P+ dentate region) which can form a better protection effect on the multi-stage trench gate, the P+ dentate region is arranged at two sides of the P+ masking layer, the P+ masking layer is not needed to be injected at the bottom of the single-stage trench, the P+ Teeth region of the multi-stage trench can be used to form a better protection effect on the single-stage gate trench, the electric field of the gate oxide layer is reduced, the whole surface of P+ in the section B is injected to form a source P+ region, and meanwhile, the P+ masking layer can be kept in a grounded state in space, and the dynamic reliability of the device is improved.
The above examples are only some embodiments of the present application, and other embodiments according to the variations of the above examples may fall within the scope of the present application, and those skilled in the art may implement the corresponding designs according to the above examples.
According to the embodiment of the invention, a P well region, a P+ masking layer, a grid connecting groove, a source electrode P+ region, a source electrode N+ region, a source electrode and a drain electrode are constructed to form a wide-forbidden-band semiconductor trench gate MOSFET device structure, wherein the grid connecting groove and a grid trench are connected together above a semiconductor through grid polysilicon, the surfaces of the source electrode P+ regions on two sides and the source electrode N+ region form ohmic contact at the same time, the grid connecting groove is in a strip shape and is directly connected with polysilicon around a chip, and therefore, the constructed grid connecting groove can provide a grid layout design for a square grid structure; in the traditional scheme, the two sides of each grid groove are required to mask the grid groove angle electric field by the P+ region of the source electrode, the P+ region of the source electrode occupies a larger chip area, if the electric field is required to be further reduced, the P+ masking layer which is required to be in a grounding state is also required to occupy a certain chip area, the design of the P+ masking layer is utilized to ensure that the dynamic reliability of the device is improved by the low grid groove angle electric field, and meanwhile, the chip area grounded by the P+ masking layer and the chip area of the P+ region of the source electrode can be in the same area in space, so that one-time ion implantation is saved, the process cost is saved, the chip area is greatly saved, and the conduction characteristic of the device is improved.
In addition, the N-P-N sandwich epitaxy is adopted in the structure, the P+ buried layer can naturally form a protection effect on the groove angle of the grid electrode, the N+ current channel can form a device conducting area, the P+ area of the source electrode is electrically connected with the P+ masking layer and the P+ buried layer, ohmic contact can be formed on the surface of the P+ area of the source electrode at two sides of the grid electrode connecting groove and the N+ area of the source electrode, the P+ buried layer and the P+ masking layer are in short circuit, the structure has a good masking effect, and the dynamic reliability of the device can be improved.
In a second aspect, the embodiment of the present invention further provides a method for manufacturing a wide bandgap semiconductor trench MOSFET device structure (illustrated by taking cross sections a and B as examples), as shown in fig. 5, and the method operates as follows:
Step S1: (section A & B) A first N-epitaxial layer is grown on a substrate of wide bandgap semiconductor material (SiC/GaN/Ga 2O3/C/AlN, etc.).
Step S2: (section a & B) a P + buried layer is grown on the first N-epi layer.
Step S3: and (section A & B) growing a second N-epitaxial layer on the P+ buried layer.
Step S4: (section A & B) forming a P well region by means of ion implantation, secondary epitaxy, growing P-type oxide and the like; the source n+ region is formed by ion implantation.
Step S5: and (section A (left) and section B (right)) forming a gate trench and a gate connection groove by dry etching.
Step S6: (section B) the source p+ region is formed by ion implantation.
Step S7: (section a (left) and section B (right)) forming a p+ mask layer by P-type ion implantation.
Step S8: (section a (left) and section B (right)) forms an n+ current channel by N-type ion implantation.
Step S9: (section A (left) & section B (right)) gate dielectric growth, gate polysilicon growth and etching, interlayer dielectric growth and etching, ohmic contact metal deposition and annealing, source metal deposition and etching, drain metal deposition.
The manufacturing method is used for manufacturing the wide band gap semiconductor groove MOSFET device structure, so that the beneficial effects of the wide band gap semiconductor groove MOSFET device structure are applicable to the manufacturing method, and the beneficial effects of the wide band gap semiconductor groove MOSFET device structure can be described with reference to the effects and are not repeated herein.
In the description of the present specification, reference to the term "a particular example" or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the invention. In this specification, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A wide bandgap semiconductor trench MOSFET device structure comprising: the semiconductor device comprises a substrate, a first epitaxial layer, a second epitaxial layer, a P+ masking layer, a gate electrode and a source P+ region;
The first epitaxial layer and the second epitaxial layer are sequentially grown on the substrate in a stacking manner;
The gate electrodes are sequentially arranged in the second epitaxial layer at intervals along the length direction of the device structure, the bottom of any gate electrode is provided with the P+ masking layer, and the P+ masking layer is positioned in the second epitaxial layer;
The source P+ region penetrates through the P+ masking layer at intervals along the length direction of the gate electrode, and the P+ masking layer and the P+ buried layer are electrically connected with the source P+ region.
2. The wide bandgap semiconductor trench MOSFET device structure of claim 1, further comprising a p+ buried layer;
the P+ buried layer is manufactured between the first epitaxial layer and the second epitaxial layer;
an N+ current channel is arranged in the P+ buried layer, and the N+ current channel is located right below the P+ masking layer.
3. The wide bandgap semiconductor trench MOSFET device structure of claim 2, wherein said source p+ region is disposed in a central region of said gate electrode along a length direction of said device structure, a bottom of said source p+ region is in contact with said p+ buried layer, and a sidewall of said source p+ region is in contact with said p+ masking layer.
4. The wide bandgap semiconductor trench MOSFET device structure of claim 3, further comprising a gate connection trench;
The grid electrodes are connected through the grid connecting grooves, the source electrode P+ area is wrapped in the grid connecting grooves, and the grid connecting grooves are used for assisting source electrode P+ ion implantation.
5. The wide bandgap semiconductor trench MOSFET device structure of claim 1, wherein a plurality of said source p+ regions extend through said gate electrode at intervals along a length of said gate electrode.
6. The wide bandgap semiconductor trench MOSFET device structure of claim 5, wherein said gate electrode bottom is provided with said p+ masking layer and p+ Halo/p+ Teeth regions, said p+ Halo/p+ Teeth regions being provided on both sides of said p+ masking layer.
7. The wide bandgap semiconductor trench MOSFET device structure of claim 1, wherein said second epitaxial layer has a P-well region, a source n+ region, an ohmic contact region, and a source electrode fabricated in sequence from bottom to top.
8. The wide bandgap semiconductor trench MOSFET device structure of claim 7, wherein said gate electrode comprises a gate trench, a gate dielectric layer, and gate polysilicon;
The grid groove penetrates through the source electrode N+ region, the P well region and part of the second epitaxial layer;
the inner wall side of the gate trench is provided with the gate dielectric layer, and the gate polysilicon is filled in the gate trench.
9. The wide bandgap semiconductor trench MOSFET device structure of claim 1, further comprising a drain electrode;
the drain electrode is arranged at the bottom of the substrate.
10. A method for fabricating the wide bandgap semiconductor trench MOSFET device structure of any of claims 1-9, comprising:
Sequentially epitaxially growing a first epitaxial layer, a P+ buried layer and a second epitaxial layer on a substrate;
forming a P-well region by ion implantation, secondary epitaxy and growing P-type oxide, and forming a source N+ region on the P-well region by ion implantation;
forming a source trench and a gate trench by dry etching;
forming a source P+ region by ion implantation;
forming a P+ masking layer through P-type ion implantation;
forming an N+ current channel through N-type ion implantation;
And sequentially performing gate dielectric growth, gate polysilicon deposition and etching, interlayer dielectric deposition and etching, ohmic contact metal deposition and annealing, source metal deposition and etching and drain metal deposition to obtain the semiconductor device.
CN202410115473.XA 2024-01-26 2024-01-26 Wide bandgap semiconductor trench MOSFET device structure and manufacturing method thereof Pending CN118039697A (en)

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