CN118471965A - TPAK packaging structure with four parallel layout of silicon carbide chips - Google Patents
TPAK packaging structure with four parallel layout of silicon carbide chips Download PDFInfo
- Publication number
- CN118471965A CN118471965A CN202410930846.9A CN202410930846A CN118471965A CN 118471965 A CN118471965 A CN 118471965A CN 202410930846 A CN202410930846 A CN 202410930846A CN 118471965 A CN118471965 A CN 118471965A
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- Prior art keywords
- heat dissipation
- copper layer
- signal terminal
- chip
- power terminal
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 32
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 32
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052802 copper Inorganic materials 0.000 claims abstract description 49
- 239000010949 copper Substances 0.000 claims abstract description 49
- 230000017525 heat dissipation Effects 0.000 claims abstract description 46
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000005022 packaging material Substances 0.000 claims description 3
- 238000012536 packaging technology Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 229910002601 GaN Inorganic materials 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
A TPAK packaging structure with four parallel layouts of silicon carbide chips comprises a carrier component, a chip set, a heat dissipation component and a cover plate. The carrier assembly includes a connection copper layer, a first power terminal, a second power terminal, a first signal terminal, and a second signal terminal. The second power terminal comprises an output part, a heat dissipation part and a connecting part. The heat dissipation assembly comprises a first heat dissipation assembly and a second heat dissipation assembly. Compared with the prior art, the invention increases the space which can be laid out by arranging the first power terminal and the connecting copper layer which are integrally formed, and reduces the occupation of the connecting structure to the space by arranging the connecting structure and the bonding wire. The plurality of connection parts of the second power terminal are respectively welded on each chip of the chip set, so that a multi-chip parallel layout scheme is formed. And meanwhile, the heat dissipation assembly is arranged to conduct double-sided heat dissipation on the chip set, so that the heat dissipation capacity of the chip is guaranteed.
Description
Technical Field
The invention relates to the technical field of power semiconductor device packaging, in particular to a TPAK packaging structure with four parallel layout of silicon carbide chips.
Background
The silicon carbide driving module is a single switch module with high current density and is specially designed for the application of the main driving inverter of the new energy automobile. The silicon carbide MOSFET bare chip can be filled, and IGBT or gallium nitride HEMT and the like can be selected as core chips. The silicon carbide driving module can be used as a high-performance silicon carbide driving module, can be used as a high-cost-performance IGBT power module, and can be seamlessly connected with a gallium nitride bare chip to be a high-frequency power switch device even after the high-power gallium nitride technology of the vehicle is mature. The TPAK (Tesla Pack) package adopts a single-switch Module (SINGLE SWITCH Module) design between a single tube and a conventional Module, which not only surpasses the limitations of output current, output power, parasitic inductance and the like brought by the prior single tube package, but also reserves the flexibility of multi-tube parallel connection, and can select the parallel connection quantity of the silicon carbide driving modules according to different inverter power output requirements.
In the current TPAK packaging structure, as the power requirement is higher, the number of chips connected in parallel is increased, the thermal coupling generated correspondingly is higher, the space for layout is smaller, and therefore the packaging requirement is higher.
Disclosure of Invention
In view of the above, the present invention provides a TPAK package structure with four parallel layout of silicon carbide chips to solve the above technical problems.
A TPAK packaging structure with four parallel-connection layout of silicon carbide chips comprises a carrier component serving as a substrate, a chip set arranged on the carrier component, a heat dissipation component arranged on the chip set and a cover plate arranged on the carrier component. The carrier assembly comprises a connecting copper layer, a first power terminal connected with the connecting copper layer, a second power terminal arranged between the first power terminal and the connecting copper layer, a first signal terminal arranged on one side of the second power terminal, and a second signal terminal which is positioned on the same side of the connecting copper layer as the first signal terminal and is arranged at intervals with the first signal terminal. The second power terminal comprises an output part, a plurality of heat dissipation parts which are arranged at intervals, and a plurality of connection parts which are arranged between the heat dissipation parts. The plurality of connecting parts are respectively and electrically connected with each chip of the chip set. The chip set comprises four silicon carbide chips, and the four silicon carbide chips are respectively connected to the connecting copper layer and are in a rectangular array. The heat dissipation assembly comprises a first heat dissipation assembly positioned on one side of the carrier assembly and a second heat dissipation assembly positioned on the other side of the carrier assembly. The first heat dissipation component is connected to a plurality of the heat dissipation parts of the second power terminal. The second heat dissipation assembly is closely attached to the connection copper layer and is located on the other side, far away from the chip set, of the connection copper layer.
Further, the connecting copper layer comprises an upper copper layer, a lower copper layer and a silicon nitride insulating layer which are connected with each other.
Further, the first power terminal and the connection copper layer are integrally formed.
Further, the output part is located at a free end of the second power terminal, which is far away from the connecting copper layer, and extends out of the side surface of the cover plate when the cover plate is assembled, and the heat dissipation part is of a plate-shaped structure.
Further, the first signal terminal is a gate signal terminal and is fixedly connected to a connection structure.
Further, the connection structure is fixed on the connection copper layer, is located at one end of the connection copper layer, which is close to the second power terminal, and is arranged at intervals with the heat dissipation part, and the connection structure is connected with the gate electrode of each chip from two sides of the second power terminal respectively.
Further, the second signal terminal is an emitter signal terminal, is located at one side of the second power terminal, and is integrally formed, and an end portion of the second signal terminal is connected with the output portion.
Further, the cover plate is made of plastic packaging material, the chip set and the heat dissipation assembly are packaged in the cover plate through plastic packaging technology, the first power terminal and the second power terminal extend out of two sides of the cover plate respectively, and the first signal terminal and the second signal terminal extend out of one side where the second power terminal is located.
Compared with the prior art, the TPAK packaging structure with the four parallel layout of the silicon carbide chips has the advantages that through the arrangement of the integrally formed first power terminal and the connecting copper layer so as to connect the collector electrode of each chip, the space capable of being laid out is increased, and through the arrangement of the connecting structure and the bonding wire, the first signal terminal is ensured to be connected to the gate electrode of each chip, and the occupation of the connecting structure to the space is reduced. The plurality of connection parts of the second power terminal are respectively welded on each chip of the chip set, so that a multi-chip parallel layout scheme is formed, and the requirements of the market on high-power chips are met. Meanwhile, through the arrangement of the heat dissipation assembly, the chip set is subjected to double-sided heat dissipation, so that the problems of increased chip temperature and increased chip temperature due to the enhancement of four-chip parallel thermal coupling are solved, and the heat dissipation capacity of the chip is ensured.
Drawings
Fig. 1 is a schematic structural diagram of a TPAK package structure with a four-parallel layout of silicon carbide chips according to the present invention.
Fig. 2 is an exploded view of a TPAK package structure of the four parallel layout of silicon carbide chips of fig. 1.
Fig. 3 is a schematic diagram illustrating an internal structure of a TPAK package structure with a four-parallel layout of the silicon carbide chip of fig. 1.
Detailed Description
Specific embodiments of the present invention are described in further detail below. It should be understood that the description herein of the embodiments of the invention is not intended to limit the scope of the invention.
Fig. 1 to 3 are schematic structural diagrams of a TPAK package structure with a four-parallel layout of silicon carbide chips according to the present invention. The TPAK package structure of the four parallel arrangement of silicon carbide chips comprises a carrier assembly 10 serving as a substrate, a chip set 20 arranged on the carrier assembly 10, a heat dissipation assembly 30 arranged on the chip set 20 and a cover plate 40 arranged on the carrier assembly 10. It is conceivable that the TPAK package structure with the four parallel arrangement of silicon carbide chips further includes other functional modules such as a radiator for connecting heat dissipation, fasteners on the package structure, etc., which are known to those skilled in the art, and will not be described in detail herein.
The carrier assembly 10 comprises a connection copper layer 11, a first power terminal 12 connected to the connection copper layer 11, a second power terminal 13 arranged at a distance from the connection copper layer 11, a first signal terminal 14 arranged on one side of the second power terminal 13, and a second signal terminal 15 arranged at the same side of the connection copper layer 11 as the first signal terminal 14 and at a distance from the first signal terminal 14.
The connection copper layer 11 is a carrier layer for carrying the above structure, and includes an upper copper layer, a lower copper layer and a silicon nitride insulating layer connected by solder, and the above structure is a common technology applied in TPAK devices, so that a detailed description thereof will not be given here.
The first power terminal 12 and the second power terminal 13 are respectively used for connecting different electrodes. The first power terminal 12 and the upper copper layer of the connection copper layer 11 are integrally formed, so that the layout space is increased, and meanwhile, the use of solder is effectively reduced, and the risk of solder failure is reduced.
The second power terminal 13 includes an output portion 131, a plurality of heat dissipation portions 132 disposed at intervals from each other, and a plurality of connection portions 133 disposed between the heat dissipation portions 132. The output portion 131 is located at a free end of the second power terminal 13 and protrudes from a side of the cap plate 40 when the cap plate 40 is assembled, so as to serve as a connection end of a circuit. The heat dissipation portion 132 has a plate-like structure, so that a larger contact surface is obtained when the heat dissipation portion is connected to the heat dissipation assembly 30, thereby obtaining a better heat dissipation effect. The plurality of connection parts 133 may be electrically connected to each chip of the chipset 20 through Cu-Clip interconnection technology, specifically, the second power terminals 13 are soldered to the upper ends of the chips by means of one reflow, specifically, each connection part 133 of the second power terminals 13 is connected to an emitter of each chip, respectively. The Cu-Clip interconnection technology is a prior art applied to the field of power semiconductor devices, and is described in connection with a Clip copper sheet and strip as mentioned in chinese invention CN202111502245.0, which will be understood by those skilled in the art, and therefore the principles thereof will not be described in detail herein.
The first power terminal 12, the second power terminal 13, the first signal terminal 14 and the second signal terminal 15 are perforated on the surface, and the main structure with turning parts is arranged, so that the cover plate 40 can be clamped at the edge of the packaging shell when being used for packaging, the stress is more stable, and the terminals are not easy to fall off.
The first signal terminal 14 is a gate signal terminal, and is connected to a connection structure 141 through a Cu-Clip. The connection structure 141 is fixed on the connection copper layer 11, and is located at one end of the connection copper layer 11 near the second power terminal 13, and is spaced from the heat dissipation portion 132, so that the connection structure 141 and the second power terminal 13 will not be affected by contact. The connection structure 141 connects the gate electrode of each chip from both sides of the second power terminal 13, respectively, to make the space more compact and reduce the occupation space of the connection structure while achieving the connection of the first signal terminal 14 with the gate electrode of the chip by using the bonding wire 142.
The second signal terminal 15 is an emitter signal terminal, and is located at one side of the second power terminal 13, and the end portion of the second signal terminal is connected to the output portion 131, and is integrally formed, so that the second signal terminal 13 is connected to the emitters of the chips, thereby reducing the occupied space of the additional connection structure.
The chipset 20 includes four silicon carbide chips. Four chips are soldered on the connection copper layer 11 by solder one reflow, respectively, and are presented as rectangular arrays. Because the four chips are welded on the connecting copper layer 11, and the collectors of the chips are simultaneously contacted with the connecting copper layer 11 and are connected with an external circuit through the first power terminal 12 integrally formed with the connecting copper layer 11, and the emitters of the four chips are respectively welded with the second power terminal 13 at the same time, the four chips form a parallel layout.
The heat sink assembly 30 includes a first heat sink assembly 31 on one side of the carrier assembly 10 and a second heat sink assembly 32 on the other side of the carrier assembly 10. The first heat dissipation component 31 is soldered to the heat dissipation portion 132 and located at a side far from the chipset 20 for cooling the chip. The second heat dissipation component 32 is disposed closely to the connection copper layer 11 and is located on the other side of the connection copper layer 11 away from the chipset 20, so as to reduce a greater temperature rise due to thermal coupling when four chips are connected in parallel.
The cover 40 may be a plastic material that wraps around the outside of each functional module, and encapsulates the chipset 20 and the heat dissipating component 30 by using a plastic packaging technology. Portions of the first power terminal 12 and the second power terminal 13 protrude from both sides of the cap plate 40, respectively. The first signal terminal 14 and the second signal terminal 15 extend out of the cover plate 40 from the side where the second power terminal 13 is located, enough space is reserved to design corresponding thimble positioning holes, and finally packaging is completed through plastic packaging materials, so that stability of the structure is guaranteed.
Compared with the prior art, the TPAK packaging structure with the four parallel layout of the silicon carbide chips has the advantages that through the arrangement of the integrally formed first power terminal 12 and the connecting copper layer 11 so as to connect the collector electrode of each chip, the space capable of being laid out is increased, and through the arrangement of the connecting structure 141 and the bonding wire 142, the first signal terminal 14 can be ensured to be connected to the gate electrode of each chip, and the occupation of the connecting structure to the space is reduced. The plurality of connection portions 132 of the second power terminal 13 are respectively soldered on each chip of the chipset 20, so as to form a multi-chip parallel layout scheme, so as to meet the market demand for high-power chips. Meanwhile, by arranging the heat dissipation assembly 30, the two-sided heat dissipation is performed on the chipset 20, so that the problems of increased chip temperature and increased chip temperature due to the enhancement of four-chip parallel thermal coupling are solved, and the heat dissipation capability of the chip is ensured.
The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions or improvements within the spirit of the present invention are intended to be covered by the claims of the present invention.
Claims (8)
1. A TPAK packaging structure of four parallel layouts of silicon carbide chips is characterized in that: the TPAK packaging structure of the four parallel layout of the silicon carbide chips comprises a carrier component serving as a substrate, a chip set arranged on the carrier component, a heat dissipation component arranged on the chip set, and a cover plate arranged on the carrier component, wherein the carrier component comprises a connecting copper layer, a first power terminal connected with the connecting copper layer, a second power terminal arranged at intervals between the connecting copper layer, a first signal terminal arranged at one side of the second power terminal, a second signal terminal arranged at the same side of the connecting copper layer as the first signal terminal and arranged at intervals with the first signal terminal, the second power terminal comprises an output part, a plurality of heat dissipation parts arranged at intervals with each other, and a plurality of connecting parts arranged between the heat dissipation parts, the connecting parts are respectively electrically connected with each chip of the chip set, the chip set comprises four silicon carbide chips, the four chips are respectively connected with the connecting copper layer, the four chips are respectively rectangular, the first signal terminals are arranged at the same side of the connecting copper layer and are arranged at intervals with the first signal terminal, the first signal terminal is arranged at intervals with the first signal terminal, the second signal terminal is arranged at the other side of the first signal terminal, the first signal terminal is far away from the carrier component, and is arranged at the other side of the first heat dissipation component, and is far away from the first heat dissipation component.
2. The silicon carbide chip four-parallel layout TPAK package structure as set forth in claim 1, wherein: the connecting copper layer comprises an upper copper layer, a lower copper layer and a silicon nitride insulating layer which are connected with each other.
3. The silicon carbide chip four-parallel layout TPAK package structure as set forth in claim 1, wherein: the first power terminal and the connecting copper layer are integrally formed.
4. The silicon carbide chip four-parallel layout TPAK package structure as set forth in claim 1, wherein: the output part is positioned at the free end of the second power terminal, which is far away from the connecting copper layer, and extends out of the side surface of the cover plate when the cover plate is assembled, and the heat dissipation part is of a plate-shaped structure.
5. The silicon carbide chip four-parallel layout TPAK package structure as set forth in claim 1, wherein: the first signal terminal is a gate signal terminal and is fixedly connected to a connecting structure.
6. The silicon carbide chip four-parallel layout TPAK package structure as set forth in claim 5, wherein: the connecting structure is fixed on the connecting copper layer, is positioned at one end of the connecting copper layer, which is close to the second power terminal, and is arranged at intervals with the heat dissipation part, and the two sides of the connecting structure from the second power terminal are respectively connected with the gate electrode of each chip.
7. The silicon carbide chip four-parallel layout TPAK package structure as set forth in claim 1, wherein: the second signal terminal is an emitter signal terminal, is positioned at one side of the second power terminal, and is integrally formed, and the end part of the second signal terminal is connected with the output part.
8. The silicon carbide chip four-parallel layout TPAK package structure as set forth in claim 1, wherein: the cover plate is made of plastic packaging material, the chip set and the heat dissipation assembly are packaged in the cover plate through plastic packaging technology, the first power terminal and the second power terminal extend out of two sides of the cover plate respectively, and the first signal terminal and the second signal terminal extend out of one side where the second power terminal is located.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410930846.9A CN118471965A (en) | 2024-07-12 | 2024-07-12 | TPAK packaging structure with four parallel layout of silicon carbide chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410930846.9A CN118471965A (en) | 2024-07-12 | 2024-07-12 | TPAK packaging structure with four parallel layout of silicon carbide chips |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118471965A true CN118471965A (en) | 2024-08-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410930846.9A Pending CN118471965A (en) | 2024-07-12 | 2024-07-12 | TPAK packaging structure with four parallel layout of silicon carbide chips |
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| CN (1) | CN118471965A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW586654U (en) * | 2003-06-17 | 2004-05-01 | Molex Inc | Heat dissipation module |
| CN210403712U (en) * | 2019-09-30 | 2020-04-24 | 比亚迪股份有限公司 | Power module |
| US20200161224A1 (en) * | 2017-08-30 | 2020-05-21 | Yangzhou Guoyang Electronic Co.,Ltd. | Parallel electrode combination, power module and power module group |
| CN114267649A (en) * | 2021-12-15 | 2022-04-01 | 合肥综合性国家科学中心能源研究院(安徽省能源实验室) | Double-sided heat dissipation SiC half-bridge module packaging structure with extremely low parasitic inductance |
| CN219040462U (en) * | 2022-11-01 | 2023-05-16 | 浙江谷蓝电子科技有限公司 | Semiconductor power module bonded with SiC chip by aluminum-clad copper wire |
| JP3245862U (en) * | 2023-10-27 | 2024-02-28 | チャイナ エフエーダブリュー カンパニー リミテッド | Power module package structure and operating equipment |
| CN117672994A (en) * | 2023-10-26 | 2024-03-08 | 中国第一汽车股份有限公司 | Plastic packaging power module and vehicle |
| CN117878077A (en) * | 2024-01-19 | 2024-04-12 | 浙江翠展微电子有限公司 | Single-row TPAK and micro-channel double-sided heat dissipation power module device |
-
2024
- 2024-07-12 CN CN202410930846.9A patent/CN118471965A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW586654U (en) * | 2003-06-17 | 2004-05-01 | Molex Inc | Heat dissipation module |
| US20200161224A1 (en) * | 2017-08-30 | 2020-05-21 | Yangzhou Guoyang Electronic Co.,Ltd. | Parallel electrode combination, power module and power module group |
| CN210403712U (en) * | 2019-09-30 | 2020-04-24 | 比亚迪股份有限公司 | Power module |
| CN114267649A (en) * | 2021-12-15 | 2022-04-01 | 合肥综合性国家科学中心能源研究院(安徽省能源实验室) | Double-sided heat dissipation SiC half-bridge module packaging structure with extremely low parasitic inductance |
| CN219040462U (en) * | 2022-11-01 | 2023-05-16 | 浙江谷蓝电子科技有限公司 | Semiconductor power module bonded with SiC chip by aluminum-clad copper wire |
| CN117672994A (en) * | 2023-10-26 | 2024-03-08 | 中国第一汽车股份有限公司 | Plastic packaging power module and vehicle |
| JP3245862U (en) * | 2023-10-27 | 2024-02-28 | チャイナ エフエーダブリュー カンパニー リミテッド | Power module package structure and operating equipment |
| CN117878077A (en) * | 2024-01-19 | 2024-04-12 | 浙江翠展微电子有限公司 | Single-row TPAK and micro-channel double-sided heat dissipation power module device |
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