CN114267649A

CN114267649A - Double-sided heat dissipation SiC half-bridge module packaging structure with extremely low parasitic inductance

Info

Publication number: CN114267649A
Application number: CN202111531788.5A
Authority: CN
Inventors: 王佳宁; 於少林; 周伟男; 刘元剑
Original assignee: Institute of Energy of Hefei Comprehensive National Science Center
Current assignee: Institute of Energy of Hefei Comprehensive National Science Center
Priority date: 2021-12-15
Filing date: 2021-12-15
Publication date: 2022-04-01

Abstract

The invention discloses a double-sided heat dissipation SiC half-bridge module packaging structure with extremely low parasitic inductance. The packaging structure comprises a top DBC, a bottom DBC, a direct current terminal, an output terminal, a SiC chip, a gasket and a driving pin. The direct current terminal is composed of a positive terminal lamination and a negative terminal lamination, and parasitic inductance is reduced by the lamination. The positive terminal is connected with the bottom DBC, and two welding points and two screw holes are formed, so that the symmetry of the loop is favorably kept; the negative terminal is connected to the top DBC, with two solder joints and a centrally located screw hole, which is beneficial to maintaining loop symmetry. The gasket divide into buffer spacer and connecting pad, and buffer spacer welds between chip and top DBC, plays buffering and connection effect, and the material of buffer spacer is metal molybdenum, can alleviate chip thermal stress, prevents the chip fracture. The invention can effectively reduce the voltage peak in the switching process of the device and ensure that the multi-chip parallel connection has good current-sharing property. In addition, the module design is standardized, so that the module has excellent expansibility.

Description

Double-sided heat dissipation SiC half-bridge module packaging structure with extremely low parasitic inductance

Technical Field

The invention relates to a semiconductor device, in particular to a double-sided heat dissipation SiC half-bridge module packaging structure with extremely low parasitic inductance.

Background

The power semiconductor device is a core component of the power electronic converter. In recent years, with the rapid development of power electronic technology in the fields of new energy power generation, electric vehicles, and the like, and the development of wide bandgap semiconductors such as SiC, new demands have been made on power semiconductor devices.

Although wide bandgap semiconductors such as SiC have higher operating temperatures, higher breakdown voltage strengths, higher thermal conductivities, and higher switching frequencies than Si-based semiconductors. However, when the conventional packaging technology based on Si power devices is used to package wide bandgap semiconductor power devices, two major problems are caused. Firstly, the traditional packaging technology adopts wire bonding to realize complex internal interconnection in the structure, which can bring larger parasitic inductance, when the power semiconductor device is turned off, the energy stored in the larger parasitic inductance can cause voltage spike and oscillation at most, and the loss is increased possibly, and along with the increasing switching speed of the power semiconductor device in recent years, the problem of the packaged parasitic inductance is more prominent. Therefore, in order to ensure the performance and safe operation of the power device and the power electronic system, attention needs to be paid to reducing the parasitic inductance of the package when the power module is packaged. Secondly, the heat dissipation mode of traditional packaging technology is mostly single face heat dissipation, consequently, the radiating efficiency is poor. The SiC device can work at a higher temperature, so that the SiC device has a higher requirement in terms of heat dissipation, and if there is no efficient heat dissipation manner, the reliability of the module is affected.

Therefore, the development of a package structure with low parasitic inductance and high efficiency heat dissipation has become a hot issue of research, which has been deeply theoretically analyzed by academic papers, and has an engineering method for practical application, such as the invention and application patents of "package structure and processing technology of double-sided heat dissipation IPM hybrid module" (CNl09920785A) and "three-dimensional stacked package structure of semiconductor device with fixing device and double-sided water cooling" (CN 103367278A).

The packaging structure and the processing technology of the double-sided heat dissipation IPM hybrid module disclosed in the Chinese invention patent application publication specification are in a packaging form of upper and lower double substrates and flip chips, and an emitter of an IGBT chip and an anode of an SBD chip are connected to a lead frame through a copper-clad ceramic plate, so that bonding leads are reduced, and the reliability of the module is improved; and the nano silver interconnection layer replaces a solder layer between the chip and the substrate, so that the high-temperature characteristic of the SiC material is favorably exerted, and the longitudinal conduction capability of heat from the chip to the substrate is improved, so that the highest temperature of the IPM hybrid module is reduced, and the service life of the module is prolonged. However, this structure has the following disadvantages:

1. the structure does not consider a method for reducing the power terminal, and most of the inductance of the packaging structure comes from the power terminal:

2. the structure does not use water cooling for heat dissipation, and cannot meet the requirements of high-power devices.

The three-dimensional stacked packaging structure of the semiconductor device with the fixing device and double-sided water cooling disclosed by the patent application publication specification of the Chinese invention realizes three-dimensional packaging of the semiconductor device, has no lead bonding, reduces the line resistance and the self inductance generated by the lead bonding, adopts double-sided water cooling heat dissipation, and has small volume, large integrated power and large heat dissipation coefficient. Meanwhile, each laminated plate can package any number of semiconductor elements with the same or different sizes, the preset fixing structure effectively prevents the semiconductor elements from sliding when being impacted externally, the deformable connecting piece prevents the device from deforming even damaging the SiC semiconductor chip when being impacted, vibrated, expanded with heat and contracted with cold and the like when in work, and each laminated plate is provided with a temperature and pressure detection device for preventing the service life loss of the SiC semiconductor chip caused by improper use environment. However, this structure has the following disadvantages:

1. the structure does not consider the balanced heat dissipation of each SiC semiconductor chip;

2. the structure does not consider the consistency of the distribution of the parasitic inductances of the branches.

Disclosure of Invention

The invention aims to provide a double-sided heat dissipation SiC half-bridge module packaging structure with extremely low parasitic inductance. Aiming at the problem of large parasitic inductance in the existing packaging technology, a method that an upper DBC structure and a lower DBC structure are adopted and a direct current positive terminal and a direct current negative terminal adopt a lamination technology is provided to reduce the parasitic inductance. The double-DBC structure at the top and the bottom can realize double-layer heat dissipation, and the reliability of the module is improved. In addition, the positive terminal is connected with the bottom DBC and is provided with two welding points and two screw holes; the negative terminal is connected with the top DBC, and has two welding points and a screw hole placed in the middle, and this kind of layout structure is favorable to packaging structure symmetry, consequently obtains good effect of flow equalizing.

In order to achieve the purpose, the technical scheme provided by the invention is as follows:

a double-sided heat dissipation SiC half-bridge module packaging structure with extremely low parasitic inductance comprises a DBC, a direct current terminal, an output terminal, a SiC chip, a gasket and a driving pin;

the DBC comprises a top DBC and a bottom DBC;

the DC terminal is formed by a positive terminal and a negative terminal lamination; wherein the positive terminal is connected to the bottom DBC and has two solder joints and two screw holes for maintaining loop symmetry, the negative terminal is connected to the top DBC and has two solder joints and a central screw hole for maintaining loop symmetry, and the output terminal is connected to the bottom DBC;

the top DBC is provided with a connecting gasket connecting area and two groups of buffer gasket connecting areas, and each group of buffer gasket connecting areas comprise a plurality of buffer gasket connecting areas; wherein one set of buffer spacer connection regions are equidistant from said negative terminal and the other set of buffer spacer connection regions are equidistant from said connection spacer connection regions; two groups of chip connection regions are arranged on the bottom DBC, each group of chip connection regions comprises a plurality of chip connection regions, the distances from one group of chip connection regions to the positive terminal are equal, and the distances from the other group of chip connection regions to the output terminal are equal;

the chips are arranged on the chip connecting areas, and a driving loop of each chip is also arranged on the bottom DBC;

the gasket includes buffer spacer, connection gasket and ceramic gasket, buffer spacer welds between chip and top DBC's buffer spacer joining region, plays the effect of buffering and connection, connection gasket welds between top DBC's connection gasket joining region and bottom DBC, plays the connection effect, ceramic gasket is arranged in between positive terminal and the negative terminal, plays the effect of insulating isolation.

Furthermore, each group of chips is parallel chips, each group of parallel chips is linearly arranged, and the two groups of parallel chips are arranged in parallel.

Furthermore, the buffering cushion sheet material is made of molybdenum metal, so that the thermal stress of the chip can be relieved, and the chip is prevented from cracking.

Furthermore, the driving circuits of the chips on the bottom DBC are completely the same, and the chips and the driving circuits are connected by bonding wires.

Furthermore, the chip and the DBC, the chip and the gasket, and the gasket and the DBC are welded by vacuum reflow.

Further, the direct current terminal, the output terminal and the driving lead are connected to the DBC by metal ultrasonic bonding.

Furthermore, the packaging structure adopts a standard module design and has good expansibility.

Furthermore, the packaging structure adopts a plane packaging structure, and double-sided heat dissipation can be realized.

The invention has the advantages that: the invention can effectively reduce the voltage peak in the switching process of the device and ensure that the multi-chip parallel connection has good current-sharing property. In addition, the standardized module design enables the module to have excellent expansibility.

Drawings

FIG. 1 is a package circuit topology of the present invention;

FIG. 2 is a schematic view of the overall structure;

FIG. 3 is a schematic view of a bottom DBC structure;

FIG. 4 is a schematic top DBC structure;

FIG. 5 is a schematic view of a bond line on a bottom DBC substrate;

FIG. 6 is a schematic diagram of a buffer pad and a connection pad on the top DBC substrate;

FIG. 7 is a schematic view of bond pads and connection regions on top and bottom DBC substrates according to the invention;

FIG. 8 is a schematic diagram of a die structure bonded to a die attach region;

fig. 9 is a side schematic view of the overall structure.

Detailed Description

The following describes an embodiment of the present invention with reference to the drawings.

Fig. 1 is a circuit diagram of the package structure of the present invention. In the figure, P is a positive electrode, N is a negative electrode, Output is an alternating current Output port, the circuit has six SiC semiconductor chips, and the SiC semiconductor chips connected in parallel increase the total current, so that the integratable power of the packaging structure is higher.

2-4, the main structure of the double-sided heat-dissipating SiC half-bridge module package structure with very low parasitic inductance of the present invention includes a top DBC1, a bottom DBC2, a positive terminal 3, a negative terminal 4, an output terminal 5, six SiC chips 7, six buffer pads 9, four connection pads 8, and six sets of driving pins 6, where one set of driving pins has two driving pins 6, one is connected to the driving source and the other is connected to the driving gate. The positive terminal 3 and the negative terminal 4 form a direct current terminal through lamination, and the lamination is beneficial to reducing parasitic inductance. The design of the positive terminal 3 with two welds and two screw holes and the negative terminal 4 with two welds and one centered screw hole is advantageous to maintain loop symmetry. The buffer gasket 9 is welded between the SiC semiconductor chip 7 and the top DBC1 and plays a role in buffering, the material used by the buffer gasket 9 is molybdenum, so that the thermal stress of the chip can be relieved, and the chip is prevented from cracking; the connecting pad 8 is welded between the top DBC1 and the bottom DBC2 for connection.

Fig. 2 is a view showing the entire structure of the package, fig. 3 and 4 are a lower half and an upper half, respectively, of the package after the package is disassembled, and fig. 7 is a view showing a top portion DBC1 and a bottom portion DBC2 of the package without the positive terminal 3, the negative terminal 4, the output terminal 5, and the driving pins 6. Fig. 8 shows a SiC semiconductor chip 7 including a source 16, a gate 17, and a drain 18, the source 16 and the drain 18 of the chip 7 being soldered to the buffer pad 9 on the top DBC1 and the die attach region 14 on the bottom DBC2, respectively, and a set of driving pins 6 of the driving circuit being connected to the source 16 and the gate 17 of the SiC semiconductor chip 7, respectively.

Starting with the top DBC1 and bottom DBC2 of fig. 7 without any mounted components, it is first bonded to the drive pins 6. The driving guide pin 6 is L-shaped, the bonding part of the driving guide pin and the bottom DBC2 is 5.27mm long and 0.5mm thick, and the lead of the driving guide pin and the bottom DBC2 metallization layer are bonded at an atomic level through a metal ultrasonic bonding technology. Likewise, the bonding between the positive terminal 3, the output terminal 5, the negative terminal 4 and the bottom DBC2 and top DBC1 terminal pads 12 is accomplished using metal ultrasonic bonding techniques. It is noted that after the positive terminal 3 and the bottom DBC2 are welded together, a ceramic spacer 11 is placed over the positive terminal 3 to provide insulating insulation between the positive terminal 3 and the negative terminal 4, as shown in fig. 5.

Next, it is necessary to solder the SiC semiconductor chip 7 to the die attach region 14 on the bottom DBC2 by a reflow process, and the source 15 and the gate 16 of the SiC semiconductor chip 7 and the drive pins 6 of the drive circuit are connected together by wire bonding after the soldering is completed. On the top DBC1, six bumper pads 9 and two connection pads 8 need to be soldered to the bumper pad connection region 13 and the connection pad connection region 15 on the top DBC1, respectively. The components on both the top DBC1 and the bottom DBC2 have been welded, and then need to be welded together, as shown in FIG. 9. And after the top DBC1 and the bottom DBC2 are coated with soldering paste and aligned, the top DBC1 and the bottom DBC2 are welded together by secondary reflow soldering, and the whole low-parasitic-inductance double-side heat dissipation SiC half-bridge module structure is packaged.

Claims

1. A double-sided heat dissipation SiC half-bridge module packaging structure with extremely low parasitic inductance is characterized in that the packaging structure comprises a DBC, a direct current terminal, an output terminal, a SiC chip, a gasket and a driving pin;

the DBC comprises a top DBC and a bottom DBC;

the DC terminal is formed by a positive terminal and a negative terminal lamination; the positive terminal is connected with the bottom DBC, the positive terminal is provided with two welding points and two screw holes, the negative terminal is connected with the top DBC, the negative terminal is provided with two welding points and a middle screw hole, and the output terminal is connected with the bottom DBC;

the gasket includes buffer gasket, connection gasket and ceramic gasket, the buffer gasket welds between chip and top DBC's buffer gasket union region, the connection gasket welds between top DBC's connection gasket union region and bottom DBC, the ceramic gasket is arranged in between positive terminal and the negative terminal.

2. The SiC half-bridge module package structure with double-sided heat dissipation and extremely low parasitic inductance of claim 1, wherein each group of chips is parallel chips, each group of parallel chips is arranged in a straight line, and two groups of parallel chips are arranged in parallel.

3. The SiC half-bridge module package with very low parasitic inductance of claim 1, wherein the buffer pad material is molybdenum metal.

4. The SiC half-bridge module package structure with very low parasitic inductance of claim 1, wherein the driving loops of the chips on the bottom DBC are identical, and the chips and the driving loops are connected by bonding wires.

5. The SiC half-bridge module package structure with double-sided heat dissipation and extremely low parasitic inductance of claim 1, wherein the bonding of the chip to the DBC, the chip to the gasket, and the gasket to the DBC is performed by vacuum reflow soldering.

6. The SiC half-bridge module package with double side heat dissipation and extremely low parasitic inductance of claim 1, wherein the dc terminals, the output terminals and the driving pins are connected to the DBC by metal ultrasonic bonding.

7. The SiC half-bridge module package with very low parasitic inductance of claim 1, in which the package is of a standard module design.

8. The SiC half-bridge module package structure with double-sided heat dissipation and extremely low parasitic inductance as claimed in claim 1, wherein the package structure is a planar package structure, and double-sided heat dissipation can be achieved.