WO2021223694A1

WO2021223694A1 - Power semiconductor device

Info

Publication number: WO2021223694A1
Application number: PCT/CN2021/091813
Authority: WO
Inventors: 晏新海
Original assignee: Yan Xinhai
Priority date: 2020-05-06
Filing date: 2021-05-04
Publication date: 2021-11-11
Also published as: WO2021223695A1; CN111540723A

Abstract

Disclosed is a power semiconductor device. The power semiconductor device comprises: a shell, wherein the shell is provided with a first pin, a second pin and a third pin in an extending manner; a packaging base plate, wherein the packaging base plate is integrally arranged with the shell; and a power chip, wherein the power chip has a front face and a back face, the front face of the power chip is attached to the packaging base plate, the front face of the power chip is provided with a first electrode connected to the first pin and a second electrode connected to the packaging base plate, the second pin is connected to the packaging base plate, and the back face of the power chip is provided with a third electrode connected to the third pin. According to the solution of the present invention, the thermal resistance of a system can be greatly reduced, the heat dissipation capability of the system can be improved, the working reliability of the power semiconductor device is improved, and the process cost is reduced.

Description

A power semiconductor device

Technical field

The present invention relates to the technical field of power devices, in particular to a power semiconductor device.

Background technique

At present, in many power device application scenarios, power semiconductor devices such as bipolar transistors BJTs, field effect transistors MOSFETs, IGBT monotubes, IGBT modules, and IPM modules are usually applied to the output of the system. As a power semiconductor device for power output, the NPN BJT emitter E and the source S of the N-channel MOS tube are connected to the ground, and the PNP type BJT emitter E and the source S of the P-channel MOS tube are connected to the power supply. The potential is fixed, the collector C or drain D is connected to the load, and the potential of the load is variable.

In traditional packaging processes, metal packaging, plastic packaging, module packaging, etc., all weld the collector C or the drain D to the package bottom plate; for high-power semiconductor devices, due to the large output power and heat generation, external heat dissipation is required. The chip dissipates heat from its power semiconductors. Sometimes there are multiple power devices sharing the heat sink. When the collector C or drain D is connected to the load, because its potential is variable, in order to be electrically isolated from the system, it is necessary to add mica between the collector C or drain D and the external heat sink. Insulating materials, such as sheets (or ceramic layers), act as electrical isolation.

However, the mica sheet (or ceramic layer) has good electrical insulation performance, but poor thermal conductivity. After electrical isolation, the heat dissipation capacity of the system is greatly reduced; for the application scenarios of low voltage or a single device with an external heat sink, such as collector C or Drain D is directly connected to an external heat sink, which will increase the capacitance effect and affect the frequency characteristics of the system.

Summary of the invention

The main purpose of the present invention is to provide a power semiconductor device, which aims to improve the working reliability of the power semiconductor device and improve the current carrying capacity of the system.

In order to achieve the above objective, the power semiconductor device proposed by the present invention includes:

A housing, on which a first pin, a second pin and a third pin are protrudingly provided;

A package bottom plate, the package bottom plate and the housing are integrally arranged;

A power chip, the power chip has a front surface and a back surface, the front surface of the power chip is attached to the package bottom plate, and the front surface of the power chip has a first electrode connected to the first pin and connected to the package The second electrode of the bottom plate, the second pin is connected to the package bottom plate, and the back of the power chip has a third electrode connected to the third pin.

Optionally, the first electrode is the base or gate of the power chip, the second electrode is the emitter or source of the power chip, and the third electrode is the collector of the power chip. Electrode or drain.

Optionally, the second pin is connected to the emitter or source of the power chip, and the third pin is connected to the collector or drain of the power chip.

Optionally, the base or gate of the power chip is soldered to the first pin, the emitter or source of the power chip is soldered to the package bottom plate, and the power chip's The collector or drain is connected to the third pin through a connector.

Optionally, the connecting member between the collector or drain of the power chip and the third pin is a plurality of conductive wires or conductive rows.

Optionally, the base or gate of the power chip is connected to the first pin through a connector, the emitter or source of the power chip is soldered to the package bottom plate, and the power chip The collector or drain is connected to the third pin connection end through a connector.

Optionally, the number of connections between the base or gate of the power chip and the first pin is one conductive wire, and the collector or drain of the power chip is connected to the third lead. The connecting piece between the feet is a plurality of conductive wires or conductive rows.

Optionally, the power semiconductor device is a bipolar transistor BJT, a field effect transistor MOSFET, an IGBT monotube, an IGBT module or an IPM module.

Beneficial effect

Compared with the prior art, the technical solution of the present invention has the following remarkable progress and technical effects:

1. The internal resistance of the chip of the present invention is mainly concentrated in the epitaxial layer. The thickness of the substrate is generally one or two hundred microns, and the thickness of the epitaxial layer is several to tens of microns. The heat is concentrated in the epitaxial layer, and the heat dissipation path from the source is short, which reduces the heat of the chip. Hinder.

2. The internal resistance of all MOS devices has a positive temperature change. The higher the temperature, the greater the internal resistance. The solution of the present invention improves heat dissipation and reduces the operating temperature, thereby indirectly reducing the internal resistance of the chip. Internal resistance is reduced, heat generation is reduced, and efficiency is improved.

3. In the high-power application scenario, the source of the present invention has low potential and can be directly connected to the heat sink. The electrical isolation layer usually has poor heat conduction, accounting for about 60% of the thermal resistance of the system. Mica, ceramic, or plastic electrical isolation layers are omitted. Will greatly reduce the thermal resistance of the system, that is, greatly improve the heat dissipation capacity of the system.

4. With the same chip size, the heat dissipation improvement of the solution of the present invention can improve the working efficiency, device reliability, and service life of the device; or meet the requirements of the same working conditions, reduce the chip area, and reduce the chip cost; or both, reduce the cost and At the same time, product performance is improved to meet a wider range of requirements.

5. In the application of switching power supply, MOS tubes generally work at a frequency of 20-200K. Electromagnetic radiation is also a key parameter. The energy of electromagnetic radiation is proportional to the square of the voltage. The poles are connected to the package shell, which greatly reduces the electromagnetic radiation of the package shell and also improves the efficiency of the system.

Description of the drawings

1a-1c are schematic cross-sectional views of the device structure of an embodiment of the existing power semiconductor device;

FIG. 1d is a top view of the device structure of an embodiment of the existing power semiconductor device;

2a-2c are schematic cross-sectional views of the device structure of the first embodiment of the power semiconductor device of the present invention;

2d is a top view of the device structure of the first embodiment of the power semiconductor device of the present invention;

3a-3c are schematic cross-sectional views of the device structure of the second embodiment of the power semiconductor device of the present invention;

3d is a top view of the device structure of the second embodiment of the power semiconductor device of the present invention;

4a-4c are schematic cross-sectional views of the device structure of the third embodiment of the power semiconductor device of the present invention;

4d is a top view of the device structure of the third embodiment of the power semiconductor device of the present invention;

5 is a schematic cross-sectional view of an embodiment of an electrode structure of a power chip in a power semiconductor device of the present invention;

Fig. 6 is a schematic cross-sectional view of solder welding of a power chip in a power semiconductor device of the present invention.

Attached icon number description:

标号Label	名称 name	标号Label		名称name
1010	第一引脚 First pin	6060	连接件 Connector
2020	第二引脚 Second pin	5151	基极或栅极Base or gate
3030	第三引脚 Third pin	5252	发射极或源极Emitter or source
4040	封装底板 Package bottom plate	5353	集电极或漏极Collector or drain
5050	功率芯片Power chip	To	To

Detailed ways

The realization of the objectives, functional characteristics and advantages of the present invention will be combined with the embodiments, and will be further described below with reference to the accompanying drawings.

In the traditional packaging process, the packaging of power semiconductor devices is shown in Figures 1a-1d. For metal packaging, plastic packaging, module packaging, etc., the collector C or drain D is welded to the package bottom plate, and the base or gate The emitter or source is connected to the protruding pins of the power semiconductor for high-power semiconductor devices through a connecting wire; for high-power semiconductor devices, due to the large output power and heat generation, an external heat sink needs to be added to dissipate the power semiconductor. Sometimes there are multiple power devices sharing the heat sink. When the collector C or drain D is connected to the load, because its potential is variable, in order to be electrically isolated from the system, it is necessary to add mica between the collector C or drain D and the external heat sink. Insulating materials, such as sheets (or ceramic layers), act as electrical isolation.

According to an embodiment of the present invention, as shown in FIGS. 2a-2d and FIGS. 3a-3d, the power semiconductor device includes:

A shell, on which a first pin 10, a second pin 20 and a third pin 30 are protrudingly provided;

A package bottom plate 40, the package bottom plate 40 is integrally arranged with the housing;

The power chip 50 has a front surface and a back surface. The front surface of the power chip 50 is attached to the package bottom plate 40. The front surface of the power chip 50 has a first pin 10 connected to the first pin 10. The electrode and the second electrode connected to the package bottom plate 40, the second pin 20 is connected to the package bottom plate 40, and the back of the power chip 50 has a third electrode connected to the third pin 30.

The first electrode is the base or gate of the power chip, the second electrode is the emitter or source of the power chip, and the third electrode is the collector or drain of the power chip. The second pin 20 is connected to the emitter or source of the power chip, and the third pin 30 is connected to the collector or drain of the power chip.

As shown in FIG. 5, the front of the power chip 50 has a base or gate 51 and an emitter or source 52, and the back of the power chip 50 has a collector or drain 53. By turning the power chip 50 upside down, the emitter or source 52 on the front of the power chip 50 is welded to the package bottom plate 40, and connected to the second pin 20 of the power semiconductor device housing, and the base or gate on the front of the power chip 50 is connected. 51 is connected to the first pin 10 of the power semiconductor device housing, and the collector or drain electrode 53 on the back of the power chip 50 is connected to the third pin 30 of the power semiconductor device housing. It can be understood that the first pin 10 of the power semiconductor device housing is the base or gate of the power semiconductor device, and the second pin 20 of the power semiconductor device housing is the emitter or source of the power semiconductor device. The third pin 30 of the housing is the collector or drain of the power semiconductor device. With this solution, the power chip 50 is set upside down. In high-power semiconductor driving applications, the emitter or source is grounded, and the flip-chip package bottom plate 40 can be grounded, so that the power chip 50 can be directly cooled without the need for additional mica The electrical isolation layer (or ceramic layer, etc.) greatly reduces the system thermal resistance of the power semiconductor device and improves the heat dissipation capacity of the system. At the same time, due to the reduced thermal resistance, the operating temperature of the power chip 50 can be improved, and the 50 load of the power chip can be greatly increased. Flow capacity.

Specifically, the current power semiconductor devices weld the collector or drain of the power chip 50 to the package bottom plate 40. When the power is low, heat can be directly dissipated through the bottom plate and the package shell; when the power is high, the bottom plate is connected to a heat sink, and heat dissipation is The chip transfers heat to the environment for heat dissipation; in the application of high-power devices, the heat dissipation capacity of the overall heat dissipation system is improved by adjusting the structure of the heat sink. For this solution, the thermal resistance of the collector or drain terminal heat dissipation mode is: total thermal resistance = power chip 50 resistance + solder resistance + package base 40 resistance + mica sheet or ceramic layer resistance + heat sink resistance ；

The thermal resistance of the emitter or the source for heat dissipation is: total thermal resistance = 50 resistance of the power chip + solder resistance + 40 resistance of the package base plate + radiator resistance, the emitter or source is grounded, no electrical isolation is required, and mica is eliminated Therefore, the thermal resistance generated by the mica sheet, ceramic layer or other insulating materials is reduced, and the heat dissipation capacity of the system is improved.

In this embodiment, the second pin 20 is integrally provided with the package bottom plate 40.

The power semiconductor device of the technical solution of the present invention has a first pin 10, a second pin 20, and a third pin 30 protruding from the housing. The power chip 50 has a front side and a back side, and the front side of the power chip 50 is attached On the package bottom plate 40; the first electrode on the front side of the power chip 50 is connected to the first pin 10 on the housing, the second electrode on the front side of the power chip 50 is connected to the package bottom plate 40, and the second pin 20 on the housing is connected to the package The bottom plate 40 and the third electrode on the back of the power chip 50 are connected to the third pin 30 on the housing. It solves the problem that the third electrode on the back of the power semiconductor device is welded to the package bottom plate 40. In the application scenario of an external heat sink, it is necessary to increase the electrical isolation insulating material, which increases the thermal resistance of the device and improves the working reliability of the power semiconductor device. , Improve the current carrying capacity of the system.

As shown in FIGS. 2a-2d, the base or gate of the power chip 50 is soldered to the first pin 10, and the emitter or source of the power chip 50 is soldered to the package bottom plate. At 40, the collector or drain of the power chip 50 is connected to the third pin 30 through a connector 60.

In this embodiment, the power chip 50 is turned upside down, and the emitter or source on the front side of the power chip 50 is soldered to the package bottom plate 40, and connected to the second pin 20 of the power semiconductor device housing. The base or gate is soldered to the first pin 10 of the power semiconductor device housing, and the collector or drain on the back of the power chip 50 is connected to the third pin 30 of the power semiconductor device housing through a connector 60. With this solution, the power chip 50 is set upside down. In high-power semiconductor driving applications, the emitter or source is grounded, and the flip-chip package bottom plate 40 can be grounded, so that the power chip 50 can be directly cooled without the need for additional mica The electrical isolation layer (or ceramic layer, etc.) greatly reduces the thermal resistance of the system with power semiconductor devices and improves the heat dissipation capacity of the system. At the same time, due to the reduced thermal resistance, the operating temperature of the power chip 50 can be improved, and the power chip 50 can be greatly increased. Current carrying capacity.

In this embodiment, the connecting member between the collector or drain of the power chip 50 and the third pin 30 is a plurality of conductive wires or conductive rows. It can be understood that the conductive wires or conductive rows are here. The number can be 2, 3, 4, etc., and there is no limitation here, so as to improve the current-carrying capacity of the collector or drain of the power semiconductor device.

In an embodiment, as shown in FIGS. 3a-3d, the base or gate of the power chip 50 is connected to the first pin 10 by a connector 60, and the emitter or source of the power chip 50 is connected by solder Soldered on the package bottom plate 40, the collector or drain of the power chip 50 and the connection end of the third pin 30 are connected by a connector 60.

In this embodiment, the power chip 50 is turned upside down, and the emitter or source on the front side of the power chip 50 is soldered to the package bottom plate 40, and connected to the second pin 20 of the power semiconductor device housing. The base or gate is connected to the first pin 10 of the power semiconductor device housing through a connector 60, and the collector or drain on the back of the power chip 50 is connected to the third pin 30 of the power semiconductor device housing through the connector 60. With this solution, the power chip 50 is set upside down. In high-power semiconductor driving applications, the emitter or source is grounded, and the flip-chip package bottom plate 40 can be grounded, so that the power chip 50 can be directly cooled without the need for additional mica The electrical isolation layer (or ceramic layer, etc.) greatly reduces the thermal resistance of the system with power semiconductor devices and improves the heat dissipation capacity of the system. At the same time, due to the reduced thermal resistance, the operating temperature of the power chip 50 can be improved, and the power chip 50 can be greatly increased. Current carrying capacity.

In this embodiment, the number of connections between the base or gate of the power chip 50 and the first pin 10 is one conductive wire, and the collector or drain of the power chip 50 is connected to the The connecting member between the third pins 30 is a plurality of conductive wires or conductive rows. It is understandable that the number of conductive wires or conductive rows here can be 2, 3, 4, etc., which is not done here. Limit, so as to improve the current-carrying capacity of the collector or drain in the power semiconductor device.

In an optional embodiment, the first electrode is the base or gate of the power chip, the second electrode is the emitter or source of the power chip, and the third electrode is the The collector or drain of the power chip. The second pin 20 is connected to the emitter or source of the power chip, and the third pin 30 is connected to the collector or drain of the power chip.

It should be noted that, as shown in FIGS. 4a-4d, the connection between the third pin 30 and the collector or drain of the power chip can be through aluminum, copper, or other metal bars, that is, the connection here. It is aluminum row or other metal row.

In the above embodiment, the second pin 20 is connected to the emitter or the source, the third pin 30 is connected to the collector or the drain, and the first pin 10 and the second pin 20 are not in specific positions. The relationship is arranged, and the positions of the second pin number 20 and the third pin 30 are not limited here.

Based on the above embodiment, the package bottom plate 40 can be but not limited to a copper bottom plate; the solder soldering can be, but not limited to, lead-free solder, lead-tin solder, or other specific solder; the connecting member 60 is connected by ultrasonic Welding connection; the power semiconductor device can be but not limited to bipolar transistor BJT, field effect transistor MOSFET, IGBT single tube, IGBT module, IPM module, and other SIC power devices. It can be understood that the connecting member 60 can be, but not limited to, a conductive metal connecting piece or a connecting wire, which is selected according to actual application conditions.

In the above-mentioned embodiment, as shown in FIG. 6 is a schematic diagram of the welding of the power chip 50 and the package bottom plate 40, and the pins, and the packaging steps of the power semiconductor are as follows:

The first step: the pretreatment of the metal layer of the front electrode of the power chip 50 is connected, and then the solder layer is added;

Step 2: Pre-processing the corresponding positions of the package bottom plate 40 and the protruding pins of the power semiconductor, adding a solder layer;

The third step: glue the power chip 50 to the corresponding position of the package bottom plate 40 and the power semiconductor pin by an automatic chip mounter, and fix it;

Step 4: Heat and melt the solder layer to solder the power chip 50, the package bottom plate 40, and the pins. After cooling, the power chip 50, the package bottom plate 40, and the pins are connected to each other;

The fifth step: the pre-processing of the back of the power chip 50, which is connected by wire bonding through the above-mentioned soldering method or through the connector 60.

The technical solution of the present invention not only greatly reduces the thermal resistance of the system, that is, greatly improves the heat dissipation capacity of the system, but also reduces the process cost. Compared with the existing traditional process of drain welding, source and gate wire bonding (high power is multiple aluminum wires); the improved process of the present invention is source and gate welding, drain wire bonding (high power Aluminum tape). The cost of wire bonding process is higher than that of welding, and the cost of wire bonding process is better than that of multiple aluminum wires. Traditional processes such as packaging materials and improved processes are basically unchanged, so the process cost of the present invention will be better than traditional processes.

The foregoing descriptions are only optional embodiments of the present invention, and do not limit the scope of the present invention. Any equivalent structural transformations or direct/indirect conversions made by using the contents of the description and drawings of the present invention are based on the concept of the present invention. Applications in other related technical fields are included in the scope of patent protection of the present invention.

Claims

A power semiconductor device, characterized in that it comprises:

A housing, on which a first pin, a second pin and a third pin are protrudingly provided;

A package bottom plate, the package bottom plate and the housing are integrally arranged;

A power chip, the power chip has a front surface and a back surface, the front surface of the power chip is attached to the package bottom plate, and the front surface of the power chip has a first electrode connected to the first pin and connected to the package The second electrode of the bottom plate, the second pin is connected to the package bottom plate, and the back of the power chip has a third electrode connected to the third pin.
The power semiconductor device of claim 1, wherein the first electrode is a base or gate of the power chip, and the second electrode is an emitter or source of the power chip, so The third electrode is the collector or drain of the power chip.
The power semiconductor device of claim 2, wherein the second pin is connected to the emitter or source of the power chip, and the third pin is connected to the collector or drain of the power chip.极连接。 Pole connection.
The power semiconductor device according to claim 3, wherein the base or gate of the power chip and the first pin are soldered, and the emitter or source of the power chip is soldered to On the package bottom plate, the collector or drain of the power chip is connected to the third pin through a connector.
4. The power semiconductor device according to claim 4, wherein the connecting member between the collector or drain of the power chip and the third pin is a plurality of conductive wires or conductive rows.
The power semiconductor device according to claim 3, wherein the base or gate of the power chip is connected to the first pin by a connector, and the emitter or source of the power chip is soldered by soldering. On the package bottom plate, the collector or drain of the power chip and the third pin connection end are connected by a connector.
The power semiconductor device according to claim 6, wherein the number of the connecting member between the base or gate of the power chip and the first pin is 1 conductive wire, and the power chip The connecting member between the collector or drain and the third pin is a plurality of conductive wires or conductive rows.
7. The power semiconductor device according to any one of claims 1 to 7, wherein the power semiconductor device is a bipolar transistor BJT, a field effect transistor MOSFET, an IGBT monotube, an IGBT module or an IPM module.