CN118248713A - Enhancement type GaN HEMT device integrating P-N junction - Google Patents
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Abstract
The invention discloses an enhanced GaN HEMT device integrating a P-N junction. The enhancement-mode GaN HEMT device comprises an epitaxial structure and a source electrode, a drain electrode and a grid electrode, wherein the source electrode, the drain electrode and the grid electrode are matched with the epitaxial structure, the epitaxial structure comprises a channel layer, a first barrier layer, a second barrier layer and a P-N reverse stacking layer, the first barrier layer is arranged on the channel layer in a stacking mode along a selected direction, the P-N reverse stacking layer is arranged on a grid electrode area of the first barrier layer in a stacking mode along the selected direction, the second barrier layer is arranged on the first barrier layer and the P-N reverse stacking layer in a stacking mode along the selected direction, the source electrode and the drain electrode are arranged on the second barrier layer and form ohmic contact with the second barrier layer, and the grid electrode is arranged on the P-N reverse stacking layer and forms Schottky contact with the P-N reverse stacking layer. The invention provides an effective method for manufacturing the enhanced HEMT device, and the manufactured GaN HEMT device has higher gate breakdown voltage.
Description
Technical Field
The invention particularly relates to an enhanced GaN HEMT device integrated with a P-N junction, and belongs to the technical field of third-generation semiconductor devices.
Background
Gallium nitride high electron mobility transistors (GaN HEMTs) are a type of semiconductor device used for high frequency high power applications. Compared to conventional silicon (Si) and gallium arsenide (GaAs) devices, gaN HEMTs have higher electron mobility and larger energy gap, making them excellent in high frequency applications. However, in some application scenarios, a fast switching function is required that enables high power, which requires the use of enhanced devices.
Currently, the only method used for commercial fabrication is to grow a p-GaN cap layer on the gate region of the AlGaN surface for depleting the two-dimensional electron gas of the GaN channel surface below the gate region. However, high-concentration doping of P-type is difficult to achieve, and it is common to increase the thickness of the P-GaN cap layer to deplete the two-dimensional electron gas between GaN/AlGaN. This has a problem in that an excessively thick P-GaN cap layer forms a large space between the gate electrode and the two-dimensional electron gas, resulting in that the gate electrode electric field cannot effectively affect the two-dimensional electron gas. As a result, the regulation effect of the gate on the two-dimensional electron gas is poor, a sufficiently good drain operating current is difficult to realize, and a large optimization space exists for the gate breakdown voltage and the gate reliability of the P-GaN cap layer structure.
Due to the existence of GaN/AlGaN polarization effect, a depletion type device is naturally formed, and the depletion type device is conducted under zero bias voltage, so that certain static power consumption is caused, particularly under a high-temperature environment. In practice depletion mode devices require an appropriate bias circuit to ensure proper operation, and the design of the bias circuit is often complex.
The threshold voltage of the existing enhanced GaN HEMT device is relatively low, and the small threshold voltage causes high leakage current of the HEMT device in the off state. And the HEMT device is easier to accidentally turn on under the condition that conduction is not needed due to the small threshold voltage. A smaller saturated drain current may limit the output power and frequency response of the device. The HEMT device gate breakdown voltage is too small, meaning that when the applied voltage between the gate and source exceeds the breakdown voltage, device damage may result. A smaller breakdown voltage may also lead to reduced device reliability, and in practical applications voltage spikes, electromagnetic interference, or unstable voltage conditions may be encountered, which may lead to gate voltages exceeding the breakdown voltage, leading to reduced device lifetime or irreparable damage.
Disclosure of Invention
The invention mainly aims to provide an enhanced GaN HEMT device integrated with a P-N junction, which has the advantages that the threshold voltage of the device is larger, the saturation working current of a drain electrode is higher, and the breakdown voltage of a grid electrode is larger while the enhanced GaN HEMT device is realized, so that the defects in the prior art are overcome.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention comprises the following steps:
The invention provides an enhanced GaN HEMT device integrating a P-N junction, which comprises an epitaxial structure, a source electrode, a drain electrode and a grid electrode which are matched with the epitaxial structure,
The epitaxial structure comprises a channel layer, a first barrier layer, a second barrier layer and a P-N reverse stacking layer, wherein the first barrier layer is stacked on the channel layer along the selected direction, the P-N reverse stacking layer is stacked on a grid region of the first barrier layer along the selected direction, the second barrier layer is stacked on the first barrier layer and the P-N reverse stacking layer along the selected direction, the source electrode and the drain electrode are arranged on the second barrier layer and form ohmic contact with the second barrier layer, and the grid electrode is arranged on the P-N reverse stacking layer and forms Schottky contact with the P-N reverse stacking layer.
Further, the P-N reverse stacked layer includes a P-type semiconductor layer and an N-type semiconductor layer stacked in order along a selected direction, the P-type semiconductor layer is disposed on the first barrier layer, and the gate is disposed on the N-type semiconductor layer and forms a schottky contact with the N-type semiconductor layer. When the gate is forward biased, the p-n junction is reverse biased, and can withstand higher voltages at the same peak electric field because the depletion region extends to both the n-side and the p-side. If the n-type and p-type semiconductors are inverted, the depletion region narrows when the gate is forward biased, and the device can only withstand lower voltages at the same peak electric field.
Further, the p-type semiconductor layer includes a p-GaN layer, and the n-type semiconductor layer includes an n-GaN layer.
Further, the doping concentration of the p-type impurity in the p-type semiconductor layer is greater than the doping concentration of the n-type impurity in the n-type semiconductor layer.
Further, the doping concentration of the p-type impurity in the p-type semiconductor layer is 10 19cm-3～1020cm-3, and the doping concentration of the n-type impurity in the n-type semiconductor layer is 10 18cm-3～1019cm-3.
Further, the thickness of the p-type semiconductor layer is greater than the thickness of the n-type semiconductor layer.
Further, the thickness of the p-type semiconductor layer is 80nm to 130nm, and the thickness of the n-type semiconductor layer is 20nm to 40nm.
Further, the thickness of the first barrier layer is smaller than the thickness of the second barrier layer. Specifically, the thickness of the first barrier layer is thin to make the threshold voltage of the device larger, but if the thickness of the first barrier layer is reduced uniformly, the working current of the device becomes smaller, so that the device is added with a second barrier layer, and the working current of the device can be improved due to the larger thickness of the second barrier layer.
Further, the ratio of the thickness of the first barrier layer to the thickness of the second barrier layer is 2:3, and further, the thickness of the first barrier layer is 10nm, and the thickness of the second barrier layer is 15nm.
Further, the first barrier layer and the second barrier layer are made of a group III nitride material containing Al, and the first barrier layer and the second barrier layer have the same Al content.
Further, the content of the Al component in the first barrier layer and the second barrier layer is 0.1 to 0.5. In HEMT devices, the composition of aluminum is typically controlled between 0.1 and 0.5, and too high an aluminum composition may result in too high a resistance and thus poor electrical performance.
Further, the gate region of the second barrier layer is further provided with a gate groove structure, the groove bottom of the gate groove structure is located on the surface of the n-type semiconductor layer, and a part of the gate is arranged in the gate groove structure and is in electrical contact with the n-type semiconductor layer.
Further, the channel layer comprises a GaN layer, and the first barrier layer and the second barrier layer comprise AlGaN.
Further, the thickness of the channel layer is 50 nm-400 nm.
Further, the epitaxial structure further comprises a substrate and a buffer layer, wherein the buffer layer is arranged on the substrate in a lamination mode along the selected direction, and the channel layer is arranged on the buffer layer in a lamination mode along the selected direction.
Further, the material of the buffer layer comprises GaN.
Further, the thickness of the buffer layer is 2000 nm-4000 nm.
Further, the material of the substrate includes any one of SiC, si, gaN, but is not limited thereto.
Compared with the prior art, the invention has the advantages that:
According to the enhanced GaN HEMT device integrating the P-N junction, the P-N junction is used for replacing a traditional P-GaN cap layer, an effective method is provided for manufacturing the enhanced HEMT device, and the grid breakdown voltage of the manufactured GaN HEMT device is higher;
according to the enhanced GaN HEMT device integrated with the P-N junction, the problem of low saturated drain current caused by a low Al component thin AlGaN barrier layer is solved by adopting the composite barrier layer, so that the threshold voltage of the enhanced device is larger, and the working current is higher.
Drawings
Fig. 1 is a schematic structural diagram of an enhanced GaN HEMT device with integrated P-N junction according to an exemplary embodiment of the present invention;
fig. 2 is a schematic diagram of a manufacturing flow of an enhanced GaN HEMT device integrated with a P-N junction according to an exemplary embodiment of the present invention;
Fig. 3 is a transfer characteristic curve of an enhanced GaN HEMT device integrated with a P-N junction provided in embodiment 1 of the present invention;
Fig. 4 is an output characteristic curve of an enhanced GaN HEMT device integrated with a P-N junction provided in embodiment 1 of the present invention;
Fig. 5 is a gate breakdown voltage curve of an enhanced GaN HEMT device integrated with a P-N junction provided in embodiment 1 of the present invention.
Detailed Description
In view of the shortcomings in the prior art, the inventor of the present invention has long studied and practiced in a large number of ways to propose the technical scheme of the present invention. The technical scheme, implementation process and principle thereof, etc. will be further explained with reference to the drawings and specific embodiments, and unless otherwise indicated, the epitaxial growth apparatus and process thereof adopted by the embodiments of the present invention are known to those skilled in the art.
Referring to fig. 1, an enhanced GaN HEMT device with integrated P-N junction includes an epitaxial structure, and a source electrode 8, a drain electrode 9 and a gate electrode 10 matched with the epitaxial structure,
The epitaxial structure comprises a substrate 1, a GaN buffer layer 2, a GaN channel layer 3, a first AlGaN barrier layer 4, a second AlGaN barrier layer 5, a p-GaN layer 6, an n-GaN layer 7,p-GaN layer 6 and an n-GaN layer 7 which are sequentially arranged from bottom to top, wherein the first AlGaN barrier layer 4 and the second AlGaN barrier layer 4 are sequentially stacked, the second AlGaN barrier layer 5 is stacked on the first AlGaN barrier layer 4 and the n-GaN layer 7 and covers the side walls of the p-GaN layer 6 and the n-GaN layer 7, a grid groove structure is arranged in a grid electrode region of the second AlGaN barrier layer 5, the bottom of the grid electrode 10 is arranged in the grid groove structure and forms Schottky contact with the n-GaN layer 7, and a source electrode 8 and a drain electrode 9 are arranged in an ohmic region of the second AlGaN barrier layer 5 and form ohmic contact with the second AlGaN barrier layer 5.
Specifically, the thickness of the first AlGaN barrier layer 4 is smaller than the thickness of the second AlGaN barrier layer 5, more specifically, the thickness of the first AlGaN barrier layer 4 is about 10nm, the thickness of the second AlGaN barrier layer 5 is about 15nm, specifically, the content of Al component in the first A1GaN barrier layer 4 and the second AlGaN barrier layer 5 is the same, and more specifically, the content of Al component in the first AlGaN barrier layer 4 and the second AlGaN barrier layer 5 is 0.1 to 0.5.
Specifically, the P-GaN layer 6 and the N-GaN layer 7 form a P-N junction structure, the Mg doping concentration in the P-GaN layer 6 is greater than the Si doping concentration in the N-GaN layer 7, more specifically, the Mg doping concentration in the P-GaN layer 6 is 10 19cm-3～1020cm-3, and the Si doping concentration in the N-GaN layer 7 is 10 18cm-3～1019cm-3. Specifically, the thickness of the p-GaN layer 6 is greater than the thickness of the n-GaN layer 7, more specifically, the thickness of the p-GaN layer 6 is 80nm to 130nm, and the thickness of the n-GaN layer 7 is 20nm to 40nm. More specifically, the p-GaN layer 6 functions to realize enhancement of the device, and if the doping concentration of the p-GaN layer 6 is too low or the thickness is thin, the device may be formed as a depletion type device.
In particular, it was found by testing that when the gate is forward biased, the p-n junction is reverse biased, and because the depletion region extends to both the n-side and the p-side, a higher voltage can be sustained at the same peak electric field, and if the p-GaN layer 6, the n-GaN layer 7 are inverted, the depletion region narrows when the gate is forward biased, and the device can only sustain a lower voltage at the same peak electric field.
Specifically, the thickness of the GaN channel layer 3 is 50nm to 400nm, and the thickness of the GaN buffer layer 2 is 2000nm to 4000nm.
Specifically, the material of the substrate 1 includes any one of SiC, si, gaN, and the thickness of the substrate 1 is about 10000nm.
Specifically, the electrode materials used for the source electrode 8, the drain electrode 9 and the gate electrode 9 are one or an alloy of two or more metals Ni, al, au, pt, ti.
In a more typical embodiment, referring to fig. 2, a method for fabricating an integrated P-N junction enhancement mode GaN HEMT device includes the steps of:
Step 1: epitaxially growing a GaN buffer layer 2, a GaN channel layer 3, a first AlGaN barrier layer 4, a p-GaN layer 6 and an n-GaN layer 7 on a substrate 1 from bottom to top through a metal organic chemical vapor deposition process to form an epitaxial wafer;
Step 2: and cleaning the epitaxial wafer row which grows in an epitaxial mode.
Firstly, soaking an epitaxial wafer in an acetone solution for ultrasonic treatment, cleaning by flowing deionized water, and drying by nitrogen; then, placing the epitaxial wafer into a solution of HCl: H 2 O=1:1, standing for 1.5 minutes, and finally cleaning with flowing deionized water and drying with nitrogen;
Step 3: removing the p-GaN layer 6 and the n-GaN layer 7 positioned in the non-grid region by adopting a dry etching process to expose the first AlGaN barrier layer 4 in the non-grid region, growing a second AlGaN barrier layer 5 on the first AlGaN barrier layer 4 and the p-GaN layer 6, and enabling the second AlGaN barrier layer 5 to continuously cover the side walls of the p-GaN layer 6 and the n-GaN layer 7;
Step 4: depositing metal in the regions of the growth source electrode and the drain electrode left on the second AlGaN barrier layer 5 to form the source electrode and the drain electrode in ohmic contact with the second AlGaN barrier layer 5; the source electrode and the drain electrode are both deposited with metal by adopting an electron beam evaporation process, and the ohmic contact positions on two sides of the source electrode and the drain electrode are subjected to interface treatment by adopting a low-temperature supercritical fluid process before and after the metal deposition;
And 5, etching in the second AlGaN barrier layer 5 to form a gate groove structure so as to expose a part of the n-GaN layer 7, and depositing metal on the exposed n-GaN layer 7 and the second AlGaN barrier layer 5 to form a gate electrode which is in Schottky contact with the second AlGaN barrier layer 5.
And carrying out simulation on the specific embodiment by using Sentaurus TCAD simulation software, respectively writing codes by using a sStructureEditor module and a sDevice module in the software to construct a device structure and a physical model, and carrying out electrical analysis on the constructed device structure.
Example 1
Referring to fig. 1, a GaN HEMT device with integrated P-N junction includes an epitaxial structure, and a source electrode 8, a drain electrode 9 and a gate electrode 10 matched with the epitaxial structure,
The epitaxial structure comprises a substrate 1, a GaN buffer layer 2, a GaN channel layer 3, a first AlGaN barrier layer 4, a second AlGaN barrier layer 5, a p-GaN layer 6, an n-GaN layer 7,p-GaN layer 6 and an n-GaN layer 7 which are sequentially arranged from bottom to top, wherein the first AlGaN barrier layer 4 and the second AlGaN barrier layer 4 are sequentially stacked, the second AlGaN barrier layer 5 is stacked on the first AlGaN barrier layer 4 and the n-GaN layer 7 and covers the side walls of the p-GaN layer 6 and the n-GaN layer 7, a grid groove structure is arranged in a grid electrode region of the second AlGaN barrier layer 5, the bottom of the grid groove structure is located on the surface of the n-GaN layer 7, the bottom of a grid electrode 10 is arranged in the grid groove structure and forms Schottky contact with the n-GaN layer 7, and a source electrode 8 and a drain electrode 9 are arranged in an ohmic region of the second A1GaN barrier layer 5 and form ohmic contact with the second AlGaN barrier layer 5.
In this embodiment, the substrate 1 is an unintentionally doped Si substrate with a thickness of 10 μm, the GaN buffer layer 2 is unintentionally doped GaN with a thickness of 4.2 μm; the GaN channel layer 3 is unintentionally doped GaN, and the thickness is 0.42 mu m; the first AlGaN barrier layer 4 is unintentionally doped with AlGaN, the content of Al component is 0.2, and the thickness is 0.01 mu m; the second AlGaN barrier layer 5 is unintentionally doped with AlGaN, the content of Al component is 0.2, and the thickness is 0.015 mu m; the p-GaN layer 6 is Mg-doped GaN, the doping concentration is 5 x 10-19 cm (-3), and the thickness is 0.12 μm; the n-GaN layer 7 is Si-doped GaN, the doping concentration is 9 x 10-18 cm (-3), and the thickness is 0.03 μm.
Example 2
Referring to fig. 1, a structure of a GaN HEMT device integrated with a P-N junction in the present embodiment is substantially the same as that of embodiment 1, except that: in this embodiment, the first AlGaN barrier layer 4 is unintentionally doped with AlGaN, the Al component content is 0.1, and the thickness is 0.01 μm; the second AlGaN barrier layer 5 is unintentionally doped with AlGaN, the content of Al component is O.1, and the thickness is 0.015 mu m; the p-GaN layer 6 is Mg-doped GaN, the doping concentration is 1 x 10-19 cm (-3), and the thickness is 0.08 μm; the n-GaN layer 7 is Si-doped GaN, the doping concentration is 1 x 10-18 cm (-3), and the thickness is 0.02 μm.
Example 3
Referring to fig. 1, a structure of a GaN HEMT device integrated with a P-N junction in the present embodiment is substantially the same as that of embodiment 1, except that: in this embodiment, the first AlGaN barrier layer 4 is unintentionally doped with AlGaN, the Al component content is 0.5, and the thickness is 0.01 μm; the second AlGaN barrier layer 5 is unintentionally doped with AlGaN, the content of Al component is 0.5, and the thickness is 0.015 mu m; the p-GaN layer 6 is Mg-doped GaN with doping concentration of 1 x 10-20 cm (-3) and thickness of 0.08 μm; the n-GaN layer 7 is Si doped GaN with doping concentration of 1 x 10-19 em (-3) and thickness of 0.04 μm.
Comparative example 1
The structure of a P-N junction integrated GaN HEMT device of comparative example 1 is substantially the same as that of example 1, except that the second AlGaN barrier layer 5 is omitted from comparative example 1.
Comparative example 2
The structure of a P-N junction integrated GaN HEMT device of comparative example 2 is substantially the same as that of example 1, except that: the first AlGaN barrier layer 4 in comparative example 2 was unintentionally doped AlGaN and had a thickness of 0.015 μm; the second AlGaN barrier layer 5 is unintentionally doped with AlGaN and has a thickness of 0.01um.
Comparative example 3
The structure of a P-N junction integrated GaN HEMT device of comparative example 3 is substantially the same as that of example 1, except that: comparative example 3 omits the n-GaN layer 7. The transfer characteristic curve of the P-N junction integrated GaN HEMT device in embodiment 1 is shown in fig. 3, where the conventional device in fig. 3 is the device in comparative example 1, and as can be known from fig. 3, the threshold voltage of the GaN HEMT device is about 3V, the GaN HEMT device is an enhancement mode device, the threshold voltage of the GaN HEMT device is higher than the threshold voltage of the conventional enhancement mode device, and the device in comparative example 1 has no second AlGaN barrier layer, so that the saturated drain current of the device becomes smaller. The output characteristic curve of the P-N junction integrated GaN HEMT device of example 1 is shown in fig. 4, and the conventional device of fig. 4 is the device of comparative example 2, and as can be seen from fig. 4, the saturated drain operating current of the GaN HEMT device is about 0.3A/mm, the saturated drain operating current is higher than the conventional enhancement mode operating current, and the threshold voltage of the device of comparative example 2 is significantly reduced. The gate breakdown voltage curve of the P-N junction integrated GaN HEMT device of example 1 is shown in fig. 5, the conventional device of fig. 5 is the device of comparative example 3, and as can be seen from fig. 5, the gate breakdown voltage of the device of example 1 is 14.5v, and the gate breakdown voltage of the device of comparative example 3 is 7.8v.
The threshold voltage and saturated drain operating current of the GaN HEMT devices of examples 2 and 3 are substantially the same as those of example 1.
Compared with the traditional P-GaN cap layer of the grid metal Schottky junction, the invention uses the P-N reverse stacking layer, when the depletion region extends to the P side and the N side, the P-N reverse stacking layer can bear larger reverse bias voltage, so that the grid breakdown voltage of the device is higher, and because the enhancement type of the device is realized, the invention uses the thin first barrier layer with low A1 component, but the working current of the device is obviously reduced, and the growth of the second barrier layer is beneficial to the recovery of two-dimensional electron gas, so that the working current of the drain electrode is enhanced.
Compared with the traditional P-GaN grid HEMT device, the invention introduces the grid P-N junction structure, and the P-N junction structure can bear higher reverse voltage under the same peak electric field because the depletion region extends to the N side and the P side, and simultaneously, the existence of the composite barrier layer realizes high threshold voltage and simultaneously gives consideration to enough large drain operating current.
It should be understood that the above embodiments are merely for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the present invention and implement the same according to the present invention without limiting the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.
Claims (10)
1. An enhanced GaN HEMT device integrating a P-N junction comprises an epitaxial structure, and a source electrode, a drain electrode and a grid electrode matched with the epitaxial structure, and is characterized in that,
The epitaxial structure comprises a channel layer, a first barrier layer, a second barrier layer and a P-N reverse stacking layer, wherein the first barrier layer is stacked on the channel layer along the selected direction, the P-N reverse stacking layer is stacked on a grid region of the first barrier layer along the selected direction, the second barrier layer is stacked on the first barrier layer and the P-N reverse stacking layer along the selected direction, the source electrode and the drain electrode are arranged on the second barrier layer and form ohmic contact with the second barrier layer, and the grid electrode is arranged on the P-N reverse stacking layer and forms Schottky contact with the P-N reverse stacking layer.
2. The P-N junction integrated enhancement mode GaN HEMT device of claim 1, wherein: the P-N reverse stacking layer comprises a P-type semiconductor layer and an N-type semiconductor layer which are sequentially stacked along a selected direction, the P-type semiconductor layer is arranged on the first barrier layer, and the grid electrode is arranged on the N-type semiconductor layer and forms schottky contact with the N-type semiconductor layer;
Preferably, the p-type semiconductor layer includes a p-GaN layer, and the n-type semiconductor layer includes an n-GaN layer.
3. The P-N junction integrated enhancement mode GaN HEMT device of claim 2, wherein: the doping concentration of the p-type impurity in the p-type semiconductor layer is larger than that of the n-type impurity in the n-type semiconductor layer;
Preferably, the doping concentration of the p-type impurity in the p-type semiconductor layer is 10 19cm-3～1020cm-3, and the doping concentration of the n-type impurity in the n-type semiconductor layer is 10 18cm-3～1019cm-3.
4. The P-N junction integrated enhancement mode GaN HEMT device of claim 2, wherein: the thickness of the p-type semiconductor layer is greater than that of the n-type semiconductor layer;
preferably, the thickness of the p-type semiconductor layer is 80nm to 130nm, and the thickness of the n-type semiconductor layer is 20nm to 40nm.
5. The P-N junction integrated enhancement mode GaN HEMT device of claim 1, wherein: the thickness of the first barrier layer is smaller than that of the second barrier layer;
Preferably, the ratio of the thicknesses of the first barrier layer and the second barrier layer is 2:3.
6. The P-N junction integrated enhancement mode GaN HEMT device of claim 1, wherein: the first barrier layer and the second barrier layer are made of III-nitride materials containing A1, and the content of A1 components in the first barrier layer and the second barrier layer is the same;
Preferably, the content of the A1 component in the first barrier layer and the second barrier layer is 0.1 to 0.5.
7. The P-N junction integrated enhancement mode GaN HEMT device of claim 1, wherein: the gate region of the second barrier layer is also provided with a gate groove structure, the groove bottom of the gate groove structure is positioned on the surface of the n-type semiconductor layer, and part of the gate is arranged in the gate groove structure and is electrically contacted with the n-type semiconductor layer.
8. The P-N junction integrated enhancement mode GaN HEMT device of claim 1, wherein: the channel layer is made of a GaN layer, and the first barrier layer and the second barrier layer are made of AlGaN.
9. The P-N junction integrated enhancement mode GaN HEMT device of claim 1, wherein: the thickness of the channel layer is 50 nm-400 nm.
10. The P-N junction integrated enhancement mode GaN HEMT device of claim 1, wherein: the epitaxial structure further comprises a substrate and a buffer layer, wherein the buffer layer is arranged on the substrate in a stacking manner along the selected direction, and the channel layer is arranged on the buffer layer in a stacking manner along the selected direction;
Preferably, the material of the buffer layer comprises GaN;
Preferably, the thickness of the buffer layer is 2000 nm-4000 nm;
Preferably, the material of the substrate includes any one of SiC, si, gaN.
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| CN202410406443.4A CN118248713A (en) | 2024-04-03 | 2024-04-03 | Enhancement type GaN HEMT device integrating P-N junction |
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| CN202410406443.4A CN118248713A (en) | 2024-04-03 | 2024-04-03 | Enhancement type GaN HEMT device integrating P-N junction |
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