CN118213441A - Manufacturing method of back SE structure TOPCon battery - Google Patents
Manufacturing method of back SE structure TOPCon battery Download PDFInfo
- Publication number
- CN118213441A CN118213441A CN202410393796.5A CN202410393796A CN118213441A CN 118213441 A CN118213441 A CN 118213441A CN 202410393796 A CN202410393796 A CN 202410393796A CN 118213441 A CN118213441 A CN 118213441A
- Authority
- CN
- China
- Prior art keywords
- layer
- silicon wafer
- phosphorus
- poly layer
- poly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 46
- 229910052710 silicon Inorganic materials 0.000 claims description 45
- 239000010703 silicon Substances 0.000 claims description 45
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 41
- 229910052698 phosphorus Inorganic materials 0.000 claims description 41
- 239000011574 phosphorus Substances 0.000 claims description 41
- 238000000151 deposition Methods 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 20
- 230000008021 deposition Effects 0.000 claims description 18
- 239000003513 alkali Substances 0.000 claims description 17
- 239000011248 coating agent Substances 0.000 claims description 15
- 238000000576 coating method Methods 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 230000005641 tunneling Effects 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 7
- 238000005498 polishing Methods 0.000 claims description 7
- 238000004804 winding Methods 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 238000007639 printing Methods 0.000 claims description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 5
- 229910000077 silane Inorganic materials 0.000 claims description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 239000005922 Phosphane Substances 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 238000009826 distribution Methods 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 229910000064 phosphane Inorganic materials 0.000 claims description 3
- 238000002310 reflectometry Methods 0.000 claims description 3
- 238000007650 screen-printing Methods 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- -1 silver-aluminum Chemical compound 0.000 claims description 3
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 2
- 230000004580 weight loss Effects 0.000 claims description 2
- 210000002268 wool Anatomy 0.000 claims description 2
- 238000010521 absorption reaction Methods 0.000 abstract description 10
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 229910052755 nonmetal Inorganic materials 0.000 abstract description 7
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 239000002002 slurry Substances 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 68
- 238000002161 passivation Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004093 laser heating Methods 0.000 description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 101001073212 Arabidopsis thaliana Peroxidase 33 Proteins 0.000 description 1
- 101001123325 Homo sapiens Peroxisome proliferator-activated receptor gamma coactivator 1-beta Proteins 0.000 description 1
- 102100028961 Peroxisome proliferator-activated receptor gamma coactivator 1-beta Human genes 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006388 chemical passivation reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Landscapes
- Photovoltaic Devices (AREA)
Abstract
The invention provides a manufacturing method of a back SE structure TOPCon battery, which is characterized in that a high-concentration +thick poly is formed in a metal region of the SE structure, and a low-concentration +thin poly structure is formed in a non-metal region. The structure manufactured by the method ensures the thickness difference and also meets the concentration difference, the metal area with high concentration and thick poly ensures the contact performance of the slurry, and the thin poly and low concentration of the non-metal area can reduce parasitic absorption and free carrier absorption, thereby improving the short-circuit current.
Description
Technical Field
The invention relates to the technical field of photovoltaics, in particular to a manufacturing method of a back SE structure TOPCon battery.
Background
TOPCon batteries are used as current main current batteries, are subjected to the layout of most manufacturers, and according to professional organization statistics, the domestic planning capacity reaches 224GW by 2023, so that PERC batteries can be gradually replaced in the future.
The back of the existing TOPCon structure adopts a tunneling oxidation structure, namely an ultrathin tunneling oxidation layer and a doped polysilicon layer are deposited on the back, chemical passivation and multi-sub tunneling effect of silicon oxide and field passivation of the doped polysilicon layer are utilized, surface recombination on the back is greatly reduced, and conversion efficiency of the battery is improved.
The TOPCon structure has very good passivation, but the introduced doped polysilicon has very serious parasitic absorption to light, and according to experimental data, the doped polysilicon on the back side can cause absorption of about 0.004 mA/cm/nm, while the doped polysilicon on the 30nm meets the existing passivation requirement, but is limited by the current back side slurry, and when the thickness is lower than 80nm, the slurry burning-through occurs on the back side polysilicon layer, so that the electric performance is affected.
Disclosure of Invention
The invention aims to provide a manufacturing method of a back SE structure TOPCon battery, which solves the problem of slurry sintering of a metal area by respectively forming a high surface concentration+thick poly area and a low surface concentration+thin poly area on the back, reduces the poly thickness and concentration of a non-metal area, reduces parasitic absorption and free carrier absorption, and improves the short-circuit current of the battery, thereby improving the conversion efficiency of the battery.
In order to achieve the above purpose, the present invention provides the following technical solutions:
In a first aspect, the present invention provides a method for manufacturing a back side SE structure TOPCon battery, including the steps of:
S1, selecting an N-type silicon wafer, and performing texturing on the N-type silicon wafer on a texturing machine;
S2, performing boron diffusion on the textured silicon wafer;
S3, removing BSG on the back and the edge of the silicon wafer after boron diffusion is completed, and then performing alkali polishing on the back, and simultaneously retaining BSG on the front;
S4, sequentially depositing the following layers on the back of the silicon wafer subjected to alkali polishing from bottom to top: the device comprises a tunneling oxide layer, an intrinsic poly layer, an intermediate oxide layer and a phosphorus doped poly layer, wherein the thickness of the intrinsic poly layer is smaller than that of the phosphorus doped poly layer;
s5, generating a patterned silicon oxide mask on the surface of the silicon wafer after the deposition;
S6, carrying out alkaline etching on the silicon wafer with the silicon oxide mask, wherein in the silicon oxide protected area, the lower film layer is not corroded, and the area without the silicon oxide protection is corroded by alkali in an alkali solution, but due to the existence of an intermediate oxide layer, alkali can slow down or even stop corroding at the interface and does not continue corroding the lower poly layer, so that an etching time difference exists, an etching window is greatly increased, different thickness difference structures, namely a phosphorus doped poly layer and an intrinsic poly layer are formed, and an independent intrinsic poly layer area are formed, and meanwhile, the silicon oxide of the protected area is removed in a subsequent HF (high frequency) groove;
S7, carrying out a high-temperature phosphorus expansion process on the etched silicon wafer, crystallizing and phosphorus expanding the intrinsic poly layer on the back, wherein a layer of phosphorus-doped poly layer exists in a protected area, and the intrinsic poly layer is taken as a doping source except a doping source when the phosphorus is expanded at a high temperature, and only one layer of intrinsic poly layer is arranged in an unprotected area and can be doped only in a phosphorus expansion mode, so that staggered distribution of thick poly+ high doping and thin poly+ low doping is formed respectively;
s8, performing front PSG etching on the phosphorus-expanded silicon wafer, and then performing a winding plating removing process on the silicon wafer to remove the doped polysilicon layer subjected to front winding plating;
s9, carrying out front silicon nitride and aluminum oxide coating on the silicon wafer subjected to the de-winding coating, and carrying out back silicon nitride coating;
and S10, printing silver-aluminum paste on the front side of the coated silicon wafer by screen printing, and printing silver paste on the back side of the coated silicon wafer to prepare the back side SE structure TOPCon battery piece.
Preferably, in step S1, the silicon wafer parameters used are: the thickness is 160-180um, the resistivity is 0.5-1.0mΩ cm; the wool making parameters are as follows: the reflectivity is controlled to be 9-11%, and the weight loss is controlled to be 0.2-1g.
Preferably, in step S2, the process parameters are: the boron diffusion deposition temperature is 900-1050 ℃, the diffusion time is 3h30min, and the square resistance is 80-200ohm/sq.
Preferably, in step S4, the phosphorus doped poly layer is deposited while introducing a phosphorus-containing gas, phosphorus doping is performed to form an in-situ doped layer, and the thickness of the intrinsic poly layer is smaller than the thickness of the phosphorus doped poly layer. More preferably, the phosphorus-containing gas is a phosphine. The specific steps of the step S4 are as follows: in LPCVD, 10000-100000sccm oxygen is introduced, and an ultrathin tunneling oxide layer with the thickness of 1-2nm is deposited firstly at 500-600 ℃ for 300-900s by using an atmospheric pressure oxidation mode; then 300-2000sccm silane is introduced, the deposition temperature is 550-650 ℃, the deposition time is 10-500s, the pressure is 200-500mTorr, and a 10-50nm intrinsic poly layer is deposited; then introducing 10000-100000sccm of oxygen to react with the intrinsic poly layer deposited before to generate a 1-2nm intermediate oxide layer; then 300-2000sccm silane and 100-1000sccm phosphane are introduced, the deposition temperature is 550-650 ℃, the deposition time is 500-1500s, the pressure is 200-500mTorr, and a 50-100nm in-situ phosphorus doped poly layer is deposited.
Preferably, in step S5, the silicon oxide mask is formed by laser irradiation heating, wherein the specific process is as follows: coating a layer of TEOS solution on the surface of a silicon wafer, drying to form a layer of film, heating the surface of the film by utilizing laser, and reacting the film in a heating area to generate silicon oxide, wherein the laser is infrared laser with the power of 5-30W, the repetition frequency of 120000KHZ and the speed of 10000-40000mm/s.
Preferably, in step S9, the thicknesses of the front side silicon nitride film and the aluminum oxide film are respectively 70-90nm and 3-10nm, and the thickness of the back side silicon nitride film is 80-90nm.
In a second aspect, the invention also provides a rear SE structure TOPCon battery made by a method as described above.
Compared with the prior art, the invention has the beneficial effects that: the method realizes the SE structure of the metal region with high concentration and thick poly and the non-metal region with low concentration and thin poly on the back by forming the protective layer reversely etched on the metal region by mask and laser, thereby realizing the reduction of parasitic absorption while meeting the sintering requirement of thick poly on the back on slurry. Compared with the traditional back Topcon passivation structure, the SE structure adopts a structure of high concentration and thick poly in a metal region and low concentration and thin poly in a non-metal region, so that the thickness difference is ensured, meanwhile, the concentration difference is also satisfied, the contact performance of slurry is ensured by the high concentration metal region, and free carrier absorption and parasitic absorption can be reduced by the low concentration and the thin poly in the non-metal region, so that the short circuit current is improved.
Drawings
Fig. 1 is a schematic view of a back side SE structure TOPCon cell structure made by the method of the present invention.
In the figure: 1: front side silicon nitride; 2: alumina; 3: a P-type emitter; 4: an N-type substrate; 5: tunneling oxide layer; 6: a first phosphorus doped poly layer; 7: an intermediate oxide layer; 8: a second phosphorus doped poly layer; 9: back side silicon nitride; 10: a back electrode; 11: a front electrode.
Detailed Description
The invention aims to solve the problem of thickness of the passivation structure on the back of the battery piece and simultaneously meet the contradictory requirements of reducing parasitic absorption and burning-through resistance. In one exemplary embodiment, we have the technical scheme that a "SE" structure is adopted on the back surface of TOPCon cells, namely a double-layer poly structure is deposited on the back surface, then a patterned region is formed by adopting a mask coating and laser heating mode, and then a lightly doped structure is formed by back etching, namely the structure shown in fig. 1 is formed: the heavily doped region (metal region) is a structure of a tunneling oxide layer, a first phosphorus doped poly layer, an intermediate oxide layer and a second phosphorus doped poly layer, and the lightly doped region (nonmetal region) is in the form of the tunneling oxide layer, the first phosphorus doped poly layer and the second phosphorus doped poly layer, wherein the thickness of the first phosphorus doped poly layer is smaller than that of the second phosphorus doped poly layer, and the second phosphorus doped poly layer is deposited in-situ doped.
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the terms "upper," "lower," "inner," "outer," "front," "rear," "both ends," "one end," "the other end," and the like indicate or are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "provided," "connected," and the like are to be construed broadly, and may be fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
Examples
In an exemplary embodiment, the method of making the backside SE structure TOPCon cell is as follows.
Firstly, selecting an N-type silicon wafer, wherein the thickness of the silicon wafer is 160-180um, the resistivity is 0.5-1.0mΩ cm, then, texturing by trough alkali, the reflectivity is controlled to be 9-11%, and the weight reduction is controlled to be 0.2-1g.
And step two, performing boron diffusion on the silicon wafer subjected to the step one in a back-to-back mode, wherein the deposition temperature is 900-1050 ℃, the diffusion time is 3h30min, and the square resistance is 80-200ohm/sq.
And thirdly, removing BSG on the back surface and the edge of the silicon wafer after the step two by using chain HF, and polishing the back surface by using groove type alkali polishing, and simultaneously retaining the BSG on the front surface.
Step four, depositing a tunneling oxide layer and a plurality of amorphous silicon layers on the back surface of the silicon wafer after the step three by using an LPCVD silicon wafer, namely firstly introducing 10000-100000sccm of oxygen, and firstly depositing an ultrathin tunneling oxide layer with the thickness of 1-2nm by using a normal pressure oxidation mode at the temperature of 500-600 ℃ for 300-900 s; then 300-2000sccm silane is introduced, the deposition temperature is 550-650 ℃, the deposition time is 10-500s, the pressure is 200-500mTorr, and a 10-50nm intrinsic poly layer is deposited; then 10000-100000sccm oxygen is introduced to react with the intrinsic poly layer deposited before to generate an intermediate oxide layer with the thickness of 1-2nm, then 300-2000sccm silicane is introduced, 100-1000sccm phosphane is introduced, the deposition temperature is 550-650 ℃, the deposition time is 500-1500s, the pressure is 200-500mTorr, and an in-situ phosphorus doped poly layer with the thickness of 50-100nm is deposited.
And fifthly, coating a layer of TEOS (tetraethoxysilane) solution on the surface of the silicon wafer after the step four, drying to form a layer of film, heating the surface of the film by utilizing laser, wherein the film in a heating area can react to generate silicon oxide, the laser is infrared laser with the power of 5-30W, the repetition frequency of 120000KHZ and the speed of 10000-40000mm/s, and the film is only acted, so that extra laser damage can not be generated to poly below the film.
Step six, etching the silicon wafer after the step five by using a groove type alkali polishing machine, wherein the laser area is protected by silicon oxide, the lower poly can not be corroded, but the laser area is not protected by the silicon oxide, but can be corroded by alkali in an alkali solution, but the alkali can slow down or even stop corroding at the interface due to the existence of an intermediate oxide layer, the lower poly layer can not be continuously corroded, corrosion windows are greatly increased, different thickness difference structures are formed, and meanwhile, the silicon oxide of the laser area is removed in a subsequent HF groove.
And step seven, carrying out high-temperature phosphorus expansion process on the silicon wafer after the step six by utilizing a phosphorus expansion pipe, and doping and crystallizing the intrinsic poly layer and the phosphorus doped poly layer on the back, wherein as a layer of in-situ doped poly layer exists in the laser region, phosphorus oxychloride introduced into the furnace pipe can be used as a doping source during high-temperature phosphorus expansion, and can be used as a doping source, and only one intrinsic poly layer can be doped only in a phosphorus expansion mode after alkali etching is carried out on a non-laser region, so that the alternating distribution of thick poly+ high doping and thin poly+ low doping can be respectively formed.
And step eight, etching the PSG formed on the front surface of the silicon wafer by using chain HF, and then performing a winding plating removing process on the silicon wafer to remove the doped polysilicon layer wound and plated on the front surface.
Step nine, coating the silicon nitride and the aluminum oxide on the front surface of the silicon wafer after the step eight, wherein the thicknesses of the silicon nitride and the aluminum oxide are respectively 70-90nm and 3-10nm; the thickness of the back silicon nitride coating is 80-90nm;
And step ten, printing silver-aluminum paste on the front surface and silver paste on the back surface of the silicon wafer obtained in the step nine by utilizing screen printing.
The present invention is not described in detail in the present application, and is well known to those skilled in the art. It should be understood that the specific details of the steps above are merely illustrative, and that alternatives may be readily found after understanding the principles of the invention, and therefore the above specific details should not be taken to limit the scope of the invention, which is ultimately defined by the claims. For example, in the embodiment, the mask is formed on the silicon wafer by laser heating, but those skilled in the art can easily think of forming the mask by other methods, such as coating, printing, etching, depositing, etc., according to the principle of the method of the present invention, so long as the silicon oxide mask is formed on the silicon wafer to protect the underlying poly layer, and thus these alternatives should be protected.
Finally, what is to be described is: the above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the examples, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered by the scope of the claims of the present invention.
Claims (8)
1. A method for manufacturing a back side SE structure TOPCon battery, the method comprising the steps of:
s1, selecting an N-type silicon wafer, and texturing the N-type silicon wafer;
S2, performing boron diffusion on the textured silicon wafer;
S3, removing BSG on the back and the edge of the silicon wafer after boron diffusion is completed, and then performing alkali polishing on the back, and simultaneously retaining BSG on the front;
S4, sequentially depositing the following layers on the back of the silicon wafer subjected to alkali polishing from bottom to top: the device comprises a tunneling oxide layer, an intrinsic poly layer, an intermediate oxide layer and a phosphorus doped poly layer, wherein phosphorus-containing gas is required to be introduced into the phosphorus doped poly layer during deposition, phosphorus doping is carried out to form an in-situ doped layer, and the thickness of the intrinsic poly layer is smaller than that of the phosphorus doped poly layer;
s5, generating a patterned silicon oxide mask on the surface of the silicon wafer after the deposition;
s6, carrying out alkaline etching on the silicon wafer with the silicon oxide mask, wherein in the silicon oxide protected area, the lower film layer is not corroded, and the area without the silicon oxide protection is corroded by alkali in an alkali solution, but due to the existence of an intermediate oxide layer, alkali can slow down or even stop corroding at the interface and does not continue corroding the lower poly, so that an etching time difference exists, an etching window is greatly increased, different thickness difference structures, namely a phosphorus doped poly layer and an intrinsic poly layer are formed, and an independent intrinsic poly layer area are formed, and meanwhile, the silicon oxide of the protected area is removed in a subsequent HF (high frequency) groove;
S7, carrying out a high-temperature phosphorus expansion process on the etched silicon wafer, crystallizing and phosphorus expanding the intrinsic poly layer on the back, wherein a layer of phosphorus-doped poly layer exists in a protected area, and the intrinsic poly layer is taken as a doping source except a doping source when the phosphorus is expanded at a high temperature, and only one layer of intrinsic poly layer is arranged in an unprotected area and can be doped only in a phosphorus expansion mode, so that staggered distribution of thick poly+ high doping and thin poly+ low doping is formed respectively;
s8, performing front PSG etching on the phosphorus-expanded silicon wafer, and then performing a winding plating removing process on the silicon wafer to remove the doped polysilicon layer subjected to front winding plating;
s9, carrying out front silicon nitride and aluminum oxide coating on the silicon wafer subjected to the de-winding coating, and carrying out back silicon nitride coating;
and S10, printing silver-aluminum paste on the front side of the coated silicon wafer by screen printing, and printing silver paste on the back side of the coated silicon wafer to prepare the back side SE structure TOPCon battery piece.
2. The method of manufacturing a back side SE structure TOPCon battery as set forth in claim 1, wherein in step S1, the silicon wafer parameters used are: the thickness is 160-180um, the resistivity is 0.5-1.0mΩ cm; the wool making parameters are as follows: the reflectivity is controlled to be 9-11%, and the weight loss is controlled to be 0.2-1g.
3. The method for manufacturing the back SE structure TOPCon battery as set forth in claim 1, wherein in step S2, the process parameters are: the boron diffusion deposition temperature is 900-1050 ℃, the diffusion time is 3h30min, and the square resistance is 80-200ohm/sq.
4. The method of manufacturing a back side SE structure TOPCon battery of claim 1, wherein in step S4, said phosphorus-containing gas is a phosphine.
5. The method for manufacturing the back SE structure TOPCon battery as set forth in claim 4, wherein the specific steps of step S4 are as follows: in LPCVD, 10000-100000sccm oxygen is introduced, and an ultrathin tunneling oxide layer with the thickness of 1-2nm is deposited firstly at 500-600 ℃ for 300-900s by using an atmospheric pressure oxidation mode; then 300-2000sccm silane is introduced, the deposition temperature is 550-650 ℃, the deposition time is 10-500s, the pressure is 200-500mTorr, and a layer of 10-50nm intrinsic poly layer is deposited and is an intrinsic poly layer; then introducing 10000-100000sccm of oxygen to react with the intrinsic poly layer deposited before to generate a 1-2nm intermediate oxide layer; then 300-2000sccm silane and 100-1000sccm phosphane are introduced, the deposition temperature is 550-650 ℃, the deposition time is 500-1500s, the pressure is 200-500mTorr, and a 50-100nm phosphorus doped poly layer, namely the phosphorus doped poly layer, is deposited.
6. The method for manufacturing a back side SE structure TOPCon battery as claimed in claim 1, wherein in step S5, the silicon oxide mask is formed by laser irradiation heating, wherein the specific process is as follows: coating a layer of TEOS solution on the surface of a silicon wafer, drying to form a layer of film, heating the surface of the film by utilizing laser, and reacting the film in a heating area to generate silicon oxide, wherein the laser is infrared laser with the power of 5-30W, the repetition frequency of 120000KHZ and the speed of 10000-40000mm/s.
7. The method of manufacturing a back side SE structure TOPCon battery according to claim 1, wherein in step S9, the front side silicon nitride and aluminum oxide coating films have thicknesses of 70-90nm and 3-10nm, respectively, and the back side silicon nitride coating film has a thickness of 80-90nm.
8. A backside SE structure TOPCon battery fabricated by the method of any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410393796.5A CN118213441A (en) | 2024-04-02 | 2024-04-02 | Manufacturing method of back SE structure TOPCon battery |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410393796.5A CN118213441A (en) | 2024-04-02 | 2024-04-02 | Manufacturing method of back SE structure TOPCon battery |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118213441A true CN118213441A (en) | 2024-06-18 |
Family
ID=91448727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410393796.5A Pending CN118213441A (en) | 2024-04-02 | 2024-04-02 | Manufacturing method of back SE structure TOPCon battery |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118213441A (en) |
-
2024
- 2024-04-02 CN CN202410393796.5A patent/CN118213441A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5025184B2 (en) | Solar cell element, solar cell module using the same, and manufacturing method thereof | |
| CN111029438A (en) | Preparation method of N-type passivated contact solar cell | |
| CN113345970A (en) | P-type back contact type crystalline silicon solar cell, preparation method and cell assembly | |
| CN111640823B (en) | N-type passivated contact battery and preparation method thereof | |
| CN110890432A (en) | Efficient polycrystalline silicon solar cell and preparation method thereof | |
| CN213519984U (en) | Solar cell | |
| CN117153953B (en) | Preparation method of split-film type double-sided TOPCON battery | |
| CN114823933A (en) | Solar cell structure and manufacturing method thereof | |
| JP6246982B1 (en) | High photoelectric conversion efficiency solar cell and method for producing high photoelectric conversion efficiency solar cell | |
| CN115207136A (en) | Manufacturing method of P-type IBC battery | |
| CN117673207B (en) | Preparation method of solar cell, solar cell and photovoltaic module | |
| CN114050105A (en) | TopCon battery preparation method | |
| KR20120062224A (en) | Method for fabricating solar cell | |
| CN218632057U (en) | P-TBC back contact structure crystalline silicon solar cell | |
| CN117457797A (en) | Preparation method and application of TOPCON battery structure | |
| JP6330108B1 (en) | High photoelectric conversion efficiency solar cell and method for producing high photoelectric conversion efficiency solar cell | |
| CN115692516A (en) | Novel TOPCON battery and manufacturing method thereof | |
| CN219696463U (en) | Solar cell | |
| CN117133814A (en) | Selective passivation contact solar cell, preparation method thereof and photovoltaic module | |
| CN116469948A (en) | TOPCON battery and preparation method thereof | |
| CN116314471A (en) | Preparation method of rear SE structure | |
| CN216563145U (en) | Battery back structure and double-sided TOPCon solar battery | |
| JP6220483B1 (en) | High photoelectric conversion efficiency solar cell and method for producing high photoelectric conversion efficiency solar cell | |
| CN118213441A (en) | Manufacturing method of back SE structure TOPCon battery | |
| CN117276361B (en) | Solar cell, manufacturing method thereof, photovoltaic module and photovoltaic system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination |