CN115207136A - Manufacturing method of P-type IBC battery - Google Patents
Manufacturing method of P-type IBC battery Download PDFInfo
- Publication number
- CN115207136A CN115207136A CN202210854522.2A CN202210854522A CN115207136A CN 115207136 A CN115207136 A CN 115207136A CN 202210854522 A CN202210854522 A CN 202210854522A CN 115207136 A CN115207136 A CN 115207136A
- Authority
- CN
- China
- Prior art keywords
- layer
- type
- doping
- silicon substrate
- intrinsic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 30
- 239000010703 silicon Substances 0.000 claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 claims abstract description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052796 boron Inorganic materials 0.000 claims abstract description 10
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 10
- 239000011574 phosphorus Substances 0.000 claims abstract description 10
- 238000010030 laminating Methods 0.000 claims abstract description 8
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 22
- 239000005388 borosilicate glass Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 229910021645 metal ion Inorganic materials 0.000 claims description 3
- 238000006386 neutralization reaction Methods 0.000 claims description 3
- 239000003921 oil Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 239000002245 particle Substances 0.000 claims description 3
- 239000005360 phosphosilicate glass Substances 0.000 claims description 3
- 238000005406 washing Methods 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 7
- 229910004298 SiO 2 Inorganic materials 0.000 abstract description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0216—Coatings
- H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
- H01L31/076—Multiple junction or tandem solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
- H01L31/077—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type the devices comprising monocrystalline or polycrystalline materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
- H01L31/182—Special manufacturing methods for polycrystalline Si, e.g. Si ribbon, poly Si ingots, thin films of polycrystalline Si
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a manufacturing method of a P-type IBC battery, which comprises the following steps: sequentially laminating a first SiO layer on one side surface of a P-type silicon substrate 2 A layer and a first intrinsic polysilicon layer; carrying out phosphorus doping on the first intrinsic polycrystalline silicon layer to form an N-type doping layer; forming a mask layer on the N-type doping layer, and carrying out patterning slotting on the mask layer; using the mask layer as a mask to sequentially etch the N-type doped layer and the first SiO 2 A layer exposing a partial region of one side surface of the P-type silicon substrate; sequentially laminating a second SiO layer on the partial region 2 A layer and a second intrinsic polysilicon layer; carrying out boron doping on the second intrinsic polycrystalline silicon layer to form a P-type doped layer; and forming electrodes on the N-type doped layer and the P-type doped layer respectively.The invention improves the photoelectric conversion efficiency of the P-type IBC battery.
Description
Technical Field
The invention relates to the technical field of photovoltaic power generation, in particular to a manufacturing method of a P-type IBC battery.
Background
At present, with the gradual depletion of fossil energy, solar cells are increasingly widely used as a new energy alternative. A solar cell is a device that converts solar energy into electrical energy. The solar cell generates current carriers by utilizing a photovoltaic principle, and then the current carriers are led out by using the electrodes, so that the electric energy is effectively utilized.
The IBC cell is one of the photovoltaic cells with the highest conversion efficiency at present, the cell takes monocrystalline silicon as a substrate, a p-n junction and a metal electrode are positioned on the back surface of the cell, and the front surface is not shaded by the metal electrode, so that very high short-circuit current and conversion efficiency can be obtained. The IBC battery can be divided into an N-type IBC battery and a P-type IBC battery according to the type of a substrate, and the P-type IBC is more and more favored by the industry at present due to simple process and lower cost.
However, due to the surface passivation problem, the conversion efficiency of the P-type IBC battery is restricted, and the conversion efficiency of the P-type IBC battery can be greatly improved by overlapping and passivating the contact structure.
Disclosure of Invention
In view of the defects in the prior art, the invention provides a manufacturing method of a P-type IBC battery, which comprises the following steps:
sequentially laminating a first SiO layer on one side surface of a P-type silicon substrate 2 A layer and a first intrinsic polysilicon layer;
carrying out phosphorus doping on the first intrinsic polycrystalline silicon layer to form an N-type doping layer;
forming a mask layer on the N-type doping layer, and carrying out patterning slotting on the mask layer;
sequentially etching the N-type doped layer and the first SiO by taking the mask layer as a mask 2 A layer exposing a partial region of one side surface of the P-type silicon substrate;
sequentially laminating to form a second SiO on the partial region 2 A layer and a second intrinsic polysilicon layer;
carrying out boron doping on the second intrinsic polycrystalline silicon layer to form a P-type doped layer;
and forming electrodes on the N-type doped layer and the P-type doped layer respectively.
Preferably, the phosphorus doping the first intrinsic polycrystalline silicon layer comprises:
diffusing phosphorus impurities for 20 minutes at the temperature of 850-900 ℃;
the phosphosilicate glass formed during the doping process is cleaned by an HF solution.
Preferably, the boron doping the second intrinsic polycrystalline silicon layer comprises:
depositing a borosilicate glass layer on the second intrinsic polycrystalline silicon layer;
diffusing boron particles of the borosilicate glass layer into the second intrinsic polycrystalline silicon layer by adopting a laser doping process, wherein the width of a laser spot of the laser doping process is 10-300 um, the laser power is 20-80W, the pulse width is 0.5-2 us, and the laser frequency is more than or equal to 20KHz;
the borosilicate glass layer and the borosilicate glass formed during the doping process are cleaned by an HF solution.
Preferably, before forming electrodes on the N-type doped layer and the P-type doped layer, respectively, the method further comprises:
putting the P-type silicon substrate into 5-20% KOH solution to corrode for 10-300 s, and then cleaning with pure water;
putting the cleaned P-type silicon substrate into a KOH solution with the volume concentration of 1-3% for texturing for 7-10 min;
annealing and oxidizing the textured P-type silicon substrate;
and forming a back silicon nitride layer and a front silicon nitride layer.
Preferably, the temperature of the annealing oxidation is 850-950 ℃, the duration is 10-30 min, and the oxygen introduction amount is more than or equal to 8000sccm.
Preferably, the mask layer is a silicon nitride film with a thickness of 50nm to 70nm.
Preferably, a first SiO is formed on one side surface of the P-type silicon substrate by stacking in sequence 2 The layer and the first intrinsic polycrystalline silicon layer comprise:
putting the P-type silicon substrate into H with the volume concentration of 0.2-1% 2 O 2 Cleaning oil stains on the surface in the solution;
then, the P-type silicon substrate is put into NaOH solution with the mass concentration of 5% -20% for neutralization, and metal ions and an oxide layer are cleaned;
and then washing and drying.
In the P-type IBC battery structure manufactured by the manufacturing method, the tunneling oxide layers are arranged between the P-type silicon substrate and the N-type doping layer as well as between the P-type silicon substrate and the P-type doping layer, so that the photoelectric conversion efficiency of the P-type IBC battery is improved.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a P-type IBC battery according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention are described in detail below with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the accompanying drawings. The embodiments of the invention shown in the drawings and described in accordance with the drawings are merely exemplary and the invention is not limited to these embodiments.
It should be noted that, in order to avoid obscuring the present invention with unnecessary details, only the structures and/or processing steps closely related to the scheme according to the present invention are shown in the drawings, and other details not so relevant to the present invention are omitted.
The embodiment provides a method for manufacturing a P-type IBC battery, which comprises the following steps:
s1, sequentially laminating a first SiO on one side surface of a P-type silicon substrate 2 A layer and a first intrinsic polysilicon layer.
And S2, carrying out phosphorus doping on the first intrinsic polycrystalline silicon layer to form an N-type doped layer.
And S3, forming a mask layer on the N-type doping layer, and carrying out patterning slotting on the mask layer. Wherein the mask layer is a silicon nitride film with a thickness of 50 nm-70 nm.
S4, with the mask layer as a mask, sequentially etching the N-type doped layer and the first SiO 2 And the layer is used for exposing partial area of one side surface of the P-type silicon substrate.
S5, sequentially laminating and forming second SiO on the partial area 2 A layer and a second intrinsic polysilicon layer.
And S6, carrying out boron doping on the second intrinsic polycrystalline silicon layer to form a P-type doped layer.
And S7, forming electrodes on the N-type doped layer and the P-type doped layer respectively.
Specifically, phosphorus doping the first intrinsic polycrystalline silicon layer includes: diffusing the phosphorus impurities for 20min at the temperature of 850-900 ℃. The phosphosilicate glass formed during the doping process is then cleaned by an HF solution.
Specifically, boron doping the second intrinsic polysilicon layer includes:
and depositing and forming a borosilicate glass layer on the second intrinsic polycrystalline silicon layer. And then diffusing the boron particles of the borosilicate glass layer into the second intrinsic polycrystalline silicon layer by adopting a laser doping process. The laser doping process is characterized in that the width of a laser spot is 10-300 um, the laser power is 20-80W, the pulse width is 0.5-2 us, and the laser frequency is more than or equal to 20KHz. The borosilicate glass layer and the borosilicate glass formed during the doping process are then cleaned by means of an HF solution.
Preferably, before forming electrodes on the N-type doped layer and the P-type doped layer, respectively, the method further comprises:
and putting the P-type silicon substrate into a KOH solution with the mass concentration of 5-20% for corrosion for 10-300 s, and then cleaning by using pure water. And then putting the cleaned P-type silicon substrate into a KOH solution with the volume concentration of 1-3% for texture surface making for 7-10 min. And then annealing and oxidizing the textured P-type silicon substrate. And then forming a back silicon nitride layer and a front silicon nitride layer. Wherein the temperature of the annealing oxidation is 850-950 ℃, the duration is 10-30 min, and the oxygen introduction amount is more than or equal to 8000sccm.
Preferably, a first SiO is formed on one side surface of the P-type silicon substrate by stacking in sequence 2 The layer and the first intrinsic polycrystalline silicon layer comprise:
putting the P-type silicon substrate into H with the volume concentration of 0.2-1% 2 O 2 And cleaning oil stains on the surface in the solution. And then, the P-type silicon substrate is placed into a NaOH solution with the mass concentration of 5% -20% for neutralization, and metal ions and an oxide layer are cleaned. And then washing and drying.
In the P-type IBC cell structure manufactured by the manufacturing method of the embodiment, tunneling oxide layers are arranged between the P-type silicon substrate and the N-type doping layer and between the P-type silicon substrate and the P-type doping layer, so that the photoelectric conversion efficiency of the P-type IBC cell is improved.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (7)
1. A manufacturing method of a P-type IBC battery is characterized by comprising the following steps:
sequentially laminating a first SiO layer on one side surface of a P-type silicon substrate 2 A layer and a first intrinsic polysilicon layer;
carrying out phosphorus doping on the first intrinsic polycrystalline silicon layer to form an N-type doping layer;
forming a mask layer on the N-type doping layer, and carrying out patterning slotting on the mask layer;
sequentially etching the N-type doped layer and the first SiO by taking the mask layer as a mask 2 A layer exposing a partial region of one side surface of the P-type silicon substrate;
sequentially laminating to form a second SiO on the partial region 2 A layer and a second intrinsic polysilicon layer;
carrying out boron doping on the second intrinsic polycrystalline silicon layer to form a P-type doped layer;
and forming electrodes on the N-type doped layer and the P-type doped layer respectively.
2. The method of claim 1, wherein phosphorus doping the first intrinsic polysilicon layer comprises:
diffusing phosphorus impurities for 20 minutes at the temperature of 850-900 ℃;
the phosphosilicate glass formed during the doping process is cleaned by an HF solution.
3. The method of claim 1, wherein the boron doping the second intrinsic polysilicon layer comprises:
depositing and forming a borosilicate glass layer on the second intrinsic polycrystalline silicon layer;
diffusing boron particles of the borosilicate glass layer into the second intrinsic polycrystalline silicon layer by adopting a laser doping process;
the borosilicate glass layer and the borosilicate glass formed during the doping process are cleaned by an HF solution.
4. The method of claim 3, wherein before forming electrodes on the N-doped layer and the P-doped layer respectively, the method comprises:
putting the P-type silicon substrate into 5-20% KOH solution to corrode for 10-300 s, and then cleaning with pure water;
putting the cleaned P-type silicon substrate into a KOH solution with the volume concentration of 1-3% for texturing for 7-10 min;
annealing and oxidizing the textured P-type silicon substrate;
and forming a back silicon nitride layer and a front silicon nitride layer.
5. The manufacturing method of the P-type IBC battery according to claim 4, wherein the annealing oxidation temperature is 850-950 ℃, the time duration is 10-30 min, and the oxygen introduction amount is more than or equal to 8000sccm.
6. The method for manufacturing the P-type IBC battery of claim 1, wherein the mask layer is a silicon nitride film with a thickness of 50nm to 70nm.
7. The method of claim 1, wherein the first SiO is formed on the surface of the P-type silicon substrate by stacking in sequence 2 The layer and the first intrinsic polycrystalline silicon layer comprise:
putting the P-type silicon substrate into H with the volume concentration of 0.2-1% 2 O 2 Cleaning oil stains on the surface in the solution;
then, the P-type silicon substrate is put into NaOH solution with the mass concentration of 5% -20% for neutralization, and metal ions and an oxide layer are cleaned;
and then washing and drying.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210854522.2A CN115207136A (en) | 2022-07-15 | 2022-07-15 | Manufacturing method of P-type IBC battery |
| PCT/CN2023/101137 WO2024012162A1 (en) | 2022-07-15 | 2023-06-19 | Manufacturing method for p-type ibc battery |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210854522.2A CN115207136A (en) | 2022-07-15 | 2022-07-15 | Manufacturing method of P-type IBC battery |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115207136A true CN115207136A (en) | 2022-10-18 |
Family
ID=83583253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210854522.2A Pending CN115207136A (en) | 2022-07-15 | 2022-07-15 | Manufacturing method of P-type IBC battery |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN115207136A (en) |
| WO (1) | WO2024012162A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024012162A1 (en) * | 2022-07-15 | 2024-01-18 | 青海黄河上游水电开发有限责任公司西宁太阳能电力分公司 | Manufacturing method for p-type ibc battery |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN210926046U (en) * | 2019-10-29 | 2020-07-03 | 苏州阿特斯阳光电力科技有限公司 | Solar cell |
| CN113921625A (en) * | 2021-09-30 | 2022-01-11 | 泰州隆基乐叶光伏科技有限公司 | Back contact battery and manufacturing method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114695593A (en) * | 2020-12-30 | 2022-07-01 | 苏州阿特斯阳光电力科技有限公司 | Preparation method of back contact battery and back contact battery |
| CN113921626A (en) * | 2021-09-30 | 2022-01-11 | 泰州隆基乐叶光伏科技有限公司 | Manufacturing method of back contact battery |
| CN115207136A (en) * | 2022-07-15 | 2022-10-18 | 青海黄河上游水电开发有限责任公司西宁太阳能电力分公司 | Manufacturing method of P-type IBC battery |
-
2022
- 2022-07-15 CN CN202210854522.2A patent/CN115207136A/en active Pending
-
2023
- 2023-06-19 WO PCT/CN2023/101137 patent/WO2024012162A1/en unknown
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN210926046U (en) * | 2019-10-29 | 2020-07-03 | 苏州阿特斯阳光电力科技有限公司 | Solar cell |
| CN113921625A (en) * | 2021-09-30 | 2022-01-11 | 泰州隆基乐叶光伏科技有限公司 | Back contact battery and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024012162A1 (en) * | 2022-07-15 | 2024-01-18 | 青海黄河上游水电开发有限责任公司西宁太阳能电力分公司 | Manufacturing method for p-type ibc battery |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024012162A1 (en) | 2024-01-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110518088B (en) | Preparation method of SE solar cell | |
| CN111564503B (en) | Back-junction back-contact solar cell structure and preparation method thereof | |
| US8664015B2 (en) | Method of manufacturing photoelectric device | |
| WO2010064303A1 (en) | Method for manufacturing solar battery cell | |
| CN108666376B (en) | P-type back contact solar cell and preparation method thereof | |
| CN111540794A (en) | P-type passivation contact solar cell and manufacturing method thereof | |
| WO2023093604A1 (en) | Solar cell and preparation method for solar cell | |
| JP2013516081A (en) | Manufacturing method of back electrode type solar cell | |
| JP2013165160A (en) | Method for manufacturing solar cell, and solar cell | |
| CN113644142A (en) | Solar cell with passivation contact and preparation method thereof | |
| WO2024066207A1 (en) | New solar cell and fabrication method therefor | |
| CN116525697A (en) | Back contact type solar cell and preparation method thereof | |
| CN112382672A (en) | PERC double-sided solar cell and manufacturing method thereof | |
| CN112133774A (en) | Back-junction back-contact solar cell and manufacturing method thereof | |
| WO2024012162A1 (en) | Manufacturing method for p-type ibc battery | |
| WO2022156101A1 (en) | Solar cell stack passivation structure and preparation method therefor | |
| CN114050105A (en) | TopCon battery preparation method | |
| CN114725225A (en) | Efficient P-type IBC battery and preparation method thereof | |
| CN117457797A (en) | Preparation method and application of TOPCON battery structure | |
| JP5817046B2 (en) | Manufacturing method of back contact type crystalline silicon solar cell | |
| CN111584685A (en) | Novel solar cell and preparation method thereof | |
| CN115692516A (en) | Novel TOPCON battery and manufacturing method thereof | |
| CN216597603U (en) | Back contact heterojunction solar cell capable of improving insulation and isolation effects | |
| CN116741850A (en) | Solar cell and photovoltaic module | |
| KR20120129016A (en) | Bifacial Photovoltaic Localized Emitter Solar Cell and Method for Manufacturing Thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |